EP2136350A2 - Affichage à plasma et son procédé de commande - Google Patents

Affichage à plasma et son procédé de commande Download PDF

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Publication number
EP2136350A2
EP2136350A2 EP09161941A EP09161941A EP2136350A2 EP 2136350 A2 EP2136350 A2 EP 2136350A2 EP 09161941 A EP09161941 A EP 09161941A EP 09161941 A EP09161941 A EP 09161941A EP 2136350 A2 EP2136350 A2 EP 2136350A2
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EP
European Patent Office
Prior art keywords
voltage
electrodes
period
sustain
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09161941A
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German (de)
English (en)
Other versions
EP2136350A3 (fr
Inventor
Sang-Chul Han
Jung-Soo An
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Samsung SDI Co Ltd
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Samsung SDI Co Ltd
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Publication date
Application filed by Samsung SDI Co Ltd filed Critical Samsung SDI Co Ltd
Publication of EP2136350A2 publication Critical patent/EP2136350A2/fr
Publication of EP2136350A3 publication Critical patent/EP2136350A3/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/294—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/293—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for address discharge
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G09G3/2965—Driving circuits for producing the waveforms applied to the driving electrodes using inductors for energy recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0216—Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing

Definitions

  • the field relates to a plasma display and a method of driving the same.
  • a plasma display is a display device that uses a plasma display panel (PDP) that displays characters or images using plasma that is generated by a gas discharge.
  • PDP plasma display panel
  • a plurality of cells are arranged substantially in a matrix form.
  • the plasma display divides one frame into a plurality of subfields each having a corresponding weight, and drives the plurality of subfields to display an image.
  • each subfield includes a reset period, an address period, and a sustain period.
  • the reset period the cells are initialized.
  • a scan pulse is sequentially applied to a plurality of scan electrodes to select cells that will emit light (hereinafter referred to as "on-cells") and cells that will not emit light (hereinafter referred to as "off-cells").
  • a sustain pulse that alternately has a high level voltage and a low level voltage is applied to display electrodes to perform sustain-discharges in cells selected to emit light, in order to display an image.
  • An address display period separation (ADS) method may be used to address- and sustain-discharge the cells.
  • ADS method after an address operation is performed for all the cells in the address period, a sustain-discharge operation is performed for all the cells in the sustain period. That is, the address period is separated from the sustain period.
  • the sustain-discharge operation is performed after an address operation is performed by sequentially applying a scan pulse to a plurality of scan electrodes for forming the cells. Accordingly, some scan electrodes to which the address operation is initially performed are sustain-discharged after the scan pulse is applied to all the scan electrodes is performed.
  • a sustain pulse alternately having a high level voltage and a low level voltage may be applied to one display electrode while a ground voltage is applied to another display electrode in a sustain period. In this case, the ground voltage is applied to the one display electrode to perform a next operation.
  • a switch for transmitting the ground voltage is fabricated as back-to-back transistors, cost of the driving circuit is increased.
  • One aspect is a method of driving a plasma display including a plurality of first electrodes, a plurality of second electrodes, and a plurality of cells formed by the first electrodes and the second electrodes.
  • the method includes dividing the plurality of first electrodes into a plurality of groups including a first group and a second group, addressing on-cells and off-cells with the first group of electrodes in a first address period, sustain-discharging the on-cells of the first group in a first sustain period, where the sustain period is subsequent to the first address period, and addressing on-cells and off-cells with the second group of electrodes in a second address period, where the second address period is subsequent to the first sustain period.
  • Sustain-discharging the on-cells of the first group includes applying a first voltage to the plurality of first electrodes while applying a reference voltage to the plurality of second electrodes during a first period, the first voltage being higher than the reference voltage, applying a second voltage to the plurality of first electrodes while applying the reference voltage to the plurality of second electrodes during a second period subsequent to the first period, the second voltage being lower than the reference voltage, increasing the voltage at the plurality of first electrodes from the second voltage to a third voltage during a third period subsequent to the second period, the third voltage being higher than the second voltage, floating the plurality of first electrodes during a fourth period subsequent to the third period, applying a fourth voltage to the plurality of second electrodes while floating the plurality of first electrodes, the fourth voltage being higher than the reference voltage, and gradually decreasing the voltage at the plurality of first electrodes to a fifth voltage during a fifth period subsequent to the fourth period, the fifth voltage being lower than the reference voltage.
  • a plasma display including a plurality of first electrodes, a plurality of second electrodes, a plurality of cells formed near the plurality of first electrodes and the plurality of second electrodes, a first driver configured to increase a voltage at the plurality of first electrodes from a first voltage to a second voltage during a first period, float the plurality of first electrodes during a second period subsequent to the first period, and gradually decrease the voltage at the plurality of first electrodes to a third voltage during a third period subsequent to the second period, and a second driver configured to apply a fourth voltage to the plurality of second electrodes during the first period, apply a fifth voltage to the plurality of second electrodes during the second period, and apply a sixth voltage to the plurality of second electrodes during the third period, the fourth voltage being higher than the first voltage and the fifth voltage being higher than the fourth voltage.
  • Another aspect is a method of driving a plasma display including a plurality of first electrodes, a plurality of second electrodes, and a plurality of cells formed near the plurality of first electrodes and the plurality of second electrodes.
  • the method includes increasing a voltage at the plurality of first electrodes from a first voltage to a second voltage while applying a third voltage to the plurality of second electrodes during a first period, floating the plurality of first electrodes during a second period subsequent to the first period, applying a fourth voltage to the plurality of second electrodes while floating the plurality of first electrodes, the fourth voltage being higher than the third voltage, and gradually decreasing the voltage at the plurality of first electrodes to a fifth voltage during a third period subsequent to the second period.
  • FIG. 1 is a schematic block diagram of a plasma display according to an embodiment.
  • FIG. 2 is a schematic drawing showing a plasma display according to an embodiment.
  • FIG. 3 is a schematic drawing showing driving waveforms of a plasma display according to an embodiment.
  • FIG. 4 is a schematic diagram of driving circuits of a plasma display according to an embodiment.
  • FIG. 5 is a timing diagram of a driving waveform shown in FIG. 3 .
  • FIG. 6 to FIG. 8 are diagrams showing operations of driving circuits shown in FIG. 4 according to timing shown in FIG. 5 .
  • wall charges described in this specification indicate charges that are formed adjacent to each electrode on a wall (e.g., a dielectric layer) of a cell. Wall charges may not actually contact an electrode, however in this specification, it is described that wall charges are “formed,” “accumulated,” or “stacked” in or on the electrode, and a wall voltage indicates a potential difference that is formed in a wall of a cell by the wall charges.
  • FIG. 1 is a schematic block diagram of a plasma display according to an embodiment.
  • a plasma display includes a PDP 100, a controller 200, an address electrode driver 300, a scan electrode driver 400, and a sustain electrode driver 500.
  • the PDP 100 includes a plurality of display electrodes Y1 to Yn and X1 to Xn, a plurality of address electrodes (hereinafter referred to as "A electrodes") A1 to Am, and a plurality of cells 110.
  • a electrodes a plurality of address electrodes
  • Y1 to Yn are scan electrodes (hereinafter referred to as "Y electrodes")
  • X1 to Xn are sustain electrodes (hereinafter referred to as "X electrodes”).
  • the Y electrodes Y1 to Yn and the X electrodes X1 to Xn extend substantially in a row direction and substantially form parallel pairs of Y and X electrodes.
  • the A electrodes A1 to Am extend substantially in a column direction crossing the row direction and are substantially parallel to each other.
  • Each of the Y electrodes Y1 to Yn may correspond to one of the X electrodes X1 to Xn.
  • each of the Y electrodes Y1 to Yn corresponds to two or more of the X electrodes X1 to Xn.
  • Cells 110 are formed in spaces near the crossings of the A electrodes A1 to Am, the Y electrodes Y1 to Yn, and the X electrodes X1 to Xn.
  • the above-described PDP 100 is only one example, and the PDP 100 may have another structure.
  • the controller 200 receives a video signal and an input control signal for controlling the display of the video signal.
  • the video signal includes luminance information of each of the cells 110, and the luminance of each of the cells 110 may be represented as one of a number of gray levels.
  • the input control signal may include a vertical synchronization signal and a horizontal synchronization signal.
  • the controller 200 divides one frame into a plurality of subfields, each of which has a weight.
  • the controller 200 processes the video signal and the input control signal based on the plurality of subfields, and generates an A electrode driving control signal, a Y electrode driving control signal, and an X electrode driving control signal.
  • the controller 200 outputs the A electrode driving control signal to the address electrode driver 300, the Y electrode driving control signal to the scan electrode driver 400, and the X electrode driving control signal to the sustain electrode driver 500.
  • the address electrode driver 300 applies driving voltages to the A electrodes A1 to Am in accordance with the A electrode driving control signal.
  • the scan electrode driver 400 applies driving voltages to the Y electrodes Y1 to Yn in accordance with the Y electrode driving control signal.
  • the sustain electrode driver 500 applies driving voltages to the X electrodes X1 to Xn in accordance with the X electrode driving control signal.
  • FIG. 2 is a schematic drawing showing a driving method of a plasma display according to an embodiment.
  • each subfield SF includes a reset period, a mixed address/sustain period T1, a brightness compensation period T2, and a common sustain period T3.
  • the Y electrodes Y1 to Yn are divided into a number of groups G1 to Gk according to their physical locations. For example, the Y electrodes Y1 to Yn/k form the first group G1, and the Y electrodes Yn/k+1 to Y2n/k form the second group G2. Similarly, the Y electrodes Y(k-1)n/k+1 to Yn form the k-th group Gk.
  • the mixed address/sustain period T1 includes a plurality of address periods corresponding to the groups G1 to Gk and a plurality of sustain periods corresponding to the groups G1 to Gk. That is, in the mixed address/sustain period T1, the address periods and the sustain periods are mixed. Accordingly, each address/sustain period T1 has an address portion and a sustain portion.
  • each address portion on-cells and off-cells are selected among the cells of the group being addressed.
  • on-cells of the groups G1 to Gk are sustain-discharged.
  • the brightness compensation period T2 variation in brightness is compensated in the on-cells of the groups G1 to Gk.
  • the common sustain period T3 is a period that sustain-discharges the on-cells of the groups G1 to Gk in common for a predetermined time.
  • the cells of the groups G1 to Gk are initialized to off-cells in the reset period R1.
  • the cells of the groups G1 to Gk may not simultaneously be initialized in the reset period R1, and a plurality of reset periods corresponding to the groups G1 to Gk may be used. In this case, each reset period may be executed just prior to the address period of a corresponding group.
  • an address operation is performed on the cells of the first group G1 during address period AG1 to select the on-cells, and subsequently a sustain-discharge operation is performed to sustain-discharge the on-cells of the first group G1 during sustain period S11.
  • an address operation is performed on cells of the second group G2 during address period AG2 to select the on-cells, which is followed by a sustain-discharge operation that is performed to sustain-discharge the on-cells of the first and second groups G1 and G2 during the sustain period S12/S21.
  • an address operation is performed to select the on-cells in the third group G3 during the address period AG3, and again a sustain-discharge operation is performed to sustain-discharge the on-cells of the groups G1, G2, and G3 during the sustain period Sl3/S22/S31.
  • an address operation is performed to select the on-cells in the k-th group Gk in the address period AGk, and a sustain-discharge operation is performed during the sustain period S1k/S2(k-1)/S3(k-2)/.../Sk1 to sustain-discharge the on-cells in the groups G1 to Gk. Accordingly, in the address/sustain mixed period T1, the on-cells of the group having just been addressed, and the on-cells of the groups having previously been addressed are sustain discharged together.
  • the number of sustain-discharge operations for the cells of each group may vary, which leads to corresponding variance in brightness of the groups G1 to Gk.
  • the brightness compensation period T2 is performed so as to correct the brightness differences of the respective groups.
  • the sustain-discharge operations are performed so that the same number of sustain-discharges are generated in the on-cells for each of the groups G1 to Gk.
  • a sustain-discharge operation is performed during a sustain period S2k/S3(k-1)/.../Sk2 to sustain-discharge the on-cells of the groups G2 to G4 while the on-cells of the group G1 are not sustain-discharged.
  • a sustain-discharge operation is performed to sustain-discharge the on-cells of the groups G3 to Gk during a sustain period S3k/.../Sk3 while the on-cells of the groups G1 and G2 are not sustain-discharged.
  • a sustain-discharge operation is performed to sustain-discharge the on-cells of the k-th group Gk during a sustain period Skk while the on-cells of the groups G1-Gk-1 are not sustain-discharged. Accordingly, the same number of sustain-discharges are generated for each of the groups over one subfield so that the on-cells of the groups G1 to Gk can have the same brightness in the same subfield.
  • a sustain-discharge operation is performed for a time to sustain-discharge the on-cells of all of the groups G1 to Gk. Weights of corresponding subfields are set by controlling the length of the common sustain period T3. After the common sustain period T3 ends, the reset period of the next subfield starts.
  • the common sustain period T3 is performed after the brightness compensation period T2.
  • the common sustain period T3 may be performed between the mixed address/sustain period T1 and the brightness compensation period T2.
  • the common sustain period T3 is not performed when the weight of the corresponding subfield is satisfied by the sustain-discharge operation provided in the mixed address/sustain period T1 and the brightness compensation period T2.
  • FIG. 3 is a timing diagram showing driving waveforms of a plasma display according to an embodiment. It is shown for ease of description in FIG. 3 that the Y electrodes Y1 to Yn are grouped into two groups G1 and G2, and the Y electrodes of the first group G1 are denoted as Yg1 and the Y electrodes of the second group G2 are denoted as Yg2. In addition, a driving waveform applied to the A electrodes is not shown in FIG. 3 .
  • a voltage at the Y electrodes Yg1 and Yg2 of the first and second groups G1 and G2 is gradually increased from a voltage of (VscH-VscL), which is the difference between a voltage of VscH and a voltage of VscL, to a voltage of [Vs+(VscH-VscL)], which is a sum of a voltage of Vs and the voltage of (VscH-VscL), while a reference voltage (0V of FIG. 3 ) is applied to the X electrodes.
  • the voltage at the Y electrodes may be gradually increased from a voltage that is different from the voltage of (VscH-VscL), and may be gradually increased to a voltage that is different from the voltage of [Vs+(VscH-VscL)]. While the voltage at the Y electrode Yg1 and Yg2 is gradually increased, weak reset discharges are generated in the cells of the first and second groups G1 and G2 such that wall charges are formed on the cells of the first and second groups G1 and G2.
  • the voltage at the Y electrodes Yg1 and Yg2 is gradually decreased from the voltage of (VscH-VscL) to a voltage of Vnf while a voltage of Ve is applied to the X electrodes.
  • the voltage at the Y electrodes may be gradually decreased from a voltage that is different from the voltage of (VscH-VscL).
  • weak reset discharges are generated in the cells of the first and second groups G1 and G2 such that the wall charges formed on the cells of the first and second groups G1 and G2 are erased.
  • the cells of the first and second groups G1 and G2 are initialized to be off-cells.
  • the voltage of (Vnf-Ve) may be similar to a discharge firing voltage between the Y electrode and the X electrode.
  • a wall voltage between the Y electrode and the X electrode is approximately 0V such that the off-cells can be prevented from being discharged in the sustain period.
  • a scan pulse having a voltage of VscL is sequentially applied to the Y electrodes Yg1 of the first group G1 while the voltage of Ve is applied the X electrodes and a voltage of VscH that is higher than the voltage of VscL is applied to the Y electrodes Yg2 of the second group G2.
  • the voltage of VscL may be equal to or lower than the voltage of Vnf.
  • An address pulse having a positive voltage (not shown) is applied to the A electrode of a cell that will be set to the on-cell among the cells of the first group G1 formed by the Y electrode receiving the scan pulse. Then, an address discharge is generated in the cell of the first group G1 receiving the scan pulse and the address pulse. As a result, positive wall charges are formed on the Y electrode, and negative wall charges are formed on the X and A electrodes such the on-cell is set.
  • the voltage of VscH is applied to the Y electrodes not receiving the scan pulse, and the reference voltage is applied to the A electrodes not receiving the address pulse.
  • a sustain pulse alternately having the voltage of Vs and a voltage of -Vs is applied to the Y electrodes Yg1 and Yg2 of the first and second groups G1 and G2, and the reference voltage is applied to the X electrodes.
  • the voltage of -Vs may be equal to the voltage of VscL.
  • a sustain pulse is applied once to the Y electrodes Yg1 and Yg2, i.e., each of the voltage of Vs and the voltage of -Vs is applied once to the Y electrodes.
  • the sustain-discharge is generated twice in the on-cells of the first group G1.
  • negative wall charges are formed on the Y electrodes of the on-cells of the first group G1 and positive wall charges are formed on the X electrodes of the on-cells of the first group G1 by the sustain-discharge according the voltage of Vs.
  • positive wall charges are formed on the Y electrodes of the on-cells of the first group G1 and negative wall charges are formed on the X electrodes of the on-cells of the first group G1 by the sustain-discharge according the voltage of -Vs.
  • the sustain-discharge is not generated in the cells of the second group G2.
  • the wall charge state of the cells in the second group G2 may be different from the wall charge state set in the reset period R1 by the sustain-discharge generated in the on-cells of the first group G1.
  • the voltage at the Y electrodes is gradually decreased to the voltage of Vnf after the sustain-discharges in the sustain period S11.
  • a weak discharge is generated in the cells of the second group G2 such that the cells of the second group G2 are initialized again.
  • the scan pulse having the voltage of VscL is sequentially applied to the Y electrodes Yg2 of the second group G2 while the voltage of Ve is applied to the X electrodes and the voltage of VscH is applied to the Y electrodes Yg1 of the first group G1.
  • the address pulse having the positive voltage is applied to the A electrode of a cell that will be set to the on-cell among the cells of the second group G2 formed by the Y electrode receiving the scan pulse.
  • an address discharge is generated in the cell of the second group G2 receiving the scan pulse and the address pulse.
  • positive wall charges are formed on the Y electrode, and negative wall charges are formed on the X and A electrodes such that the on-cell is set in the second group G2.
  • the sustain pulse alternately having the voltage of Vs and the voltage of -Vs is applied to the Y electrodes Yg1 and Yg2 of the first and second groups G1 and G2 while the reference voltage is applied to the X electrodes. Since the positive wall charges are formed on the Y electrodes and the negative wall charges are formed on the X electrodes in the on-cells of the first groups G1 as well as on-the cells of the second group G2 when the voltage of Vs is applied to the Y electrodes Yg1 and Yg2, the sustain-discharge is generated in the on-cells of the first and second groups G1 and G2.
  • the negative wall charges are formed on the Y electrodes and positive wall charges are formed on the X electrodes, in the on-cells of the first and second groups G1 and G2.
  • positive wall charges are formed on the Y electrodes and negative wall charges are formed on the X electrodes, by the sustain-discharge according the voltage of -Vs. Accordingly, the number of sustain-discharges is "2" in the on-cells of the second group G2, but the number of sustain-discharges is "4" in the on-cells of the first group G1.
  • the brightness compensation period T2 is performed to set the number of sustain-discharges in the first group G1 to be equal to the number of sustain-discharges in the second group G2.
  • the voltage of -Vs is applied to the Y electrodes Yg1 of the first group G1 and the voltage of Vs is applied to the Y electrodes Yg2 of the second group G2 while the reference voltage is applied to the X electrodes.
  • the sustain-discharge is generated in the on-cells of the second group G2 such that the negative wall charges and the positive wall charges are respectively formed on the Y electrodes and the X electrodes in the second group G2.
  • the sustain-discharge is not generated in the on-cells of the first group G1 since the voltage -Vs applied to the Y electrodes is lower than the reference voltage applied to the X electrodes.
  • the positive wall charges on the Y electrodes and the negative wall charges on the X electrode are maintained in the first group G1.
  • the voltage of - Vs is applied to the Y electrodes Yg2 of the second group G2 while the reference voltage and the voltage of -Vs are respectively applied to the X electrodes and the Y electrodes of the first group G1.
  • the sustain-discharge is generated in the on-cells of the second group G2 such that the positive wall charges and the negative wall charges are respectively formed on the Y electrodes and the X electrodes in the second group G2.
  • the sustain-discharge is not generated in the on-cells of the first group G1 since the voltage of -Vs applied to the Y electrodes is lower than the reference voltage applied to the X electrodes.
  • the positive wall charges on the Y electrodes and the negative wall charges on the X electrode are maintained in the first group G1.
  • the sustain-discharges are generated twice in the on-cells of the second group G2 in the brightness compensation period T2 such that the number of sustain-discharges in the first group G1 becomes equal to the number of sustain-discharges in the second group G2.
  • the brightness compensation period T2 may be performed by applying the voltage of Vs to the Y electrodes Yg1 of the first group G1 when the voltage of -Vs is applied to the Y electrodes Yg2 of the second group G2.
  • the common sustain period T3 the voltage of Vs and the voltage of -Vs are further applied to the Y electrodes Yg1 and Yg2 while the reference voltage is applied to the X electrodes.
  • the on-cells of the first and second groups G1 and G2 are additionally sustain-discharged. As described above, the common sustain period T3 may be omitted.
  • a plurality of Y electrodes Y1 to Yn are divided into groups G1 to Gk, and the operation of the sustain period is performed between the two adjacent address periods.
  • a time provided between the address discharge and the sustain-discharge is reduced to generate a stable sustain-discharge.
  • the voltage at the Y electrodes is gradually decreased to the voltage of Vnf after the sustain-discharge is performed in the sustain period S11 such that the wall charge state of the second group G2 can be compensated.
  • the address discharge can be stably generated in the address period AG2 for the second group G2.
  • FIG. 4 is a schematic diagram of a driving circuit of a plasma display according to an embodiment.
  • switches are n-channel field effect transistors, and each n-channel field effect transistors may have a body diode having an anode coupled to a source and a cathode coupled to a source.
  • other types of transistors may be used as the switches.
  • each transistor is shown as one transistor in FIG. 3 , but each transistor may be formed by a plurality of transistors coupled in parallel.
  • one of the X electrodes X1 to Xn and one of the Y electrodes Y1 to Yn are shown in FIG. 3 , and a capacitive component formed by the X electrode and the Y electrode is shown as a panel capacitor.
  • a driving circuit of a scan electrode driver 400 includes an inductor L, transistors Yr, Yf, Ys1, Ys2, Yfr, and YscL, a Zener diode ZD, a capacitor CscH, a diode DscH, and a scan circuit 410.
  • the scan circuit 410 has two input terminals and an output terminal, and includes transistors Sch and Scl.
  • a plurality of scan circuits 410 that correspond to the plurality of Y electrodes Y1 to Yn are formed, but one scan circuit 410 corresponding to one Y electrode is shown in FIG. 3 .
  • a number of scan circuits 410 may be formed as one integrated circuit.
  • a source of the transistor Sch and a drain of the transistor Scl are coupled to the output terminal of the scan circuit 410, and the output terminal is coupled to the Y electrode.
  • a source of the transistor Scl is coupled to one input terminal of the scan circuit 410, which is coupled to one terminal of the capacitor CscH.
  • a drain of the transistor Sch is coupled to another input terminal of the scan circuit 410, which is coupled to a terminal of the capacitor CscH.
  • a source of the transistor YscL is coupled to a power source for supplying the voltage of VscL, and a drain of the transistor YscL is coupled to the Y electrode via one input terminal of the scan circuit 410.
  • a power source for supplying the voltage of VscH is coupled to another terminal of the capacitor CscH via a diode DscH.
  • the transistor YscL When the transistor YscL is turned on, the voltage of (VscH-VscL) may be charged to the capacitor CscH.
  • the transistor YscL In the address period, the transistor YscL is turned on, and one of the transistors Sch and Scl of the scan circuit 410 is turned on.
  • the transistor Sch is turned on, the voltage of VscH is applied to the Y electrode by the capacitor CscH and the power source VscL.
  • the voltage of VscH may be applied to the Y electrode by the power source VscH.
  • either the power source VscH or the combination of the capacitor CscH and the power source VscL act as a power source for supplying the voltage of VscH to the Y electrodes.
  • the transistor Scl when the transistor Scl is turned on, the voltage of VscL is applied to the Y electrode.
  • One terminal of the inductor L is coupled to a power source for supplying the reference voltage, for example a ground terminal, and the other terminal of the inductor L is coupled to the Y electrode via the transistors Yr and Yf and one input terminal of the scan circuit 410.
  • the drain of the transistor Yr is coupled to a terminal of the inductor L, and the source of the transistor Yr is coupled to a source of the transistor Yf.
  • the drain of the transistor Yf is coupled to the Y electrode via one input terminal of the scan circuit 410.
  • the drain of the transistor Ys1 is coupled to a power source for supplying the voltage of Vs, and the source of the transistor Ys1 is coupled to the Y electrode via an input terminal of the scan circuit 410.
  • the source of the transistor Ys2 is coupled to a power source for supplying the voltage of -Vs, and the drain of the transistor Ys2 is coupled to the Y electrode via one input terminal of the scan circuit 410.
  • the transistor Ys1 is turned on to apply the voltage of Vs to the Y electrode, and the transistor Ys2 is turned on to apply the voltage of -Vs to the Y electrode.
  • the source of the transistor Yfr is coupled to a power source for supplying the voltage of VscL
  • the drain of the transistor Yfr is coupled to an anode of the Zener diode Zd
  • the cathode of the Zener diode ZD is coupled to the Y electrode via one input terminal of the scan circuit 410.
  • the Zener diode ZD may be coupled between the source of the transistor Yfr and the power source.
  • the transistor Yfr is operated to gradually decrease the voltage at the Y electrode.
  • the breakdown voltage of the Zener diode is the difference between the voltage of Vnf and the voltage of VscL.
  • the transistor Yfr may be coupled between a power source for supplying the voltage of Vnf and the Y electrode without the Zener diode ZD.
  • a current path including the power source VscL, the body diode of the transistor Yfr/YscL, the transistor Ys2, and the power source -Vs may be formed when the transistor Ys2 is turned on.
  • a diode or a transistor may be formed in the current path.
  • a driving circuit of the sustain electrode driver 500 includes transistors Xe and Xg.
  • the drain of the transistor Xe is coupled to a power source for the voltage of Ve, and the source of the transistor Xe is coupled to the X electrode.
  • the source of the transistor Xg is coupled to a power source for supplying the reference voltage, for example the ground terminal, and the drain of the transistor Xg is coupled to the X electrode.
  • the transistor Xe is turned on to apply the voltage of Ve to the X electrode, and the transistor Xg is turned on to apply the reference voltage to the X electrode.
  • the transistors Ys1 and Ys2 may be coupled to one input terminal of the scan circuits 410 for the Y electrodes Yg2 of the second group G2.
  • additional transistors for applying the voltages of Vs and -Vs may be coupled to one input terminal of the scan circuits 410 for the Y electrodes Yg1 of the first group G1.
  • a method of generating the driving waveforms shown in FIG. 3 using the driving circuits of FIG. 4 will be described with reference to FIG. 5 to FIG. 8 .
  • driving waveforms applied in the sustain period S11 will be described. Since the same driving waveforms are applied to the Y electrodes Yg1 and Yg2 of the first and second groups G1 and G2 in the sustain period S11, the driving waveform applied to one of the Y electrodes will be described.
  • FIG. 5 is a timing diagram of a driving waveform shown in FIG. 3
  • FIG. 6 to FIG. 8 are diagrams showing operations of driving circuits shown in FIG. 4 according to timing shown in FIG. 5 .
  • the transistor Sch is turned on such that the Y electrode is maintained at the voltage of VscH.
  • a period TA1 the transistors Xe and Sch are turned off, and the transistors Yr, Scl, and Xg are turned on. Accordingly, the reference voltage is applied to the X electrode.
  • a resonance is generated between the inductor L and the panel capacitor in a current path P1 including the inductor L, the transistor Yr, the body diode of the transistor Yfr, the body diode of the transistor Scl, and the Y electrode of the panel capacitor.
  • the voltage at the Y electrode is increased from the voltage of VscH to almost the voltage of Vs due to the resonance.
  • a current path P2 including the power source Vs, the transistor Ys1, the transistor Scl, and the Y electrode of the panel capacitor is formed.
  • the voltage of Vs is applied to the Y electrode through the current path P2.
  • a resonance is generated between the inductor L and the panel capacitor in a current path P3 including the Y electrode of the panel capacitor, the transistor Scl, the transistor Yf, the transistor Yr, the inductor L, and the ground terminal.
  • the voltage at the Y electrode is decreased from the voltage of Vs to almost the voltage of -Vs due to the resonance.
  • a current path P4 including the Y electrode of the panel capacitor, the transistor Scl, the transistor Ys2, and the power source -Vs is formed.
  • the voltage of -Vs is applied to the Y electrode through the current path P4.
  • the voltage at the Y electrode is increased from the voltage of -Vs to a voltage of V1 while the reference voltage is applied to the X electrode.
  • the voltage of V1 may be equal to the voltage of VscH to not use an additional power source for supplying the voltage of V1 and an additional transistor for transmitting the voltage of V1.
  • the transistors YscL and Sch are turned on, and the transistors Scl and Ys2 are turned off.
  • a current path P5 including the power source VscL, the transistor YscL, the capacitor CscH, the transistor Sch, and the Y electrode is formed.
  • the voltage at the Y electrode is increased to the voltage of VscH through the current path P5.
  • the Y electrode is floated, and a voltage of V2 that is higher than the reference voltage is applied to the X electrode.
  • the voltage of V2 may be lower than the voltage of Vs to prevent the on-cells from being discharged.
  • the voltage of V2 voltage may be equal to the voltage of Ve to not use an additional power source for supplying the voltage of V2 and an additional transistor for transmitting the voltage of V2.
  • the transistor YscL is turned off, and the scan circuit 410 floats the Y electrode.
  • the transistors Sch and Scl of the scan circuit 410 are both turned off.
  • the transistor Xe is turned on while the Y electrode is floated.
  • the voltage at the X electrode is increased to the voltage of Ve from the reference voltage through a current path P6 including the power source Ve, the transistor Xe, and the X electrode.
  • the voltage at the floated Y electrode is also increased by the increase of the voltage at the X electrode. That is, the voltage at the Y electrode is increased to a voltage near the reference voltage while the Y electrode is floated.
  • the voltage at the Y electrode is near the reference voltage without using a transistor for transmitting the reference voltage.
  • a current path P7 including the Y electrode of the panel capacitor, the transistor Scl, the Zener diode ZD, the transistor Yfr, and the power source VscL is formed.
  • the voltage at the Y electrode is gradually decreased to the voltage of Vnf through the current path P7.
  • the voltage at the Y electrode is gradually decreased to the voltage of Vnf from the voltage near the reference voltage. Therefore, although the wall charge state of the on-cells of the second group G2 becomes unstable by the sustain-discharge of the first group, it can be compensated. As a result, the address discharge can be stably generated in the address period AG2 for the second group G2.
  • the transistor for transmitting the reference voltage to the Y electrode can be omitted.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)
EP09161941A 2008-06-17 2009-06-04 Affichage à plasma et son procédé de commande Withdrawn EP2136350A3 (fr)

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KR1020080056875A KR20090131090A (ko) 2008-06-17 2008-06-17 플라즈마 표시 장치 및 그의 구동 방법

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CN101727823B (zh) * 2008-12-30 2011-10-12 四川虹欧显示器件有限公司 用于等离子显示器的维持电极驱动电路和驱动方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1748407A1 (fr) * 2005-07-28 2007-01-31 LG Electronics Inc. Dispositif d'affichage à plasma et son procédé de commande
EP1777683A2 (fr) * 2005-10-18 2007-04-25 Samsung SDI Co., Ltd. Procédé de commande de panneau d'affichage à plasma

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1748407A1 (fr) * 2005-07-28 2007-01-31 LG Electronics Inc. Dispositif d'affichage à plasma et son procédé de commande
EP1777683A2 (fr) * 2005-10-18 2007-04-25 Samsung SDI Co., Ltd. Procédé de commande de panneau d'affichage à plasma

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