EP2127499B1 - Circuit configuration for controlling at least one fluorescent lamp - Google Patents

Abstract

A circuit configuration for controlling at least one fluorescent lamp is disclosed, wherein the circuit configuration comprises the following characteristics: (i) a half-bridge inverter having at least one downstream load circuit, (ii) at least one coupled capacitor connected to the load circuit and to the half-bridge inverter, (iii) a control device for the half-bridge inverter, the load circuit having connections for at least one fluorescent lamp, (iv) a detector circuit comparing a first voltage to a reference voltage and generating an output signal for actuating the half-bridge inverter based on at least two comparators, wherein the first voltage corresponds to a voltage drop at the at least one coupled capacitor or to a voltage drop modified by a voltage divider at the at least one coupled capacitor.

Description

The invention relates to a circuit arrangement for controlling at least one fluorescent lamp.

A possible cause of failure of fluorescent lamps is a reduced emissivity of the electrodes (so-called "end-of-life" effect). This effect occurs at the end of the life of a fluorescent lamp on one of the two electrodes. As a result, the discharge current through the lamp flows more easily in one direction than in the opposite direction. The fluorescent lamp works in this case as a rectifier. In doing so, the emission-impoverished electrode heats up so much that high temperatures can occur at the lamp surface. In extreme cases, the glass bulb can melt in fluorescent lamps of small diameter.

An electronic ballast (ECG) to control the fluorescent lamp must detect this one such fault in time and either limit output current and output voltage to a non-critical value or turn off the fluorescent lamp. Such a ballast is from the Scriptures DE 20 2005 13675U1 known. In the case of fluorescent lamps with a high lamp current, a limit value of an asymmetrical power is already achieved with a very small recharge of a coupling capacitor by approx. 10% of the normal value; in the case of an electronic ballast with two lamps connected in parallel and a common coupling capacitor, this transhipment is halved to a value of approx. 5% of the normal value. The end-of-life detector therefore has to be adjusted sensitively can cause false alarms without causing interference.

WO 00/11916 uses as a detector two transistors whose base is connected to the emitter of the other transistor. The transistors determine a voltage window within which the detector does not become active. A problem in WO 00/11916 is the significant temperature coefficient of the base-emitter threshold, which affects the width of the voltage window, thus preventing sensitive adjustment of the circuit.

WO 97/43879 shows a circuit with two voltage comparators, which compare an input voltage with a fixed voltage window. Since the voltage at the coupling capacitor but not only depends on a possible rectification of the lamp, but also from the DC link voltage, deviations of the DC link voltage from the normal value can lead to false triggering. Such deviations occur when switching on the electronic ballast, but also in network interruptions, Netzunter- or network overvoltages and thus complicate a sensitive detector setting.

The object of the invention is to avoid the disadvantages mentioned above and in particular to specify a sensitive adjustable circuit arrangement with variably adjustable detection range.

This object is achieved according to the features of the independent claims. Further developments of the invention will become apparent from the dependent claims.

To solve the problem, a circuit arrangement for operating at least one fluorescent lamp, according to claim 1 is proposed.

The detector circuit proposed in this case is particularly suitable for implementation in an integrated circuit because any tolerances of associated voltage divider resistors largely compensate each other. Another advantage is that for such an integrated solution, significantly higher sensitivity, i. a smaller detection window width can be set.

It is a development that deviations of a DC link voltage from a predetermined value can be compensated. In this case, the predetermined value is in particular a normal value.

One embodiment is that the reference voltage corresponds to a voltage drop across a further coupling capacitor or to a voltage drop on the further coupling capacitor modified by a voltage divider. In particular, such a circuit arrangement is suitable for driving two fluorescent lamps.

It is also an embodiment that a window width of the detector circuit is adjustable by an external signal. For this purpose, the detector circuit preferably has a further connection via which the external signal is made available to the detector circuit.

Advantageously, the sensitivity of the detector circuit can be reduced by a resistor provided between the two voltage inputs of the detector circuit.

Another advantage is flexible usability of the detector circuit, in particular based on its symmetrical structure comprising the electrically equal voltage inputs.

An additional development is that the activation device comprises a shutdown device which switches off the half-bridge inverter when an abnormal operating state occurs. In this case, the abnormal operating state may in particular be a fault of the fluorescent lamp.

The shutdown device can be implemented in the drive device, i. The switching off of the fluorescent lamp takes place by the activation of the half-bridge inverter is omitted.

An embodiment consists in that the reference voltage is formed by a voltage divider which is connected in parallel to a DC voltage input of the half-bridge inverter, wherein the voltage divider has a tap at which the reference voltage is available.

A further embodiment is that the circuit arrangement in an electrical ballast is used and / or an electrical ballast comprises the described circuit.

Furthermore, it is an embodiment that the circuit arrangement can be used for end-of-life detection and for switching off the fluorescent lamp.

Embodiments of the invention are illustrated and explained below with reference to the drawings.

Fig.1

eine Schaltungsanordnung zum Betrieb einer Leuchtstofflampe;

Fig.2

eine Schaltungsanordnung zum Betrieb zweier Leuchtstofflampen;

Fig.3

eine Detektorschaltung mit drei Eingängen;

Fig.4

eine Schaltungsanordnung zum Betrieb einer Leuchtstofflampe mit einer Detektorschaltung, bei der eine Fensterbreite anhand eines externen Signals einstellbar ist;

Show it:

Fig.1

a circuit arrangement for operating a fluorescent lamp;

Fig.2

a circuit arrangement for operating two fluorescent lamps;

Figure 3

a detector circuit with three inputs;

Figure 4

a circuit arrangement for operating a fluorescent lamp with a detector circuit, wherein a window width is adjustable by means of an external signal;

Fig.1 shows a circuit arrangement for operating a fluorescent lamp Lp10 comprising terminals 101, 102, 103 and 104. A half-bridge inverter comprises an npn transistor Q10 and an npn transistor Q11, wherein the emitter of the transistor Q10 is connected to the collector of the transistor Q11. This center tap of the half-bridge inverter is designated by a node 105. The node 105 is further connected to a coil L10 whose remaining terminal is connected to the terminal 101 of the fluorescent lamp LP10. The collector of the transistor Q10 is connected to a supply voltage Vbus, the emitter of the Transistor Q11 is connected to ground. A capacitor C10 is connected in parallel with the fluorescent lamp Lp10 to its terminals 102 and 104, and the terminal 103 of the fluorescent lamp LP10 is connected to ground via a capacitor C11.

Furthermore, the circuit arrangement of Fig.1 a detector circuit Det1 having inputs in1 and in2, an output out, two comparators Comp10 and Comp11 (each having a positive input, a negative input and an output) and resistors R13, R14, R16 and R17. The terminal 103 of the fluorescent lamp Lp10 is connected to the input in1 via a resistor R10, the input in2 is connected to the supply voltage Vbus via a resistor R11.

The detector circuit Det1 is constructed as follows: The positive input of the comparator Comp10 is connected to the input in1. The input in1 is connected to ground via a voltage divider comprising the resistors R13 and R16, the tap between the resistors R13 and R16 being connected to the negative input of the comparator Comp11. The input in2 is connected to the positive input of the comparator Comp11 and to ground via a voltage divider comprising the resistors R14 and R17. The tap between the resistors R14 and R17 is connected to the negative input of the comparator Comp10. The outputs of the comparators Comp10 and Comp11 are connected to each other and to the output out of the detector circuit Det1.

Also, a drive device A1 is provided, which is driven via the output out of the detector circuit Det1 and in turn is connected to the respective base of the transistors Q10 and Q11 and activates or deactivates them accordingly.

The transistors Q10 and Q11 are alternately switched by the driving device A1, so that the node 105 of the half-bridge inverter is alternately connected to the supply voltage Vbus and to the ground potential. The capacitor C11 (also referred to as coupling capacitor) is ideally charged to half the supply voltage Vbus, between the node 105 and the terminal 103 of the fluorescent lamp Lp10 flows an alternating current whose frequency is determined essentially by a switching clock of the transistors Q10 and Q11. During an electrode preheating phase, the alternating current flows through the two electrodes of the fluorescent lamp Lp10 and the capacitor C10 (also referred to as resonance capacitor). In an ignition phase, the ignition voltage for the fluorescent lamp Lp10 is provided to the capacitor C10, for example, by a resonance increase. After ignition of the discharge of the lamp Lp10, the alternating current flows substantially over the discharge path of the lamp, the capacitor C10 is almost bypassed in this case.

The detector circuit Det1 comprises a symmetrically constructed window comparator with the voltage dividers R13 / R16 and R14 / R17 and the comparators Comp10 and Comp11. The (voltage) comparators Comp10 and Comp11 respectively measure the voltage between one of the inputs in1 and in2 and the center tap of the voltage divider connected to the other input in2 and in1, respectively. The detector circuit is activated when the two input voltages at the inputs in1 and in2, regardless of their sign, differ by more than a set sensitivity (half window width).

Upon activation of the detector circuit Det1, the drive device A1 is preferably switched off. The detector circuit enables detection of the shift of the voltage drop across the capacitor C11 in FIG the positive or negative direction. If this shift is greater than a preset threshold, an error case of the fluorescent lamp Lp10 is detected, the detector circuit Det1 sends a signal to the drive device A1 via the output out, which stops or activates the activation of the fluorescent lamp Lp10 via the transistors Q10 and Q11 Driving the transistors Q10 and Q11 nurmehr a reduced current of the fluorescent lamp Lp10 supplies. Thus, upon reaching the end of life of a fluorescent lamp they are turned off or dangerous overheating of the fluorescent lamp can be effectively prevented.

Preferably, the outputs of the comparators Comp10 and Comp11 are of the "open collector" type and therefore can be connected together to provide a corresponding OR of the respective output signals at the output out.

The window width is set via a divider ratio of the two voltage dividers, eg $$\mathrm{R}\mathrm{13}\mathrm{/}\mathrm{R}\mathrm{16}\mathrm{=}\mathrm{R}\mathrm{14}\mathrm{/}\mathrm{R}\mathrm{17}\mathrm{=}\mathrm{500}\mathrm{\Omega }\mathrm{/}\mathrm{10}\mathrm{k\Omega }\mathrm{=}\mathrm{\pm }\mathrm{5}\mathrm{\%}\mathrm{,}$$

Due to the symmetrical design of the detector circuit Det1 this is particularly suitable for implementation as an integrated circuit, because then compensate for any tolerances of the voltage divider resistors largely.

For an integrated solution, the largest required sensitivity (smallest window width) is set. If necessary, this sensitivity can be reduced by a resistor arranged externally between the two inputs in1 and in2.

In the example of Fig.1 An electronic ballast for a fluorescent lamp Lp10 is shown. The voltage across the capacitor C11 is compared with the supply voltage Vbus. A factor of 2 between the two voltages can be set by appropriate dimensioning of the series resistors: $$\mathrm{R}\mathrm{10}\mathrm{=}\mathrm{1}\mathrm{milliohms}\mathrm{.}\mathrm{R}\mathrm{11}\mathrm{=}\mathrm{2}\mathrm{milliohms}\mathrm{,}$$

The influence of a deviating from the normal value DC link voltage is largely compensated in this arrangement.

Due to the symmetrical design with its two equal inputs, the detector circuit can be used flexibly. Fig.2 shows a circuit arrangement with two fluorescent lamps Lp20 and Lp21. The structure of the circuit arrangement largely corresponds to Fig.1 ,

$$\mathrm{R}\mathrm{23}\mathrm{,}\mathrm{R}\mathrm{24}\mathrm{=}\mathrm{500}\mathrm{\Omega }$$

$$\mathrm{R}\mathrm{26}\mathrm{,}\mathrm{R}\mathrm{27}\mathrm{=}\mathrm{10}\mathrm{k\Omega }$$

In Fig.2 the voltages of both coupling capacitors C21, C23 are compared directly with each other. An advantageous dimensioning of the resistors is: $$\mathrm{R}\mathrm{20}\mathrm{.}\mathrm{R}\mathrm{21}\mathrm{=}\mathrm{1}\mathrm{milliohms}$$

$$\mathrm{R}\mathrm{23}\mathrm{.}\mathrm{R}\mathrm{24}\mathrm{=}\mathrm{500}\mathrm{\Omega }$$

$$\mathrm{R}\mathrm{26}\mathrm{.}\mathrm{R}\mathrm{27}\mathrm{=}\mathrm{10}\mathrm{k\Omega }$$

Again, the influence of a deviating from the normal value DC link voltage is compensated.

By adding in each case a voltage divider and a voltage comparator, the detector circuit can be extended by one input in each case. Figure 3 shows an example of a detector circuit with three inputs in1, in2, in3 and an output out, comprising three comparators Comp30, Comp31, Comp32 and three voltage dividers R33 / R36, R34 / R37, R35 / R38.

The input in1 is connected to the positive terminal of comparator Comp30 and to ground via voltage divider R33 / R36. The input in2 is connected to the positive terminal of the comparator Comp31 and to the ground via the voltage divider R34 / R37. The input in3 is connected to the positive terminal of comparator Comp32 and to ground via voltage divider R35 / R38. The center tap of the voltage divider R33 / R36 is connected to the negative terminal of the comparator Comp31. The center tap of the voltage divider R34 / R37 is connected to the negative terminal of the comparator Comp32. The center tap of the voltage divider R35 / R38 is connected to the negative terminal of the comparator Comp30.

Figure 4 shows a circuit variant for a detector circuit Det4, in which the window width can be controlled by an external signal.

The wiring of the detector circuit Det4 largely corresponds Fig.1 , only the emitter of the transistor Q41 is now connected via a resistor R4 to ground and to an input B of the detector circuit Det4.

The detector circuit Det4 further comprises two inputs in1, in2, one output out, two comparators Comp40, Comp41 and four voltage dividers R42 / R46, R43 / R47, R44 / R48, R45 / R49.

The voltage divider R42 / R46 connects the input in1 to the terminal B, the voltage divider R43 / R47 connects the input in1 to ground, the voltage divider R44 / R48 connects the input in2 to the terminal B and the voltage divider R45 / R49 connects the input in2 Dimensions.

The center tap of the voltage divider R42 / R46 is connected to the negative input of the comparator Comp41. The center tap of the voltage divider R43 / R47 is connected to the positive input of the comparator Comp40. The center tap of the voltage divider R44 / R48 is connected to the negative input of the comparator Comp40. The center tap of the voltage divider R45 / R49 is connected to the positive input of the comparator Comp41.

$$\mathrm{R}43\mathrm{/}\mathrm{R}47\mathrm{=}\mathrm{R}45\mathrm{/}\mathrm{R}49\mathrm{=}10\mathrm{k\Omega }\mathrm{/}\mathrm{10}\mathrm{k\Omega }\mathrm{.}$$

In Figure 4 a separate voltage divider is used for each of the four comparator inputs. One possible dimensioning is as follows: $$\mathrm{R}42\mathrm{/}\mathrm{R}\mathrm{46}\mathrm{=}\mathrm{R}44\mathrm{/}\mathrm{R}48\mathrm{=}12\mathrm{k\Omega }\mathrm{/}\mathrm{10}\mathrm{k\Omega }.$$

$$\mathrm{R}43\mathrm{/}\mathrm{R}47\mathrm{=}\mathrm{R}45\mathrm{/}\mathrm{R}49\mathrm{=}10\mathrm{k\Omega }\mathrm{/}\mathrm{10}\mathrm{k\Omega }\mathrm{,}$$

Without a control signal at the input B of the detector circuit Det4 the window width is present ± 10%, with 100mV control voltage ± 5%.

A control signal depending on the lamp power (voltage across resistor R4) or lamp current, as shown here, will make the detector circuit more sensitive if needed.

Claims (10)

1. Circuit arrangement for controlling at least one fluorescent lamp (Lp10, Lp20; LP21), the circuit arrangement comprising the following features:

   - a half-bridge inverter (Q10, Q11; Q20, Q21) with at least one downstream load circuit,

   - at least one coupling capacitor (C11; C21, C23) which is connected to the load circuit and to the half-bridge inverter,

   - a control apparatus (A1; A2) for the half-bridge inverter,

   - the load circuit having connections for the at least one fluorescent lamp,

   - a detector circuit (Det1, Det2) which compares a first voltage with a reference voltage and uses at least two comparators (Comp10, Comp11; Comp20, Comp21) to generate an output signal for controlling the half-bridge inverter,

   - the first voltage corresponding to a voltage drop across the at least one coupling capacitor or to a voltage drop, modified by a voltage divider, across the at least one coupling capacitor,

   - the detector circuit being of essentially symmetrical construction,

   - the detector circuit comprising at least two voltage inputs and one voltage output,

   ○ a first voltage input (in1) being connected to a reference voltage source,

   ○ a second voltage input (in2) being connected to a connection of the at least one coupling capacitor directly or via at least one resistor, and

   ○ the voltage output (out) of the detector circuit being connected to the control apparatus for the half-bridge inverter,

   characterized in that
   the detector circuit comprises the following features:

   - the first input (in1) is connected to a first voltage divider (R13, R16) and to a positive input of a first comparator (Comp10);

   - a tap of the first voltage divider is connected to a negative input of a second comparator (Comp11);

   - the second input (in2) is connected to a second voltage divider (R14, R17) and to a positive input of the second comparator (Comp11);

   - a tap of the second voltage divider is connected to a negative input of the first comparator (Comp10);

   - an output of the first comparator is connected to an output of the second comparator and to the voltage output of the detector circuit.
2. Circuit arrangement according to Claim 1, differences between an intermediate circuit voltage and a predefined value being able to be compensated for.
3. Circuit arrangement according to one of the preceding claims, in which the reference voltage corresponds to a voltage drop across a further coupling capacitor or to a voltage drop, modified by a voltage divider, across the further coupling capacitor.
4. Circuit arrangement according to Claim 3 for controlling two fluorescent lamps.
5. Circuit arrangement according to one of the preceding claims, in which a window width of the detector circuit can be set using an external signal.
6. Circuit arrangement according to one of the preceding claims, in which the control apparatus comprises a disconnection apparatus which disconnects the half-bridge inverter when an abnormal operating state occurs.
7. Circuit arrangement according to Claim 6, in which the abnormal operating state is a fault in the fluorescent lamp.
8. Circuit arrangement according to one of the preceding claims, in which the reference voltage is formed via a voltage divider which is connected in parallel with a DC voltage input of the half-bridge inverter, the voltage divider having a tap at which the reference voltage is available.
9. Circuit arrangement according to one of the preceding claims for use in an electronic ballast.
10. Circuit arrangement according to one of the preceding claims for detecting the end of the service life and for disconnecting the fluorescent lamp.

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