EP2101438A3 - Communication system, receiver and reception method - Google Patents

Communication system, receiver and reception method Download PDF

Info

Publication number
EP2101438A3
EP2101438A3 EP09250612A EP09250612A EP2101438A3 EP 2101438 A3 EP2101438 A3 EP 2101438A3 EP 09250612 A EP09250612 A EP 09250612A EP 09250612 A EP09250612 A EP 09250612A EP 2101438 A3 EP2101438 A3 EP 2101438A3
Authority
EP
European Patent Office
Prior art keywords
amplifier
receiver
clock
serial data
synchronizing clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09250612A
Other languages
German (de)
French (fr)
Other versions
EP2101438A2 (en
Inventor
Takaaki Yamada
Hiroki Kihara
Tatsuya Sugioka
Hisashi Owa
Taichi Niki
Yukio Shimomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of EP2101438A2 publication Critical patent/EP2101438A2/en
Publication of EP2101438A3 publication Critical patent/EP2101438A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

A communication system (100) includes: a transmitter (200) adapted to transmit a synchronizing clock (SYNC CLK) and serial data (SDT) synchronous with the synchronizing clock over a line at low amplitude; and a receiver (300) adapted to receive the serial data and synchronizing clock from the transmitter. The receiver includes an amplifier (310) adapted to amplify the received synchronizing clock of low amplitude to restore the clock to its original amplitude, a latched comparator (330) adapted to latch the received serial data in synchronism with a reproduction clock, and a phase-locked circuit (320) including a frequency multiplier and a replica amplifier (325) similar to said amplifier (310) for compensating the delay caused by said amplifier (310).
EP09250612A 2008-03-12 2009-03-04 Communication system, receiver and reception method Withdrawn EP2101438A3 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008063004A JP4438877B2 (en) 2008-03-12 2008-03-12 COMMUNICATION SYSTEM, RECEPTION DEVICE, AND RECEPTION METHOD

Publications (2)

Publication Number Publication Date
EP2101438A2 EP2101438A2 (en) 2009-09-16
EP2101438A3 true EP2101438A3 (en) 2009-10-07

Family

ID=40756380

Family Applications (1)

Application Number Title Priority Date Filing Date
EP09250612A Withdrawn EP2101438A3 (en) 2008-03-12 2009-03-04 Communication system, receiver and reception method

Country Status (4)

Country Link
US (1) US8467490B2 (en)
EP (1) EP2101438A3 (en)
JP (1) JP4438877B2 (en)
CN (1) CN101534187A (en)

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US7716510B2 (en) 2006-12-19 2010-05-11 Micron Technology, Inc. Timing synchronization circuit with loop counter
US7656745B2 (en) 2007-03-15 2010-02-02 Micron Technology, Inc. Circuit, system and method for controlling read latency
US7969813B2 (en) 2009-04-01 2011-06-28 Micron Technology, Inc. Write command and write data timing circuit and methods for timing the same
JP5711949B2 (en) * 2010-12-03 2015-05-07 ローム株式会社 Serial data reception circuit, reception method, serial data transmission system using the same, and transmission method
US8984320B2 (en) 2011-03-29 2015-03-17 Micron Technology, Inc. Command paths, apparatuses and methods for providing a command to a data block
US8509011B2 (en) 2011-04-25 2013-08-13 Micron Technology, Inc. Command paths, apparatuses, memories, and methods for providing internal commands to a data path
US8687752B2 (en) * 2011-11-01 2014-04-01 Qualcomm Incorporated Method and apparatus for receiver adaptive phase clocked low power serial link
US8755480B1 (en) 2011-12-30 2014-06-17 Altera Corporation Integrated circuit (IC) clocking techniques
US8552776B2 (en) 2012-02-01 2013-10-08 Micron Technology, Inc. Apparatuses and methods for altering a forward path delay of a signal path
US9166579B2 (en) * 2012-06-01 2015-10-20 Micron Technology, Inc. Methods and apparatuses for shifting data signals to match command signal delay
US9054675B2 (en) 2012-06-22 2015-06-09 Micron Technology, Inc. Apparatuses and methods for adjusting a minimum forward path delay of a signal path
US9001594B2 (en) 2012-07-06 2015-04-07 Micron Technology, Inc. Apparatuses and methods for adjusting a path delay of a command path
US9329623B2 (en) 2012-08-22 2016-05-03 Micron Technology, Inc. Apparatuses, integrated circuits, and methods for synchronizing data signals with a command signal
US8913448B2 (en) 2012-10-25 2014-12-16 Micron Technology, Inc. Apparatuses and methods for capturing data in a memory
US9734097B2 (en) 2013-03-15 2017-08-15 Micron Technology, Inc. Apparatuses and methods for variable latency memory operations
US9727493B2 (en) 2013-08-14 2017-08-08 Micron Technology, Inc. Apparatuses and methods for providing data to a configurable storage area
US9183904B2 (en) 2014-02-07 2015-11-10 Micron Technology, Inc. Apparatuses, memories, and methods for facilitating splitting of internal commands using a shared signal path
US9508417B2 (en) 2014-02-20 2016-11-29 Micron Technology, Inc. Methods and apparatuses for controlling timing paths and latency based on a loop delay
US9530473B2 (en) 2014-05-22 2016-12-27 Micron Technology, Inc. Apparatuses and methods for timing provision of a command to input circuitry
US9531363B2 (en) 2015-04-28 2016-12-27 Micron Technology, Inc. Methods and apparatuses including command latency control circuit
US9813067B2 (en) 2015-06-10 2017-11-07 Micron Technology, Inc. Clock signal and supply voltage variation tracking
US9601170B1 (en) 2016-04-26 2017-03-21 Micron Technology, Inc. Apparatuses and methods for adjusting a delay of a command signal path
US9865317B2 (en) 2016-04-26 2018-01-09 Micron Technology, Inc. Methods and apparatuses including command delay adjustment circuit
US9997220B2 (en) 2016-08-22 2018-06-12 Micron Technology, Inc. Apparatuses and methods for adjusting delay of command signal path
US10224938B2 (en) 2017-07-26 2019-03-05 Micron Technology, Inc. Apparatuses and methods for indirectly detecting phase variations
CN113810893B (en) * 2021-11-17 2022-03-18 北京紫光青藤微系统有限公司 Device and method for clock signal recovery and NFC chip

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030098721A1 (en) * 2001-11-26 2003-05-29 Mitsubishi Denki Kabushiki Kaisha Phase comparator accurately comparing phases of two clock signals and clock generation circuit employing the same
US20030190006A1 (en) * 2002-04-09 2003-10-09 Hideo Nagano Data recovery circuit
WO2008026164A2 (en) * 2006-08-29 2008-03-06 Koninklijke Philips Electronics N.V. Method and apparatus for synchronization of a high speed lvds communication

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SE515490C2 (en) 1993-12-03 2001-08-13 Ericsson Telefon Ab L M signaling systems
JP2710214B2 (en) * 1994-08-12 1998-02-10 日本電気株式会社 Phase locked loop circuit
JP2773703B2 (en) * 1995-10-05 1998-07-09 日本電気株式会社 PLL circuit
US5859669A (en) * 1996-11-26 1999-01-12 Texas Instruments Incorporated System for encoding an image control signal onto a pixel clock signal
JP2000132266A (en) * 1998-10-23 2000-05-12 Mitsubishi Electric Corp Internal clock signal generation circuit, phase comparator, and method for testing internal clock signal generation circuit
US6801080B1 (en) * 2003-04-07 2004-10-05 Pericom Semiconductor Corp. CMOS differential input buffer with source-follower input clamps
KR100559378B1 (en) * 2004-07-02 2006-03-10 삼성전자주식회사 Lvds receiver controlling current by frequency and method for the same
US7221201B2 (en) * 2004-08-11 2007-05-22 Micron Technology, Inc. Fast-locking digital phase locked loop

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030098721A1 (en) * 2001-11-26 2003-05-29 Mitsubishi Denki Kabushiki Kaisha Phase comparator accurately comparing phases of two clock signals and clock generation circuit employing the same
US20030190006A1 (en) * 2002-04-09 2003-10-09 Hideo Nagano Data recovery circuit
WO2008026164A2 (en) * 2006-08-29 2008-03-06 Koninklijke Philips Electronics N.V. Method and apparatus for synchronization of a high speed lvds communication

Also Published As

Publication number Publication date
JP2009219035A (en) 2009-09-24
CN101534187A (en) 2009-09-16
JP4438877B2 (en) 2010-03-24
US8467490B2 (en) 2013-06-18
US20090232250A1 (en) 2009-09-17
EP2101438A2 (en) 2009-09-16

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