EP2071470B1 - Procédé et dispositif pour la génération de priorité dans un appareil multiprocesseur - Google Patents

Procédé et dispositif pour la génération de priorité dans un appareil multiprocesseur Download PDF

Info

Publication number
EP2071470B1
EP2071470B1 EP07122846A EP07122846A EP2071470B1 EP 2071470 B1 EP2071470 B1 EP 2071470B1 EP 07122846 A EP07122846 A EP 07122846A EP 07122846 A EP07122846 A EP 07122846A EP 2071470 B1 EP2071470 B1 EP 2071470B1
Authority
EP
European Patent Office
Prior art keywords
counter
value
arbiter
access
priority
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP07122846A
Other languages
German (de)
English (en)
Other versions
EP2071470A1 (fr
Inventor
Rowan Naylor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Priority to DE602007010015T priority Critical patent/DE602007010015D1/de
Priority to AT07122846T priority patent/ATE485560T1/de
Priority to EP07122846A priority patent/EP2071470B1/fr
Priority to US12/746,521 priority patent/US8423694B2/en
Priority to PCT/EP2008/067022 priority patent/WO2009074536A1/fr
Publication of EP2071470A1 publication Critical patent/EP2071470A1/fr
Application granted granted Critical
Publication of EP2071470B1 publication Critical patent/EP2071470B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Definitions

  • the present invention relates to access to a shared resource in a multiprocessor apparatus, in general, and in particular to arbitration mechanism for controlling access to the shared resource.
  • Modem single chip digital systems employ multiple processors but for cost reasons a single external memory or other shared resource.
  • an arbitration system In order to obtain maximum efficiency of use of the available resource and ensure each processor gets an adequate share of the resource it is necessary to implement an arbitration system.
  • the function of the arbitration system also referred to as an arbiter, is to decide which of the devices requesting access to the resource will have the access granted.
  • granting the access is based on a first in - first served basis. This may result in granting access to relatively unimportant processes at the expense of important ones.
  • the access is granted based on a round-robin basis.
  • Each of the devices has assigned a time-slot in which it can access the resource and after expiration of the assigned time-slot ownership of the resource is handed over to another device and it has to wait for another time-slot in order to access the resource.
  • the drawback ofthis solution is that during some time-slots the resource is not used if the device associated with this time-slot does not need the resource.
  • the decision of the arbiter is based on a parameter assigned to each of the devices known as priority.
  • a device requesting access having the highest priority is granted the access.
  • the disadvantage of this solution is that a fixed priority does not take into account behaviour of the users of the resource and changes of priorities have to be initiated and executed by the user.
  • the invention seeks to preferably mitigate, alleviate or eliminate one or more of the disadvantages mentioned above singly or in any combination.
  • a method of controlling access to a shared resource in a multiprocessor apparatus In this system the processors request access to the resource and an arbiter grants or deny the access based on priority values assigned to the processors.
  • a priority value for an individual processor is generated by a priority generator by maintaining a counter, receiving signals from the arbiter indicating access granted or access denied decision. The arbiter transmits these signals at least to those processors which requested access to said resource. Once the signal is received, changing the value of the counter upon receipt of said signals, wherein the changes of the counter go in opposite directions depending on the type of signal received from the arbiter. The modified value of the counter is then sent as a new priority value to the arbiter.
  • a device for generating a priority value of a processor in a multiprocessor apparatus comprises a counter and an interface for receiving signals from an arbiter.
  • the signals indicate decision of the arbiter about granting or denying access to a common resource in said multiprocessor apparatus.
  • the counter is adapted to change its value in response to said signal and the changes of the counter go in opposite directions depending on the type of signal received from the arbiter.
  • the device is also adapted to send the modified value of the counter as a new priority value to the arbiter.
  • a multiprocessor apparatus comprising a resource shared by at least part of said processors, and plurality of priority generators in accordance with the second aspect of the present invention.
  • the priority generators are assigned to said processors.
  • the apparatus further comprises an arbiter for controlling access to said shared resource. Said arbiter is adapted to send a signal indicating granted access to one of said priority generators that has been granted access and a signal indicating access denied to priority generators, which have not been granted access.
  • the present invention provides the benefit of finer and automatic control of access to the shared resource allowing higher efficiency allowing greater performance and so more work to be done by the system. Additionally it provides better control of the latency of access to the resource allowing the system to avoid automatically situations where the delay in access to the resource causes the associated process to fail. Finally, there is also the benefit of automatic operation and adaptation to traffic freeing the processor/s from this task and as a result freeing the processors to do more work.
  • the present invention in its various embodiments is applicable to access control to a shared resource in a multiprocessor apparatus in which an arbiter grants access based on priority value associated with the processors requesting the access.
  • processor refers to any component in the apparatus that is capable of requesting access to the shared resource. It includes, but is not limited to, microprocessors also referred to as CPUs (Central Processing Units), digital signal processors (DSPs), hardware accelerators as well as microprocessors having more than one bus and in effect being more than one requesting source.
  • CPUs Central Processing Units
  • DSPs digital signal processors
  • hardware accelerators as well as microprocessors having more than one bus and in effect being more than one requesting source.
  • the arbiter 508 In operation, as illustrated in FIG. 1 and FIG. 5 once the arbiter 508 receives a request, 102, for access to the resource, 502, it is checked by the arbiter 508 if there is other processor 504 competing for the same resource with higher priority, 104. The processor with the highest priority is granted the access, 106, and all the other processors competing are denied access, 110. The arbiter then sends two types of signals to priority generators associated with the processors 112. The priority generator 506 of the processor 504 that won the access to the shared resource 502 receives Rak signal indicating access granted decision and the remaining priority generators 506 receive Orq signal indicating access denied decision. In a preferred embodiment the Orq signal is sent to those processors which requested and have been denied access to the shared resource.
  • Orq signal is sent to all processors connected to the arbiter with the exception of the processor, which has been granted access (as it receives the Rak signal).
  • the Orq signal is sent to all processors connected to the arbiter with the exception of the processor, which has been granted access (as it receives the Rak signal).
  • the priority generator maintains a counter 200, which value is the priority value of the associated processor and it may be changed during operation depending on the behaviour of the multiprocessor apparatus.
  • the priority generator receives 202 a signal from the arbiter it checks if it is a signal indicting access granted decision or denied decision, 204.
  • the priority generator changes value of the counter in a direction that depends on the type of the signal it received, 206, 208 and mode of operation it has been setup to obey.
  • the counter value is increased (this is also referred herein as ascending mode) and access denied signal causes the counter to decrease the value of the counter.
  • the counter value is decreased (this is also referred herein as descending mode) and access denied signal causes the counter to increase the value of the counter.
  • the priority generator use the new value to send, 210, to the arbiter in order to be used in the next decision on granting access to the shared resource.
  • a preferred embodiment of the present invention is illustrated.
  • a signal from the arbiter is received at an interface 404 it is converted (decoded) to a pulse.
  • the two signals are converted at the interface in a way that one pulse is generated when any bus is granted access other than the one associated with this PG (A_Ack) 314, the second when this PG is granted access (R_Ack), 316.
  • A_Ack the first pulse is generated when any bus is granted access other than the one associated with this PG
  • R_Ack the second when this PG is granted access
  • the counter value changes as previously discussed and then is sent to the arbiter as a priority value, 321.
  • the value of the counter is limited from the top and bottom.
  • the counter reaches the limit 320, 330 it automatically takes the value of the opposite limit as the new counter value 328, 336.
  • This type of operation is further referred herein as non-saturated. That means if the counter reaches its upper limit, 330, it automatically changes its value to the value of the lower limit 336. Alternatively, if the counter reaches its lower limit, 320, it automatically changes its value to the value of the upper limit 328.
  • the counter value is changed its value is sent as a priority to the arbiter 339.
  • the priority generator may work in a saturated mode, 324, 334.
  • the counter reacts only to signals that cause decrease of the counter, 338. That is, in the ascending mode after reaching value of the upper limit 330 the counter does not increase, 338, upon receipt of Rak signal, however, receipt of Orq signal causes the counter to decrease by 1, 338, and in the next cycle the counter can change in the up direction (as it is not equal to the upper limt).
  • the counter value is sent to the arbiter as a priority value of the associated processor, 339.
  • Similar operations are performed when the priority generator 400 is in saturated mode 324 and the counter reaches its lower limit 320. The difference is that the counter value cannot decrease below the lower limit, 326, and the counter reacts only to signals that cause increase of the counter, 326.
  • saturation the counter stops at the limit and can only count in the opposite direction, 326, 338. For example on reaching the maximum it will increment no further but stay at this value unless it receives a decrement in which case it will count down. On reaching the minimum it will decrement no further but stay at this value unless it receives an increment in which case it will count up.
  • the saturation is enabled and the priority generator's counter 402 increments when its bus is granted access and decremented when another bus is granted access.
  • the priority tends to the minimum limit but rises to a maximum the more frequently the bus requests. This can be used where the user makes occasional accesses in which case it gets a nominal (its minimum) priority where latency is acceptable but should it stream data where perhaps internal buffering is limited then it can get more bandwidth as its demand increases. As demand drops its priority drops allowing other users more bandwidth. By setting min and max limit other users can be guaranteed use.
  • the saturation is enabled and the priority generator's counter 402 decrements when its bus is granted access and incremented when another bus is granted access.
  • the priority tends to the maximum limit but drops to a minimum the more frequently the bus requests. This can be used where the user makes occasional accesses requiring low latency in which case it gets a nominal (its maximum) priority where latency is critical but should it start to increase it demands and possibly block other users then its priority drops allowing other users access. As its demand drops its priority returns to the higher level.
  • the counter loops and when the limit is breeched there is a steep change to the other limit.
  • the counter is used in one direction only, the other being disabled.
  • the decrement input is disabled.
  • the bus priority starts at its minimum and ascends as the bus demand increases, at reaching the maximum value the minimum is loaded and the process repeated. This is used in situations where there are multiple busses in groups of similar performance needs, this allows each to use the resource equally but tries to minimise the average latency based on the relative demands.
  • the users in this mode have a nominal low priority that rises allowing them to gain more bandwidth relative to another group, maybe fixed priority, as the demand increases but the loop prevents them blocking other groups.
  • the counter loops and when the limit is breeched there is a steep change to the other limit.
  • the counter is used in one direction only the other being disabled.
  • the increment input is disabled.
  • the bus priority starts at its maximum and descends as the bus demand increases, at reaching the minimum value the maximum is loaded and the process repeated. This is used in situations where there are multiple busses in groups of similar performance needs, this allows each to use the resource equally but tries to minimise the average latency based on the relative demands.
  • the users in this mode have a nominal high priority that descend allowing other groups to gain more bandwidth relative to this group as their demand increases preventing the group from blocking other users.
  • the loop also prevents this group itself from being blocked.
  • the priority generator waits for another signal from the arbiter in order to modify the value of the counter, 322, 340.
  • the priority generator 400 comprises a counter 402, an interface 404 for receiving signals from an arbiter.
  • the signals indicate decision of the arbiter about granting or denying access to a common resource in said multiprocessor apparatus and the counter 402 changes its value in response to said signal.
  • the changes of the counter go in opposite directions depending on the type of signal received from the arbiter.
  • the priority generator, 400 sends the modified value of the counter as a new priority value to the arbiter.
  • the priority generator, 400 comprises a first multiplexer, 406, connected to an increment port of the counter 402 and a second multiplexer, 408, connected to the decrement port of the counter 402.
  • Each of the multiplexers comprises two ports for receiving pulses from the interface 404. The pulses are generated by the interface in response to signals received from the arbiter.
  • Said multiplexers are controlled by a counter control unit, 410. In the descending mode a pulse corresponding to the signal indicating access granted is directed by the multiplexer to the decrement port and a pulse corresponding to access denied decision to the increment port of the counter 402.
  • the counter control unit 410 directs a pulse indicating access grant decision to the increment port and a pulse indicating access denied decision to the decrement port of the counter 402.
  • the priority generator, 400 comprises a register 412, 414 for storing predefined lower and upper limits of the counter (min. and max values).
  • the priority generator also comprises two comparators 416, 418.
  • the first comparator, 416 is used to compare current value of the counter 402 with the upper limit, 414.
  • the second comparator 418 is for comparing the current counter value with the lower limit, 412.
  • the registers 412 and 414 are connected to the counter 402 via a third multiplexer 422. Results of the comparison carried out by the comparators 416 and 418 are input to the counter control unit 410.
  • the counter control unit 410 instructs the counter to operate in a prescribed way when the counter reaches one of the limits (i.e. depending on whether the priority generator is in saturated or non-saturated mode).
  • the counter control unit 410 is connected to a user interface (not shown) in order to enable the user to program the priority generator.
  • the user has the possibility to select between the four combined modes of operation and also set the values of the limits or alternatively the user may change only the direction of the changes of the counter between ascending or descending modes or only between saturated and non-saturated modes.
  • each pulse train from the interface 404 passes through a divider 420 that is programmed to divide the number of pulses reaching the counter, this moderates the response of the counter with respect to the behaviour of the arbiter and hence rate of change of the priority.
  • the apparatus 500 is a communication device, e.g. a mobile phone.
  • the apparatus comprises a resource 502 shared by at least part of said processors 504 and further comprising a plurality of priority generators 506 as discussed.
  • Each of said priority generators, 506, is assigned to one of said processors 504.
  • An arbiter, 508, for controlling access to said resource 502 has the plurality of priority generators 506 connected to it. Said arbiter, 508, sends a signal indicating granted access to one of said priority generators, 506 that has been granted access and a signal indicating access denied to the remaining priority generators 506, which have been denied said access.
  • the apparatus 502 also comprises a bus multiplexer 510 for multiplexing buses connecting the processors 504.
  • the multiple buses are multiplexed onto a single bus to the common resource 502.
  • a request from any bus for access to the resource is routed to the arbiter 508.
  • the arbiter 508 uses the requests to select the priorities it needs to compare to make a decision. It employs one or a number of algorithms known in the art when the priorities are the same. When they are not it selects the bus with the highest priority and instructs the bus multiplexer 510 to allow access to the associated bus (processor).
  • the bus multiplexer, 510 multiplexes all bus signals from multiple buses to a single bus, it also uses the bus protocol to force busses with pending request to wait while an existing transaction to common resource is completed. All access requests to the common resource 502 are sent to the arbiter 508 and the multiplexer receives an enable signal for the bus to be allowed access to the common resource from the arbiter.
  • the arbiter 508 compares the priorities of the processors requesting access to the common resource and only those, selects the highest priority and grants access to the associated bus. However, when two or more busses have the same priority the arbiter, 508, employs one of the algorithms known in the art and selectable by the system.
  • the arbiter 508 can use the round-robin algorithm.
  • the arbiter interfaces to a priority generator with two signals, one common to all priority generators (Other Request), and the other specific to a priority generator that has been granted access (Request Accepted).
  • An individual priority generator 506 produces a priority value for its bus, this value is from a range of values greater than the number of busses being arbitrated. For example 8bit (256 level) priority value is used per bus even though there may be only 8 buses traditionally requiring only a 3 bit value. This is used to improve the granularity of the decision the arbiter makes based on the bus activity.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)

Claims (16)

  1. Procédé de commande d'accès à une ressource partagée dans un appareil multiprocesseur dans lequel les processeurs demandent accès à la ressource et un arbitre accorde ou refuse l'accès sur la base de valeurs de priorité assignées aux processeurs, dans lequel une valeur de priorité pour un processeur individuel est générée par un générateur de priorité au cours des étapes suivantes consistant à :
    - conserver (200) un compteur ;
    - recevoir (202) des signaux provenant de l'arbitre indiquant la décision d'accès accordé ou d'accès refusé (204), dans lequel l'arbitre transmet ces signaux au moins aux processeurs qui ont demandé accès à ladite ressource ;
    - modifier la valeur du compteur à la réception desdits signaux, dans lequel les modifications du compteur vont dans des directions opposées (206, 208, 310, 312) en fonction du type de signal reçu en provenance de l'arbitre ;
    - envoyer (210, 321) la valeur modifiée du compteur comme une nouvelle valeur de priorité à l'arbitre.
  2. Procédé selon la revendication 1, dans lequel le signal indiquant la décision d'accès accordé (306) décrémente la valeur de compteur (308, 312) et le signal indiquant la décision d'accès refusé (314) incrémente la valeur de compteur (316, 310).
  3. Procédé selon la revendication 1, dans lequel le signal indiquant la décision d'accès accordé (306) incrémente la valeur de compteur (308, 310) et le signal indiquant la décision d'accès refusé (314) décrémente la valeur de compteur (316, 312).
  4. Procédé selon une quelconque des revendications précédentes, comprenant en outre de limiter le compteur par des limites inférieure et supérieure prédéfinies, comparer la valeur du compteur avec lesdites limites inférieure (320) et supérieure (330) prédéfinies et si la valeur de compteur atteint une desdites limites, la valeur de compteur est modifiée à la limite opposée (328, 336).
  5. Procédé selon une quelconque des revendications 1 à 3, comprenant de limiter le compteur par des limites inférieure et supérieure prédéfinies et de modifier la valeur de compteur (326, 338) en réponse seulement à un des signaux d'arbitre si ladite valeur de compteur est égale à une desdites limites inférieure ou supérieure prédéfinies (320, 330).
  6. Dispositif (400) pour générer une valeur de priorité d'un processeur dans un appareil multiprocesseur, le dispositif comprenant un compteur (402), une interface (404) pour recevoir des signaux en provenance d'un arbitre, dans lequel les signaux indiquent une décision de l'arbitre concernant l'accord ou le refus d'accès à une ressource commune dans ledit appareil multiprocesseur et le compteur (402) étant adapté afin de modifier sa valeur en réponse audit signal et les modifications du compteur vont dans des directions opposées en fonction du type de signal reçu en provenance de l'arbitre ; le dispositif est aussi adapté afin d'envoyer la valeur modifiée du compteur comme une nouvelle valeur de priorité à l'arbitre.
  7. Dispositif (400) selon la revendication 6, comprenant en outre un premier multiplexeur (406) connecté à un port d'incrémentation du compteur (402) et un second multiplexeur (408) connecté à un port de décrémentation du compteur (402), dans lequel chacun desdits multiplexeurs (406, 408) comprend deux ports pour recevoir des impulsions provenant de ladite interface (404) en réponse auxdits signaux provenant de l'arbitre et lesdits multiplexeurs (406, 408) sont commandés par une unité de commande de compteur (410).
  8. Dispositif (400) selon la revendication 7, dans lequel l'unité de commande de compteur (410) est adaptée afin de diriger une impulsion correspondant au signal indiquant la décision d'accès accordé vers le port de décrémentation et une impulsion correspondant au signal indiquant la décision d'accès refusé vers le port d'incrémentation du compteur (402).
  9. Dispositif (400) selon la revendication 7, dans lequel l'unité de commande de compteur (410) est adaptée afin de diriger une impulsion correspondant au signal indiquant la décision d'accès accordé vers le port d'incrémentation et une impulsion correspondant au signal indiquant la décision d'accès refusé vers le port de décrémentation du compteur (402).
  10. Dispositif (400) selon une quelconque des revendications 6 à 9 comprenant un registre (412, 414) pour mémoriser des valeurs de limites inférieure et supérieure prédéfinies dudit compteur (402), un premier comparateur (416) pour comparer la valeur de compteur avec la limite supérieure et un second comparateur (418) pour comparer la valeur de compteur avec la limite inférieure, dans lequel les résultats de ladite comparaison sont entrés dans ladite unité de commande de compteur (410) étant en outre adaptée afin de commander le fonctionnement du compteur (402) sur la base des entrées provenant des comparateurs (416, 418).
  11. Dispositif (400) selon la revendication 10, dans lequel ladite unité de commande de compteur (410) est adaptée afin de modifier la valeur de compteur en une desdites limites si ladite valeur de compteur atteint la limite opposée.
  12. Dispositif (400) selon la revendication 10, dans lequel ledit compteur (402) est adapté afin de modifier sa valeur en réponse seulement à une des impulsions si ladite valeur de compteur est égale à une desdites limites inférieure et supérieure prédéfinies.
  13. Dispositif (400) selon une quelconque des revendications 7 à 12, dans lequel l'unité de commande de compteur (410) est connectée à une interface d'utilisateur, qui permet à l'utilisateur de modifier la direction de modification du compteur (402) en réponse aux impulsions.
  14. Dispositif (400) selon une quelconque des revendications 7 à 13, dans lequel l'unité de commande de compteur (410) est connectée à une interface d'utilisateur, qui permet à l'utilisateur de modifier le fonctionnement du compteur est réponse au fait que lesdites limites sont atteintes.
  15. Dispositif (400) selon une quelconque des revendications 6 à 14 comprenant un diviseur (420) situé entre l'interface (404) et les multiplexeurs (406, 408) afin de commander un taux de modification de la valeur de compteur.
  16. Appareil multiprocesseur (500) comprenant une ressource partagée par au moins une partie desdits processeurs (504), l'appareil (500) comprenant en outre une pluralité de générateurs de priorité (506) selon une quelconque des revendications 6 à 15 assignés auxdits processeurs (504) et un arbitre (508) pour commander l'accès à ladite ressource (502), dans lequel ledit arbitre (508) est adapté afin d'envoyer un signal indiquant un accès accordé à un desdits générateurs de priorité (506) qui s'est vu accorder l'accès et un signal indiquant un accès refusé aux générateurs de priorité (506), qui se sont vu refuser l'accès.
EP07122846A 2007-12-11 2007-12-11 Procédé et dispositif pour la génération de priorité dans un appareil multiprocesseur Active EP2071470B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE602007010015T DE602007010015D1 (de) 2007-12-11 2007-12-11 Verfahren und Vorrichtung für die Erzeugung von Prioritäten in einem Multiprozessor-Gerät
AT07122846T ATE485560T1 (de) 2007-12-11 2007-12-11 Verfahren und vorrichtung für die erzeugung von prioritäten in einem multiprozessor-gerät
EP07122846A EP2071470B1 (fr) 2007-12-11 2007-12-11 Procédé et dispositif pour la génération de priorité dans un appareil multiprocesseur
US12/746,521 US8423694B2 (en) 2007-12-11 2008-12-08 Method and device for priority generation in multiprocessor apparatus
PCT/EP2008/067022 WO2009074536A1 (fr) 2007-12-11 2008-12-08 Procédé et dispositif pour une génération de priorité dans un appareil à processeurs multiples

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP07122846A EP2071470B1 (fr) 2007-12-11 2007-12-11 Procédé et dispositif pour la génération de priorité dans un appareil multiprocesseur

Publications (2)

Publication Number Publication Date
EP2071470A1 EP2071470A1 (fr) 2009-06-17
EP2071470B1 true EP2071470B1 (fr) 2010-10-20

Family

ID=39092078

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07122846A Active EP2071470B1 (fr) 2007-12-11 2007-12-11 Procédé et dispositif pour la génération de priorité dans un appareil multiprocesseur

Country Status (5)

Country Link
US (1) US8423694B2 (fr)
EP (1) EP2071470B1 (fr)
AT (1) ATE485560T1 (fr)
DE (1) DE602007010015D1 (fr)
WO (1) WO2009074536A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9367498B2 (en) * 2011-09-14 2016-06-14 Panasonic Intellectual Property Management Co., Ltd. Resource request arbitration device, resource request arbitration system, resource request arbitration method, integrated circuit, and program
US9191435B2 (en) 2012-08-23 2015-11-17 TidalScale, Inc. Selective data migration or remapping of virtual processors to provide required data accessibility to processor cores
US10620992B2 (en) 2016-08-29 2020-04-14 TidalScale, Inc. Resource migration negotiation
US10579274B2 (en) 2017-06-27 2020-03-03 TidalScale, Inc. Hierarchical stalling strategies for handling stalling events in a virtualized environment
US10817347B2 (en) 2017-08-31 2020-10-27 TidalScale, Inc. Entanglement of pages and guest threads

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5025370A (en) * 1986-09-02 1991-06-18 Koegel Robert J Circuit for preventing lock-out of high priority requests to a system controller
US4953081A (en) 1988-12-21 1990-08-28 International Business Machines Corporation Least recently used arbiter with programmable high priority mode and performance monitor
US5560016A (en) * 1994-10-06 1996-09-24 Dell Usa, L.P. System and method for dynamic bus access prioritization and arbitration based on changing bus master request frequency
GB2372916A (en) 2001-02-28 2002-09-04 Motorola Inc Dynamic bus arbitration for shared bus architecture
US20040059879A1 (en) * 2002-09-23 2004-03-25 Rogers Paul L. Access priority protocol for computer system
US7685346B2 (en) * 2007-06-26 2010-03-23 Intel Corporation Demotion-based arbitration

Also Published As

Publication number Publication date
WO2009074536A1 (fr) 2009-06-18
US20110004714A1 (en) 2011-01-06
EP2071470A1 (fr) 2009-06-17
ATE485560T1 (de) 2010-11-15
US8423694B2 (en) 2013-04-16
DE602007010015D1 (de) 2010-12-02

Similar Documents

Publication Publication Date Title
EP2071470B1 (fr) Procédé et dispositif pour la génération de priorité dans un appareil multiprocesseur
US6976109B2 (en) Multi-level and multi-resolution bus arbitration
US8549199B2 (en) Data processing apparatus and a method for setting priority levels for transactions
US7350004B2 (en) Resource management device
CN111444012B (zh) 一种保证延迟敏感应用延迟slo的动态调控资源方法及系统
JP4238133B2 (ja) サービス品質の規制に適合するリソースをスケジューリングする方法及び装置
US5996037A (en) System and method for arbitrating multi-function access to a system bus
US20050060456A1 (en) Method and apparatus for multi-port memory controller
US20070179676A1 (en) Peak power-controlling apparatus and method
US7213084B2 (en) System and method for allocating memory allocation bandwidth by assigning fixed priority of access to DMA machines and programmable priority to processing unit
US7380040B2 (en) Software programmable dynamic arbitration scheme
EP2320326B1 (fr) Contrôleur de bus, système de communication de bus et procédé de commande de bus
JP2011254422A (ja) 通信制御装置およびシェイピング装置
US6028841A (en) Distributed bus throttle and method
US20030221033A1 (en) Bus arbiter for integrated circuit systems
EP1029284B1 (fr) Controleur d'acces en memoire partagee
US6571306B1 (en) Bus request mechanism for bus master which is parked on a shared bus
KR20180014689A (ko) 분할 버스트 대역폭 중재를 위한 방법 및 장치
CN110213178B (zh) 流量管理方法、集成芯片、及装置
KR100605867B1 (ko) 동적 우선순위 조정기능을 갖는 버스 중재기와 버스 중재방법
KR20080081681A (ko) 다중 레벨의 우선순위를 제공하는 ｐｃｉ 신호처리장치 및그 방법
JPH05250308A (ja) 電子計算機の調停方式
JP2006041686A (ja) パケット交換機
JP2003087866A (ja) 移動通信制御装置、ｃｐｕリソース割付方法およびｃｐｕリソース割付プログラム
JPH0782470B2 (ja) バス調停回路

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA HR MK RS

17P Request for examination filed

Effective date: 20091030

17Q First examination report despatched

Effective date: 20091126

AKX Designation fees paid

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REF Corresponds to:

Ref document number: 602007010015

Country of ref document: DE

Date of ref document: 20101202

Kind code of ref document: P

REG Reference to a national code

Ref country code: NL

Ref legal event code: VDEP

Effective date: 20101020

LTIE Lt: invalidation of european patent or patent extension

Effective date: 20101020

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110220

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110120

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110221

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110121

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20101231

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110131

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20110831

26N No opposition filed

Effective date: 20110721

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20110103

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20101211

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602007010015

Country of ref document: DE

Effective date: 20110721

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

Ref country code: MT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20111211

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20101211

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110421

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101020

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20111231

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20111231

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20111211

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20231229

Year of fee payment: 17