EP2041783A2 - Module having a flat structure, and equipment method - Google Patents
Module having a flat structure, and equipment methodInfo
- Publication number
- EP2041783A2 EP2041783A2 EP07785583A EP07785583A EP2041783A2 EP 2041783 A2 EP2041783 A2 EP 2041783A2 EP 07785583 A EP07785583 A EP 07785583A EP 07785583 A EP07785583 A EP 07785583A EP 2041783 A2 EP2041783 A2 EP 2041783A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- substrate
- bonding
- module
- bonded
- module according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
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Definitions
- Modules are used to integrate different components on a substrate. Usually, components are interconnected via the modules. An encapsulation of the entire module can replace individual component encapsulations.
- modules in the event of thermal cycling depends largely on the design and connection technology as well as the encapsulation of the module.
- the bond wires present particular weak points, as they may be present at e.g. Due to different thermal expansion tensile stresses tend to tear, the function of the entire module is destroyed or destroyed.
- One method of wire bonding is the so-called stand off stitch bonding (SSB) in which a so-called stud bump is first generated on a second bondpad.
- a stud bump is the end of a bond wire that has been deformed into a ball by fusion, which is bonded to the bond pad and at which the wire over the ball is torn off immediately after bonding.
- a conventional ball stitch is performed, whereby the bonding wire is bonded to a first bonding pad by means of its ball-shaped end and the other end of the bonding wire, designated as a wedge or stitch, is placed directly on the stud bump on the second bonding pad.
- the so-called “reverse ball stitch” method becomes a stud-bump on the Component chip and the ball applied to the substrate.
- the Stud Bump is used in the "Reverse Ball Stitch” bonding to the wedge at a distance from the second Bondpad réellebonden to protect damage to the chip surface through the wire-carrying capillary of the bonding machine, especially when the bonding wire is squeezed at the end.
- thermal stability of modules with wire-bonded component chips depends essentially on the length of the bonding wires and in particular on the height of the loops which form the bonding wires fastened at both ends, in particular if the bonding wires are still covered with a glob top or module become.
- Object of the present invention is to provide a module with wire-bonded component chips, which is resistant to thermal cycling.
- a module which has a component chip bonded on and contacted to the module substrate by bonding wires.
- the "reverse ball stitch" method already described is used, but the wire end of the bonding wire already bonded to the module substrate is bonded directly onto the bond pad of the component chip without a stud bump in between , the To lead bonding wire flat over the surface of the component chip without a large component chip protruding wire loop needs to be taken into account.
- the bonding wire is conventionally bonded with a ball to the connection surfaces present there.
- the bonding wire may have a round or even a rectangular cross-sectional area. In extreme cases, it is designed as a metal strip. This design is particularly flat feasible and has advantages, if over the bonding wire or the metal ribbon HF signals are to be performed. Because of the skin effect, RF signals have only a small "depth of immersion" in the metal strip A rectangular bonding wire allows a smaller overall height compared to a round bonding wire with the same cross-sectional area
- Bonding wire used metal ribbon can be bonded at both ends as a wedge (Stictch) and needed as a first bond no ball.
- Such a module can be covered with a glob top mass or an injection molding applied mold mass, which can be applied due to the lower loop height of the bonding wires in lower overall height than heretofore.
- This increases the stability of the proposed module in that over the more unstable of the two bond connections of a bonding wire, namely over the wedge bond connection over the upward-facing surface of the component chip now only a small glob top thickness is applied.
- the tensile and shear forces acting in the module due to different thermal expansion coefficients are a function of the glob top thickness applied over the corresponding vulnerable site, here the bondwire bond.
- both the less resilient bond better protected and the overall lower Glob top height also increases the stability of the more stable bonding wire connection directly on the substrate.
- a lower Glob Top cover also results in a lower module height.
- a stud bump may be applied over the wedge bond. This sits on the bonding wire end and on the bond pad and provides an additional attachment of the bonding wire end, which makes this bond more stable against tearing off the bonding wire or releasing the bond.
- the bonding device When wedging or stitch bonding, the bonding device, ie the wire-guiding capillary, must act on the bondpad with relatively high pressure.
- the bonding pad according to the invention can be particularly designed. While previously the bondpond and then the passivation is generated, which leads to a partial overlap of the passivation on the bondpad, now the bondpad is designed so that it overlaps the passivation on all sides and they can not be damaged by the wire-guiding capillary.
- a further reduction of the overall module height and in particular the required glob top height is achieved if the height of the components sitting on the substrate and in particular of the component chips is minimized.
- the stability is additionally improved due to the lower glob top thickness.
- the lower component chip height only has an advantageous effect on the module height if no SMD components are applied to the substrate. But even if additional SMD components are applied, a gain in stability is achieved with the advantageous proposed wire bond, which is independent of the applied Glob top thickness.
- Resistors can be integrated in the module. Since these often can not be generated within the multilayer substrate, for example, SMD resistors can be used for this purpose. However, it is possible, and for a small module height, to replace SMD resistors with printed resistors deposited directly on the substrate surface. For example, a resistance paste before the sintering of the substrate as an inner layer pressure or after sintering printed as outer layer pressure and both against corrosion and against the galvanic reinforcement or the Damage / decomposition in the electroplating be covered with a passivation layer, in particular with a glass layer. Such an open resistance layer has the further advantage that it can be subsequently trimmed, for example by means of a laser.
- An advantageous substrate material is a multilayer ceramic, in particular a LTCC (Low Temperature Cofired Ceramic), which comprises a plurality of dielectric ceramic layers, between which structured metallization levels are provided. Different metallization levels are connected via vias. By way of the metallization structures within the metallization levels and their connections via the plated-through holes, any interconnection patterns can be integrated in the substrate.
- LTCC Low Temperature Cofired Ceramic
- a substrate with bondable pads and a device chip with bond pads are first provided on its front side.
- the bond pads are designed such that the bondable surface protrudes above the surface of the passivation and preferably partially overlaps the passivation.
- the component chip is glued to the intended place on the substrate. It is possible to simultaneously use a corresponding "die-flag" to produce on the substrate an electrical backside connection of the chip. However, it is also possible to stick the chip in purely mechanically and to contact electrically only via bonding wires. This is done by bonding a bonding wire with the "ball” onto the pads on the substrate, then bending the bond wire into a flat loop so that it extends close to the surface of the device chip to the bond pad, directly to the surface of the bond pad on the outside pointing surface of the component chip is now the wedge (or stitch) set, in which the
- Wire end of the bonding wire is placed flat or parallel to the bond pads aligned and bonded.
- the bonding process may include an ultrasonically assisted thermal compression process or a so-called friction welding in which the pressure force, temperature and ultrasound interact and establish the bond.
- the bond pad projecting beyond the passivation on the upward-pointing surface of the chip contributes to the fact that during the bonding process no direct action of the bonding tool - a wire-carrying capillary - on the passivation on the component chip takes place. This avoids damage to the passivation.
- the wire By bonding the wire is torn off behind the wedge or squeezed through the capillary.
- a stud bump is then placed over the wedge bond by melting the end of another bond wire into a ball and placing it on the bond site. After bonding, the excess wire is torn off leaving only the stud bump, the bond wire bonded to the end of the wedge, and the underlying bond wire Bondpad contacted and thus increases the strength of the wedge bond connection.
- a number of wire bond connections corresponding to the number of contacts to be produced are produced according to the method just described. Subsequently, further possibly different component chips can be applied in the same or in flip-chip technology on the substrate, and optionally SMD components. It may make sense to produce the bonding wire connections for all the chips to be bonded on a substrate in a common method step.
- FIG. 1 shows a schematic cross-section of conventional wire bond connections on a module
- Figure 2 shows a module with inventive
- FIG. 3 shows the production of the new bonding connection in comparison to a known ball stitch method.
- FIG. 4 shows a wedge fastened with an additional studbump.
- FIG. 1 shows a schematic cross-section of an exemplary module with a glued-on component chip BC, which is connected to the substrate SU via conventional and therefore known bonding wire connections.
- bondable pads AF On the substrate are bondable pads AF, arranged on the back of the component chip BC bondable bond pads BP.
- both a standard ball stitch bonding according to the left bonding wire BDI and a reverse stand off stitch bonding (reverse bonding SSB) corresponding to the second bonding wire BD2 on the right side are shown.
- the bond wire end BS melted into a ball is first placed on the component chip or its bond pad and then pulled to the termination surface AF on the substrate SU, where a wedge bond WB is performed.
- SMD components SMD can be arranged on the substrate SU. These usually have a component height that exceeds that of a component chip. While a device chip applied as bare die can be realized in a standard thickness of, for example, 200 ⁇ m, an SMD component requires a device height of typically 500 ⁇ m.
- the module is also provided with a glob top cover GT, which is applied so thickly that the bonding wires BD are securely covered. This leads to a component height of at least d2, in the case of using SMD components to a component height d3, where d3 is larger d2.
- FIG. 2 shows a component chip BC contacted according to the invention.
- the device chip BC is glued to a substrate SU.
- a bonding wire BD is bonded with its ball BS on the pad AF directly on the substrate.
- the bonding wire is then drawn onto the upper side towards the bonding pads BP and bonded there directly to the bonding pad BP with a wedge connection WB. It turns out that the bonding wire can be guided in this way close to the component chip BC and leads only to a small projection over the component chip height.
- the total height of the component d4 ' measured from the substrate to the highest bonding wire loop, is only insignificantly higher than the thickness of the component chip BC.
- connection surfaces AF can be connected via plated-through holes DK with a metallization plane Ml hidden in the interior of the substrate. This can be connected via further plated-through holes to further metallization levels, metallization structures being produced in each metallization level a connection or for the realization of passive component structures are arranged. External contacts of the module can be arranged on the underside of the substrate SU.
- the design according to the invention results in a height-reduced component which is realized even with a glob top cover with a smaller thickness of the glob top cover can.
- a thinner glob top cover leads to lower shear forces at the interface to the component chip BC or to the substrate SU, which thus less load the bond connections and the chip when the thermal cycling stresses acting on the module.
- FIG. 3 compares a known bond pad on the chip top side of a component chip BC with an embodiment of a bond pad that is advantageous for the new bonding method.
- FIG. 3A shows the known bonding pad during the production of a bonding wire connection according to the reverse SSB method.
- the bonding pad has a base metallization GM and above a reinforcing layer VS, which is characterized in particular by its bondability, for example a gold surface.
- a passivation layer PS is applied to the chip surface and structured in such a way that a region of the bond pad is exposed. Usually, the edges of the passivation layer overlap the bonding pad.
- a Stud-Bump SB is then bonded onto which a wedge can subsequently be placed in the reverse SSB method.
- the bonding tool from the here only the bonding wire leading capillary K is shown, the bonding wire BD on the Stud Bump SB, it binds him there firmly and then tears or squeezes him off.
- FIG. 3B shows a novel embodiment of the bondpad, in which initially a base metallization for the bondpad is produced on the substrate surface SU. Subsequently, the passivation is generated and optionally structured. Only after the passivation PS has been produced is a reinforcing layer VS applied over the bonding pad, for example by galvanic growth of a corresponding metal layer. This causes the edges of the reinforcing layer to grow over the edges of the passivation layer and eventually even overlap. Overall, the reinforcing layer is applied at a height such that it protrudes above the upper edge of the passivation layer. This supernatant replaces the stud bump of the conventional reverse SSB method.
- Such a bonding pad surface raised above the surface of the passivation layer allows a problem-free direct bonding of a bonding wire end in the reverse ball-stitch method on the surface of the amplifier layer, without damaging the passivation layer PS with the capillary K.
- FIG. 4 shows, in a schematic cross-section, how such a wire-bonded wire end is additionally fastened with a stud-bump SB, which is bonded directly onto the bond pad BP above the torn-off wire end.
- the invention illustrated and explained only with reference to a few embodiments is not limited to the embodiments. Variation possibilities arise, in particular, in the type and number of components to be applied to the substrate. elements, which are applied as Bare Dies, for example. These may represent ICs or other active semiconductor devices.
- the bare Die can also be a piezoelectric chip.
- the device chip may have device structures on both surfaces and additionally within the chip. On the side to be stuck, it may have a base metallization or a ground contact.
- An inventive module with minimized module height dispenses with SMD components.
- the invention is not limited to modules without SMD components.
- the arranged on the substrate components and device chips can have different heights, accordingly, the Glob Top cover can be designed in such a stepped manner that all components are just just covered by Glob Top or MoId (by injection molding).
- the invention is also not limited to substrates from LTCC. Also possible are polymer substrates which, however, exhibited a thermal expansion behavior relative to the LTCC, which is less adapted to the expansion behavior of conventional device chips and in particular of semiconductors.
- An inventive module can also be realized without Glob top cover, in which case, however, a different type of cover is required for protecting the bonding wire connections, for example a cap or the like.
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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DE102006033222.9A DE102006033222B4 (en) | 2006-07-18 | 2006-07-18 | Module with flat structure and procedure for assembly |
PCT/DE2007/001155 WO2008009262A2 (en) | 2006-07-18 | 2007-06-29 | Module having a flat structure, and equipment method |
Publications (1)
Publication Number | Publication Date |
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EP2041783A2 true EP2041783A2 (en) | 2009-04-01 |
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Application Number | Title | Priority Date | Filing Date |
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EP07785583A Withdrawn EP2041783A2 (en) | 2006-07-18 | 2007-06-29 | Module having a flat structure, and equipment method |
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US (1) | US20090174054A1 (en) |
EP (1) | EP2041783A2 (en) |
JP (1) | JP2009544159A (en) |
KR (1) | KR20090051740A (en) |
CN (1) | CN101490832A (en) |
DE (1) | DE102006033222B4 (en) |
WO (1) | WO2008009262A2 (en) |
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Publication number | Priority date | Publication date | Assignee | Title |
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US20100181675A1 (en) * | 2009-01-16 | 2010-07-22 | Infineon Technologies Ag | Semiconductor package with wedge bonded chip |
JP5062283B2 (en) * | 2009-04-30 | 2012-10-31 | 日亜化学工業株式会社 | Semiconductor device and manufacturing method thereof |
JP2012205093A (en) * | 2011-03-25 | 2012-10-22 | Nippon Dempa Kogyo Co Ltd | Oscillator |
JP2013084848A (en) * | 2011-10-12 | 2013-05-09 | Asahi Kasei Electronics Co Ltd | Semiconductor device and wire bonding method |
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-
2006
- 2006-07-18 DE DE102006033222.9A patent/DE102006033222B4/en not_active Expired - Fee Related
-
2007
- 2007-06-29 KR KR1020097003246A patent/KR20090051740A/en not_active Application Discontinuation
- 2007-06-29 JP JP2009519785A patent/JP2009544159A/en not_active Withdrawn
- 2007-06-29 WO PCT/DE2007/001155 patent/WO2008009262A2/en active Application Filing
- 2007-06-29 CN CNA2007800269887A patent/CN101490832A/en active Pending
- 2007-06-29 EP EP07785583A patent/EP2041783A2/en not_active Withdrawn
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2009
- 2009-01-12 US US12/352,436 patent/US20090174054A1/en not_active Abandoned
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WO2008009262A3 (en) | 2008-04-03 |
CN101490832A (en) | 2009-07-22 |
DE102006033222B4 (en) | 2014-04-30 |
JP2009544159A (en) | 2009-12-10 |
DE102006033222A1 (en) | 2008-01-24 |
KR20090051740A (en) | 2009-05-22 |
US20090174054A1 (en) | 2009-07-09 |
WO2008009262A2 (en) | 2008-01-24 |
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