Classifications

• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B19/00—Programme-control systems
  • G05B19/02—Programme-control systems electric
  • G05B19/18—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form
  • G05B19/414—Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
  • G05B19/4148—Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller characterised by using several processors for different functions, distributed (real-time) systems
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B2219/00—Program-control systems
  • G05B2219/20—Pc systems
  • G05B2219/23—Pc programming
  • G05B2219/23445—Real time simulation
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B2219/00—Program-control systems
  • G05B2219/20—Pc systems
  • G05B2219/23—Pc programming
  • G05B2219/23446—HIL hardware in the loop, simulates equipment to which a control module is fixed

Definitions

• the present invention relates generally to motion controllers and simulation systems including motion controllers.
• Motion controllers are components that range from ON/OFF devices with simple linear controllers to complex, user programmable modules that act as controllers within complex integrated multi-axis motion systems.
• a motion controller can be used in flight simulator systems.
• a simulation computer supplies position, velocity, and acceleration (PVA) demands for three (3) or more axes of motion to the controller on a precise periodic schedule, for example, one PVA demand set per axis each millisecond.
• PVA position, velocity, and acceleration
• the simulation computer supplies a piece-wise motion trajectory over time that the motion controller ensures the physical axis follows the supplied motion trajectory.
• the simulation computer can also read measurements, or readouts, from the motion controller of the actual physical axis PVA. The simulation computer can then use this data to modify its subsequent PVA demand set(s).
• This control mode represents a form of testing known as hardware-in- the-loop (HWEL) testing, wherein a larger control-loop is formed around the seeker and the flight motion simulator, of which the motion controller is an essential component.
• HWEL hardware-in- the-loop
• PC personal computer
• DSP digital signal processor
• the daughter card(s) execute the control algorithms for one or more axes and normally exist as slaves on a communication bus mastered by the PC.
• this bus is an industry-standard parallel input/output (FO) bus such as ISA bus or a Peripheral Component Interconnect (PCI) bus.
• FO parallel input/output
• PCI Peripheral Component Interconnect
• PC 30 supervises the start-up, shut-down, and run-time operations of motion controller 20 while also generally maintaining the demand and readout PVA data transactions for all simulator axes by moving data between one or more DSP cards 40 and a reflective memory interface (RMI) 50.
• RMI 50 of motion controller 20 is, like DSP card(s) 40, yet another slave card on VO bus 60 of PC 30.
• RMI card 50 of motion controller 20 is in communicative connection with a corresponding RMI card 70 residing within a simulation computer 80 via, for example, an ultra high-speed communications link such as a fiber optic link 90.
• This arrangement yields extremely low data communication latencies between reflected (that is, identical content maintained) memory on RMI card 50 and RMI card 70. This low latency is important in minimizing the phase margin of, and thereby enhancing the stability of, HWEL control system 10.
• PC 30 In its function as the I/O bus master of motion controller 20, PC 30 must: (i) Quickly recognize, whether by polling or via an interrupt from the RMI card 50, that a new block of multi-axis demand PVA data is available in the memory of simulator RMI card 70; (ii) Read (whether by programmed I/O into PC memory or via direct memory access (DMA)) the block of demand PVA data and then write (distribute) the demand PVA data to the appropriate DSP card(s) 40; (iii) Read (whether by programmed I/O into PC memory or via direct memory access (DMA)) the readout PVA data from DSP card(s) 40 and then write the resulting block of multi-axis readout PVA data to the memory of RMI card 50; and (iv) Set a flag variable in the memory of RMI card 50 to signal simulation computer 60 that the demand block / readout block transaction is complete.
• DMA direct memory access
• RTOS real time operating system
• a number of such RTOS 's are commercially available.
• a real-time operating system or RTOS schedules tasks to be performed according to a set of established priorities. Such tasks typically follow a predictable schedule of execution.
• RTOS graphical user interface
• file system as, for example, provided with Microsoft Windows ®
• the present invention provides a motion controller including a computer comprising a primary processor or a central processing unit and an input/output communication bus.
• the primary processor is in communicative connection with the bus and is adapted to communicate with at least one other device (or with other devices) in communicative connection with the bus via the bus.
• the motion controller also includes at least one secondary processor in communicative connection with the bus.
• the secondary processor is adapted to execute at least one control algorithm for one or more axes of motion associated therewith.
• the secondary processor is further adapted to communicate with at least one other device (or with other devices) in communicative connection with the bus via the bus independently of the primary processor (that is, the secondary processor can effect bus mastering).
• the operating system of the computer can, for example, be a general purpose operating system (and not a real time operating system as described above).
• the input output communication bus can, for example, be a PCI bus.
• PCI bus One skilled in the art appreciates, however, that many other types of buses can be used.
• the motion controller can further include at least one reflective memory interface in communicative connection with the bus.
• the reflective memory interface is adapted to communicate data with another reflective memory interface of a simulation computer.
• the reflective memory interface of the motion controller can, for example, be in communication with the reflective memory interface of the simulation computer via a high speed data link such as a fiber optic communication link.
• the secondary processor is operable to poll the reflective memory interface of the motion controller via the bus to determine whether new data has been received by the reflective memory interface of the motion controller from the reflective memory interface of the simulation computer, read any new data via the bus, store any new data in a local memory in communicative connection with the secondary processor, and write output data determined from any new data to the reflective memory interface of the motion controller via the bus.
• the secondary processor can further be operable to set a flag variable in memory of the reflective memory interface of the motion controller to provide an indication that the secondary processor has completed a data input/data output transaction for the one or more axes of motion associated therewith.
• the secondary process can, for example, be a component of a digital signal processing card.
• the digital signal processing card is operable as a slave card and a bus mastering card, wherein the digital signal processing card periodically requests temporary mastering of the bus from the primary processor.
• the secondary processor polls the reflective memory interface of the motion controller via the bus to determine whether new data has been received by the reflective memory interface of the motion controller from the reflective memory interface of the simulation computer, reads any new data via the bus, stores any new data in a local memory in communicative connection with the secondary processor, and writes output data determined from any new data to the reflective memory interface of the motion controller via the bus.
• the secondary processor of the digital signal processing card can relinquish bus mastership to the primary processor upon completion of a data transaction with the reflective memory interface of the motion controller.
• Data read from the reflective memory interface of the motion controller by the secondary processor can, for example, include position, velocity and acceleration data for the one or more axes of motion associated with the secondary processor.
• Data written to memory of the reflective memory interface of the motion controller by the secondary processor can, for example, include position, velocity and acceleration data for the one or more axes of motion associated with the secondary processor.
• the present invention provides a simulation system including a motion controller including a motion controller computer having a primary processor and an input/output communication bus.
• the primary processor is in communicative connection with the bus and is adapted to communicate with at least one other device (or with other devices) in communicative connection with the bus via the bus.
• the motion controller further includes at least one secondary processor in communicative connection with the bus.
• the secondary processor is adapted to execute at least one control algorithm for one or more axes of motion associated therewith.
• the secondary processor is further adapted to communicate with at least one other device (or with other devices) in communicative connection with the bus via the bus independently of the primary processor.
• the motion controller also includes at least one reflective memory interface in communicative connection with the bus.
• the simulation system further includes a simulation computer including a processor and a reflective memory interface and a communication line between the reflective memory interface of the motion controller and the reflective memory interface of the simulation computer.
• the present invention provides a method of effecting motion control including: providing a computer including a primary processor and an input/output communication bus, the primary processor being in communicative connection with the bus and being adapted to communicate with at least one other device (or with other devices) in communicative connection with the bus via the bus; providing at least one secondary processor in communicative connection with the bus, the secondary processor being adapted to execute a control algorithms for one or more axes of motion associated therewith; and having the secondary processor communicate with at least one other device (or with other devices) in communicative connection with the bus via the bus independently of the primary processor.
• the present invention provides an expansion or processing card for use with a computer.
• the computer includes a central processing unit and a computer input/output communication bus in communicative connection with the central processing unit.
• the expansion card includes a connector to place the card in communicative connection with the computer communication bus, a local input/output communication bus in communicative connection with the connector, at least one secondary processor in communicative connection with the local communication bus, a memory in communicative connection with the local communication bus, and at least one communication port in communicative connection with the local communication bus and being adapted to be placed in communicative connection with at least one component associated with at least one axis of motion to be controlled.
• the secondary processor is adapted to execute at least one control algorithm for the at least one axis of motion and to communicate with at least one other device (or with other devices) in communicative connection with the computer communication bus via the bus independently of the central processing unit.
• Figure 1 illustrates a schematic representation of a currently available hardware in the loop motion controller.
• Figure 2 illustrates an embodiment of a motion controller and simulation system of the present invention.
• Figure 3 illustrates an embodiment of a digital signal processor card for use in the present invention.
• Figure 4 illustrates another embodiment of a motion controller and simulation system of the present invention wherein multiple digital signal processors are illustrated in communicative connection with an I/O bus of a PC and with a flight motion table.
• Figure 5 illustrates an embodiment of a sequencing relationship between a simulation computer and the digital signal processing cards of a motion controller such as illustrated in Figure 4 of the present invention.
• Figure 6 illustrates a representative processing sequence for digital signal processing cards
• a motion controller 120 (forming part of an HWEL control system 110) of the present invention includes commercially available PC hardware (for example, a PC 130 including, for example, a processor 132, such as available from Intel of Santa Clara, California, and a memory 134).
• Motion controller 120 provides a substantial improvement over traditional HWIL motion controller (for example, as illustrated in Figure 1) by utilizing a feature of an FO bus such as a PCI or other data/communication bus 160 referred to as bus mastering.
• processor 132 of PC 130 is not the sole master of I/O bus 160 of PC 130.
• bus mastering refers to the capability of devices on PCI bus 160 (other than the PC system chipset or processor 132) to take control of bus 160 and perform transfers directly.
• DSP card(s) 140 of the present invention which include DSP memory 142 and DSP controller 144, are designed or adapted to periodically request temporary mastership of PCI bus 160 from PC 130.
• each DSP card 140 When granted mastership, each DSP card 140: (i) Polls (via PCI bus 160) for an indication that a new block of multi-axis demand PVA data is available in memory 172 of RMI card 170 of simulator computer 180 (Since DSP card 140 is generally optimized for speed and utilizes no operating system, the latency of detecting new data blocks, and acting once a new data block is detected, is less than the case in which a PC (such as PC 30 in system 10) acts as an intermediary.); (ii) Reads (via PCI bus I/O code programmed on DSP card 140) the demand PVA data intended for its axes of control and stores the data in local DSP memory 142; (iii) Writes (via PCI bus VO code programmed on DSP card 140) the readout PVA data for its axes of control to memory 152 of RMI card 150 and (iv) Sets a flag variable in the memory 152 of RMI card 150 to signal that the particular DSP card 140 has completed its
• each DSP card 140 relinquishes PCI bus 160 mastership back to PC 130 and becomes a slave again.
• PC 130 may then read and write to DSP card(s) 140 as slaves, for example, to maintain a local GUI, or to any other PCI slave devices residing on PCI bus 160, as normal.
• PC 130 By pushing the hard real-time requirement for RMI data FO down to DSP card(s) 140 where the data is actually utilized or produced.
• PC 130 is relieved of the need for tightly bounded timeliness, even in HWLL applications.
• This approach of the present invention permits PC 130 to execute a GPOS, such as MICROSOFT WINDOWS®, that is more suited for its remaining purposes (including, but not limited to, supervisory functions, providing a local GUI, and providing soft real-time communications interfaces such as Ethernet, IEEE-488, or RS-232).
• GPOS such as MICROSOFT WINDOWS®
• motion controller 120 reduces both cost and complexity while also providing the benefits of a true MICROSOFT WINDOWS (or other GPOS) local user interface and lowered latency HWIL data I/O.
• FIG 3 illustrates an embodiment of a DSP card 140 suitable for use in the present invention.
• DSP card 140 includes a controller or digital signal processor 144 (for example, DSP 2106XP available for Analog Devices, Inc.) and a memory (for example, SRAM) in communication with DSP controller 144 via DSP local data/communications bus 143.
• a field programmable gate array (FPGA) 145 (for example, available from Altera) is also in communicative connection with DSP local data/communication bus 143 and provides (via, a serializer/deserializer 147) for input/output communication with input/output cards 148 in communicative connection with the axes of control (position transducers, inputs, motor torque outputs etc.).
• FPGA field programmable gate array
• FPGA 145 also includes a communication or connector bridge 146 (for example, a PCI connector bridge as known in the art) for communication with communication/data bust 160.
• a communication or connector bridge 146 for example, a PCI connector bridge as known in the art
• several pins on DSP PCI bus connector 146 were reserved for bus mastering.
• any device having bus mastering capability can take control of the bus at any time, even allowing it to shut out motherboard CPU 134.
• PCI bus master devices use bandwidth as available and can potentially use all bandwidth in the system if no other devices are requesting it.
• Bus mastering is initiated by a bus mastering device such as DSP card 140 sending a request signal when it requires control of communication/data bus 160 to a central resource (not shown), which is embodied as circuitry on the motherboard of PC 130 shared by all bus devices. Bus control is relinquished to the device when a grant signal is received.
• PCI bus mastering is specified, for example, in technical detail in the PCI Local Bus Specification, Revision 2.3, available from PCI Special Interest Group (SIG) of Hillsboro, Oregon (www.psisig.com), the disclosure of which is incorporated herein by reference.
• Figure 4 illustrates another embodiment of a hardware-in-the-loop simulation system 210 and motion controller 220 of the present invention that operates essentially in the manner described above for simulation system 110 and motion controller 120.
• Components of simulation system 210 are numbered similarly to corresponding components of simulation system 110 with 100 added to each designation numeral.
• Motion controller 220 includes two DSP cards 240a and 240b, each of which can control one or more axes of control of a controlled element 300 (for example, a flight motion table or rate table simulating the motion of a missile, an aircraft, a launch vehicle, an unmanned aerial vehicle, an automobile etc. ).
• a controlled element 300 for example, a flight motion table or rate table simulating the motion of a missile, an aircraft, a launch vehicle, an unmanned aerial vehicle, an automobile etc.
• flight motion table 300 includes two axes of control 310a and 310b in operative connection with bus mastering DSP cards 240a and 240b, respectively (as described above in connection with Figures 2 and 3).
• Suitable flight motion tables for use in the present invention are, for example, available from Ideal Aerosmith, Inc. of East Grand Forms, Minnesota.
• Flight motion table 300 is mechanically coupled to a guidance system 400 under test.
• guidance system 300 includes a processor or controller 310 in operative connection with inertial sensors 320.
• Processor 310 is, for example, operable to execute an auto-pilot program 330, as known in the art.
• Guidance system 300 transmits actuator commands to simulation computer 280 including a processor or controller 282, which executes a vehicle dynamics simulation program stored in a memory 284 thereof.
• simulation computer 280 includes a reflective memory interface card 270 in communicative connection (via, for example, a high-speed communication portal or link 290 (such a fiber optic communication link) with reflective memory interface card 250 of motion controller 220.
• DSP cards 240a and 240b are in communicative connection with communication bus 160 as described above in connection with Figures 2 and 3.
• An embodiment of a sequencing relationship between simulation computer 280 and one of DSP cards 240a and 240b of motion controller 220 is illustrated in Figure 5.
• a representative processing sequence for DSP cards 240a and 240b is set forth in Figure 6.
• all DSP cards in the motion controller (including, for example, DSP cards 240a and 240b of motion controller 220) ran from the same high-accuracy time reference (for example, a 5000Hz time reference) and were, therefore, synchronized.
• Simulation computer 280 has its own high-accuracy time reference or uses the timing reference output of motion controller 220.
• the simulation period of simulation computer 280 can, for example, be an integer multiple of the simulation period of motion controller 220 (in several embodiments, a 200 microsecond period).
• Each of DSP card 240a and 240b is capable of independently arbitrating for, mastering, and then relinquishing control of the communication/data bus 260 under DSP program control.

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• Automation & Control Theory (AREA)
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• 2007
  • 2007-05-21 CA CA002659209A patent/CA2659209A1/en not_active Abandoned
  • 2007-05-21 WO PCT/US2007/011995 patent/WO2007139733A2/en active Application Filing
  • 2007-05-21 EP EP07795070A patent/EP2027514A2/de not_active Ceased

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