EP1999596A2 - Méthode et appareil de redimensionnement dynamique de partitions cache en fonction de la phase d'exécution de tâches - Google Patents

Méthode et appareil de redimensionnement dynamique de partitions cache en fonction de la phase d'exécution de tâches

Info

Publication number
EP1999596A2
EP1999596A2 EP07713173A EP07713173A EP1999596A2 EP 1999596 A2 EP1999596 A2 EP 1999596A2 EP 07713173 A EP07713173 A EP 07713173A EP 07713173 A EP07713173 A EP 07713173A EP 1999596 A2 EP1999596 A2 EP 1999596A2
Authority
EP
European Patent Office
Prior art keywords
cache
task
application
tasks
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07713173A
Other languages
German (de)
English (en)
Inventor
Bijo Thomas
Sriram Krishnan
Milind Manohar Kulkarni
Sainath Karlapalem
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of EP1999596A2 publication Critical patent/EP1999596A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory

Definitions

  • the present invention relates, in general to a data processing system comprising cache storage, and more specifically relates to dynamic partitioning of the cache storage for application tasks in a multiprocessor.
  • Cache partitioning is a well-known technique in multi-tasking systems for achieving more predictable cache performance by reducing resource interference.
  • the cache storage is shared between multiple processes or tasks.
  • the cache storage is partitioned into different sections for different application tasks. It can be advantageous to partition the cache into sections, where each section is allocated to a respective class of processes, rather than the processes sharing entire cache storage.
  • cache storage is divided into a number of sections, the question arises of how to determine the size of cache partition for different application tasks and when to resize the cache partitions.
  • US Patent application 2002/0002657A1 by Henk Muller et al discloses a method of operating a cache memory in a system, in which a processor is capable of executing a plurality of processes.
  • Such techniques partition the cache into many small partitions instead of using one monolithic data-cache in which accesses to different data objects may interfere.
  • the compiler is aware of the cache architecture and allocates the cache partitions to the tasks.
  • Such techniques reserve the partitioned section of the cache for the tasks during its entire duration of execution.
  • static partitioning techniques often result in either suboptimal usage of cache or insufficient reservations of cache partitions.
  • Dynamic partitioning techniques as proposed by Edward Suh et al in "Analytical Cache Models with applications to cache partitioning” attempt to avoid the above said drawback of static partitioning by dynamically resizing the partition sizes. Such techniques do not consider the program characteristics like phased execution of the individual tasks. For instance, the execution behavior of multimedia applications often falls into repeating behaviors (phases), which may have different cache usage characteristics. Effective cache usage can be achieved by determining the partition sizes at the program phase boundaries.
  • Timothy et al have described that it is possible to accurately identify and predict the phases in program behavior [Ref. 2: “Discovering and exploiting program phases", Timothy Sherwood et al].
  • the program (task) behavior in these phases has different resource usage characteristics and can be quantified using performance metrics.
  • An example of such a metric is basic block vector [BBV] described in [Ref. 2].
  • the present invention proposes a method and a system for dynamic cache partitioning for each application task in a multiprocessor.
  • An approach for dynamically resizing cache partitions based on the execution phase of the application tasks is provided.
  • Cache partitions are dynamically resized according to the execution phase of the current task such that, unnecessary reservation of the entire cache is avoided and hence an effective utilization of the cache is achieved.
  • partitioning In a multiprocessor, multitasking scenarios with shared cache/memory, partitioning is often conceived as a mechanism to achieve the predictable performance of the memory subsystem.
  • partitioning schemes are available in the literature such as Way Partitioning (Column Caching), Set Partitioning, etc.
  • Streaming applications adopt a pattern of execution that has distinct phases with distinct durations.
  • the objective of the present invention is to exploit the information regarding the distinct phases of execution of the multimedia application tasks and hence adapt the partition size based on the requirements during their executions phases.
  • Execution phases of the application task (program) can be identified in many ways: one example is by monitoring the working set changes and other methods [Ref. 2].
  • the execution phases of application tasks are defined as the set of intervals within the application task's execution that have similar behaviour, and the working set of the application task is defined as the cache partition requirements of the application task at a particular execution phase.
  • One aspect of the present invention provides a method for dynamically resizing cache partitions based on the execution phase of the application tasks.
  • the execution phases of the application tasks are identified and updated in a tabular form.
  • Cache partitions are resized during a particular instance of the execution of tasks such that the necessary and sufficient amount of cache space is allocated to the tasks at any given point of time.
  • the cache partition size is determined according to the working set requirement of the tasks during its execution, which is monitored dynamically or statically.
  • Another aspect of the present invention provides a computer system for dynamically resizing cache partitions for the application tasks in a multiprocessor.
  • the system comprises a task phase monitor for monitoring the working set variations of application tasks which can be either monitored dynamically or the information can be collected statically and stored in the same.
  • the phase information of the tasks is stored in a task phase table.
  • the task phase table contains the phase and the cache partition allocated (which is the working set of the application task at the corresponding phase) at the time of switching of the tasks.
  • the system also comprises of a cache allocation controller for allocating maximum cache size when a new application task interrupts a currently executing task.
  • the cache allocation controller looks at the working set requirements of the new application task and partitions the cache by allocating maximum possible cache size to the new task.
  • the cache storage allocation is done according to the phase of the new application task.
  • One object of the present invention is to devise a method and means for dynamically managing cache partitioning among a plurality of processes executing on a computing system.
  • FIG. 1 illustrates an embodiment of the method of dynamically resizing cache partitions in a multiprocessor for the application tasks.
  • FIG. 2 is a graphical depiction showing the working set variations for an application task.
  • FIG. 3 presents a block diagram illustrating the architecture of an embodiment of a system for dynamically resizing cache partitions for the application tasks.
  • FIG. 4 illustrates a task phase table for storing information of application tasks.
  • FIG. 5 illustrates a snapshot depicting an example of cache requirements for two application tasks (Tl and T2).
  • FIG. 6 illustrates the cache partitioning scenario for the example shown in FIG. 5 when a new application task, T3, interrupts the currently executing application tasks (Tl and T2).
  • FIG. 1 illustrates an embodiment of the method of dynamically resizing cache partitions in a multiprocessor for the application tasks.
  • BBV basic block vector
  • the execution phases of each of the application task is identified 101.
  • the phase information and working set of an application task is stored in tabular form 102. This phase information is then utilized for dynamically configuring the cache partition depending on the execution phase of the application task 103.
  • the cache partitions are resized during a particular instance of the execution of application tasks such that the necessary and sufficient amount of cache space is allocated to the application tasks at any time.
  • the cache partition size is determined according to the working set requirement of the tasks during its execution.
  • the working set requirements of the tasks can be monitored dynamically or statically.
  • FIG. 2 illustrates a graph depicting the working set variations for an application task 201. Variation of the working set W (t) for an application task during the period of execution 'T' of the task is shown in FIG. 2.
  • the working set of the application task varies during its execution period T. Accordingly there are distinct phases Pl, P2 and P3 corresponding to the working sets Wl, W2 and W3.
  • the application task can get switched at any of the phases of its execution. If the cache partition allocated to the application tasks is constant (as in prior art) during its period of execution T, this would result in a redundant blocking of the cache partitions.
  • the cache partition allocated to the application task is equal to that of Wl (bytes), and if the application task switches at P3 (corresponding to W3), then the cache space Wl -W3 is unnecessarily blocked for the application task.
  • FIG. 3 presents a block diagram illustrating the architecture of an embodiment of a system for dynamically resizing cache partitions for the application tasks.
  • the working set variations of the application tasks is monitored by a task phase monitor 301.
  • the working set variations can be either monitored dynamically or the information can be collected statically.
  • This phase information is stored in a task phase table 302.
  • the task phase table 302 contains the phase and the cache partition allocated (which is the working set of the task at the corresponding phase) at the time of switching of the application tasks.
  • the cache allocation controller 303 looks at the working set requirements of the new application task and partitions the cache by allocating maximum possible cache size to the new application task, in observance with the phase of the new application task.
  • FIG. 4 illustrates a task phase table 302 for storing the phase information of application tasks 401.
  • the task phase table 302 includes a separate task ID for each of the application tasks, the phase information of the application task and cache partition size allocated for each application task at the time of switching of tasks.
  • the phase information of the application task is denoted as Pi (Tl), P 2 (T2) and P 3 (T3) respectively for three successive application tasks, Tl, T2 and T3 and Pl, P2, P3 are three distinct phases of the three tasks.
  • the cache partition size allocated for each application task at the time of switching of tasks is denoted as Wl, W2 and W3.
  • FIG. 5 illustrates a snapshot depicting an example of cache requirements for two application tasks 501.
  • Tl and T2 As shown in FIG.5. Assume that the total cache size is 20 lines.
  • the application tasks are running in a multi-tasking mode, switching from one task to the other. After a period of time assume that the execution has resulted in the cache having task Tl in phase P2 (Tl) and task T2 in phase P3 (T2).
  • FIG. 6 illustrates the cache partitioning scenario for two cases of examples 601 when a new application task interrupts a currently executing application task.
  • T3 interrupting task
  • FIG. 5 consider the situation when a new application task T3 (interrupting task) arrives at phase Pl (T3) with a working set requirement of 8 lines.
  • T3 interrupting task
  • the cache size would have been allocated based on maximum cache requirements, i.e., 7 for task Tl and 8 for task T2, over the entire duration of execution. This would have consumed 15 lines until task Tl and task T2 finish their execution.
  • the present invention will find its industrial applications in system on chip (SoC) for audio, video and mobile applications.
  • SoC system on chip
  • the present invention will improve the cache utilization by avoiding unnecessary reservation of the cache partitions for the executing application tasks during the entire duration of their execution. So an effective utilization of the cache storage is achieved.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

La présente invention concerne une méthode et un système de partitionnement dynamique de cache pour les tâches d'application d'un multiprocesseur. L'invention concerne également une approche de redimensionnement dynamique de partitions cache en fonction de la phase d'exécution de tâches d'application. Les phases d'exécution de tâches d'application sont identifiées et mises à jour sous forme de tableau. Les partitions cache sont redimensionnées pendant une instance particulière de l'exécution des tâches d'application de façon à ce que la quantité nécessaire et suffisante d'espace cache soit à tout instant allouée aux tâches d'application. La taille d'une partition cache est déterminée selon l'exigence d'espace de travail d'une tâche pendant son exécution qui est surveillée dynamiquement ou statiquement. Les partitions cache sont redimensionnées dynamiquement en fonction de la phase d'exécution de la tâche de façon à ce qu'une réservation inutile de la totalité du cache soit évitée, ce qui permet une utilisation efficace du cache.
EP07713173A 2006-03-02 2007-02-24 Méthode et appareil de redimensionnement dynamique de partitions cache en fonction de la phase d'exécution de tâches Withdrawn EP1999596A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US77927106P 2006-03-02 2006-03-02
PCT/IB2007/050593 WO2007099483A2 (fr) 2006-03-02 2007-02-24 Méthode et appareil de redimensionnement dynamique de partitions cache en fonction de la phase d'exécution de tâches

Publications (1)

Publication Number Publication Date
EP1999596A2 true EP1999596A2 (fr) 2008-12-10

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Country Link
US (1) US20110113215A1 (fr)
EP (1) EP1999596A2 (fr)
JP (1) JP2009528610A (fr)
CN (1) CN101395586A (fr)
WO (1) WO2007099483A2 (fr)

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CN107329911B (zh) * 2017-07-04 2020-07-28 国网浙江省电力公司信息通信分公司 一种基于cp-abe属性访问机制的缓存替换方法
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Publication number Publication date
CN101395586A (zh) 2009-03-25
WO2007099483A2 (fr) 2007-09-07
JP2009528610A (ja) 2009-08-06
WO2007099483A3 (fr) 2008-01-03
US20110113215A1 (en) 2011-05-12

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