EP1960863A2 - Stockage de fichier adresse logiquement - Google Patents

Stockage de fichier adresse logiquement

Info

Publication number
EP1960863A2
EP1960863A2 EP06848548A EP06848548A EP1960863A2 EP 1960863 A2 EP1960863 A2 EP 1960863A2 EP 06848548 A EP06848548 A EP 06848548A EP 06848548 A EP06848548 A EP 06848548A EP 1960863 A2 EP1960863 A2 EP 1960863A2
Authority
EP
European Patent Office
Prior art keywords
host
file
sectors
data
logical address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP06848548A
Other languages
German (de)
English (en)
Inventor
Alan Welsh Sinclair
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Technologies LLC
Original Assignee
SanDisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/302,764 external-priority patent/US7877540B2/en
Priority claimed from US11/300,568 external-priority patent/US20070136553A1/en
Application filed by SanDisk Corp filed Critical SanDisk Corp
Publication of EP1960863A2 publication Critical patent/EP1960863A2/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G06F3/0605—Improving or facilitating administration, e.g. storage management by facilitating the interaction with a user or administrator
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/0643—Management of files
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7202—Allocation control and policies

Definitions

  • This application relates to the operation of re-programmable nonvolatile memory systems such as semiconductor flash memory, and, more specifically, to the management of data within such a memory.
  • All patents, patent applications, articles and other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes.
  • Flash memory systems are most commonly provided in the form of a memory card or flash drive that is removably connected with a variety of hosts such as a personal computer, a camera or the like, but may also be embedded within such host systems.
  • the host When writing data to the memory, the host typically assigns unique logical addresses to sectors, clusters or other units of data within a continuous virtual address space of the memory system.
  • DOS disk operating system
  • the host writes data to, and reads data from, addresses within the logical address space of the memory system.
  • a controller within the memory system translates logical addresses received from the host into physical addresses within the memory array, where the data are actually stored, and then keeps track of these address translations.
  • the data storage capacity of the memory system is at least as large as the amount of data that is addressable over the entire logical address space defined for the memory system.
  • a common prior interface between a host and a memory system uses a logical addressing scheme for sectors of data stored by the memory.
  • host files often become logically fragmented when they are mapped to a logical address space and as a result they may be distributed widely throughout the memory array. This can make managing the memory array more difficult because blocks in the memory array contain portions of many files and therefore often contain a mix of valid and obsolete data. In order to reclaim the space occupied by obsolete data, it may be necessary to copy a large amount of valid data.
  • a memory system receives data from a host that uses a logical addressing scheme.
  • the host first maps host files to a logical address space. Then, the host provides the memory system with signals that indicate "which file a particular sector of host data is allocated to. Subsequently, when the sector of host data is received by the memory system, the memory system uses the allocation information that it previously received to determine where to store the sector of host data. Specifically, the memory system puts sectors from the same host file in the same metablock of the memory array. A file may occupy more than one metablock in this way. The host also signals when the end of a host file has been sent so that the memory system may close the file and perform operations to more efficiently store the file.
  • a notification scheme used by a host to inform a memory system of the allocation of sectors of data uses Directory and FAT sectors so that the signals of the notification scheme are compatible with prior logical interfaces.
  • the start of a new file is identified by a Directory sector that indicates the first cluster of the file.
  • the sectors of that cluster are sent, they are stored in a new metablock. Any cluster that is logically sequential to the previous cluster received may be presumed to be from the same file as the previous cluster.
  • the host indicates this change.
  • the host sends a Directory sector to indicate the start of a new file. If the new cluster is from an open file (sectors from this file previously sent and stored in one or more metablocks for the file), then the host sends a FAT sector including a FAT entry for the previous cluster of the open file including a pointer to the new cluster. In addition to sending signals to indicate file allocation information, the host may send a FAT sector to indicate the end of a file. Such a FAT sector contains an entry for the last cluster of the file indicating an End of File.
  • the present scheme sends the allocation information before sending the host data to which it refers. Also, most prior schemes do not provide for the memory system to use allocation information sent by the host as FAT and Directory sectors.
  • a memory system may use file allocation information provided by the host to keep data of a particular host file together. Even though the host file may be logically fragmented when it is mapped by the host to a logical address range, the memory system can use the information regarding this mapping to store data of a file in a dedicated block. Thus, a new block is opened when the host indicates the start of a new file. Subsequently, any data indicated as being from that block is stored in the same metablock. Additional metablocks are opened for the file as necessary. Eventually, the host indicates the end of the file, or the memory system closes the file for some other reason.
  • a notification scheme may also allow a host to inform a memory system when power is about to be removed so that the memory system can prepare for power loss (e.g. by storing any data in volatile memory to nonvolatile memory).
  • a notification scheme may also allow a host to inform a memory system when power will be maintained so that the memory system can perform housekeeping operations such as reclaim operations.
  • Figure 1 schematically illustrates a host and a connected non-volatile memory system as currently implemented
  • Figure 2 is a block diagram of an example flash memory system for use as the non-volatile memory of Figure 1;
  • Figure 3 is a representative circuit diagram of a memory cell array that may be used in the system of Figure 2;
  • Figure 4 illustrates an example physical memory organization of the system of Figure 2
  • Figure 5 shows an expanded view of a portion of the physical memory of Figure 4.
  • Figure 6 shows a further expanded view of a portion of the physical memory of Figures 4 and 5;
  • Figure 7 illustrates a common logical address interface between a host and a reprogrammable memory system
  • Figure 8 illustrates a file interface between a host and a reprogrammable memory system
  • Figure 9 illustrates a logical address interface used with logical address-to logical file conversion by a memory system
  • Figure 10 illustrates a logical interface between a host and a memory system with logical-to-physical address translation in the memory system being dependent on file-to-logical address information received from the host;
  • Figure 11 illustrates the logical interface of Figure 10 with a file logically fragmented by a host and subsequently defragmented by the memory system when it is stored;
  • Figure 12 illustrates the storage of file allocation information for files
  • Figure 13 illustrates operation of a notification scheme for host file A sent as logically sequential clusters of host data
  • Figure 14 illustrates operation of a notification scheme for host file B sent as clusters of host data including a jump in logical address
  • Figure 15A illustrates the storage of file allocation information for files C and D in a memory system including a Directory and File Allocation Table (FAT);
  • FAT Directory and File Allocation Table
  • Figure 15B illustrates a notification scheme for host files C and D that are sent as logically sequential clusters that alternate between clusters of sectors of file C and file D.
  • a current flash memory system and a typical operation with host devices are described with respect to Figures 1 — 7. It is in such a system that the various aspects of the present invention may be implemented.
  • a host system 1 of Figure 1 stores data into and retrieves data from a flash memory 2.
  • the flash memory can be embedded within the host, the memory 2 is illustrated to be in the more popular form of a card that is removably connected to the host through mating parts 3 and 4 of a mechanical and electrical connector.
  • flash memory cards There are currently many different flash memory cards that are commercially available, examples being the CompactFlash (CF), the MultiMediaCard (MMC), Secure Digital (SD), miniSD, Memory Stick, SmartMedia and TransFlash cards.
  • each of these cards has a unique mechanical and/or electrical interface according to its standardized specifications, the flash memory included in each is very similar.
  • These cards are all available from SanDisk Corporation, assignee of the present application.
  • SanDisk also provides a line of flash drives under its Cruzer trademark, which are hand held memory systems in small packages that have a Universal Serial Bus (USB) plug for connecting with a host by plugging into the host's USB receptacle.
  • USB Universal Serial Bus
  • Each of these memory cards and flash drives includes controllers that interface with the host and control operation of the flash memory within them. [0028]
  • Host systems that use such memory cards and flash drives are many and varied.
  • PCs personal computers
  • PDAs personal digital assistants
  • digital still cameras digital movie cameras
  • portable audio players personal computers
  • the host typically includes a built-in receptacle for one or more types of memory cards or flash drives but some require adapters into which a memory card is plugged.
  • the host system 1 of Figure 1 may be viewed as having two major parts, insofar as the memory 2 is concerned, made up of a combination of circuitry and software. They are an applications portion 5 and a driver portion 6 that interfaces with the memory 2.
  • the applications portion 5 can include a processor running word processing, graphics, control or other popular application software.
  • the applications portion 5 includes the software that operates the camera to take and store pictures, the cellular telephone to make and receive calls, and the like.
  • the memory system 2 of Figure 1 includes flash memory 7, and circuits 8 that both interface with the host to which the card is connected for passing data back and forth and control the memory 7.
  • the controller 8 typically converts between logical addresses of data used by the host 1 and physical addresses of the memory 7 during data programming and reading.
  • circuitry of a typical flash memory system that may be used as the non-volatile memory 2 of Figure 1 is described.
  • the system controller is usually implemented on a single integrated circuit chip 11 that is connected in parallel with one or more integrated circuit memory chips over a system bus 13, a single such memory chip 15 being shown in Figure 2.
  • the particular bus 13 that is illustrated includes a separate set of conductors 17 to carry data, a set 19 for memory addresses and a set 21 for control and status signals.
  • a single set of conductors may be time shared between these three functions.
  • other configurations of system buses can be employed, such as a ring bus that is described in United States Patent Application No.
  • a typical controller chip 1 1 has its own internal bus 23 that interfaces with the system bus 13 through interface circuits 25.
  • the primary functions normally connected to the bus are a processor 27 (such as a microprocessor or microcontroller), a read-only-memory (ROM) 29 containing code to initialize (“boot") the system, read-only-memory (RAM) 31 used primarily to buffer data being transferred between the memory and a host, and circuits 33 that calculate and check an error correction code (ECC) for data passing through the controller between the memory and the host.
  • a processor 27 such as a microprocessor or microcontroller
  • ROM read-only-memory
  • RAM read-only-memory
  • ECC error correction code
  • the controller bus 23 interfaces with a host system through circuits 35, which, in the case of the system of Figure 2 being contained within a memory card, is done through external contacts 37 of the card that are part of the connector 4.
  • a clock 39 is connected with and utilized by each of the other components of the controller 11.
  • the memory chip 15, as well as any other connected with the system bus 13, typically contains an array of memory cells organized into multiple sub-arrays or planes, two such, planes 41 and 43 being illustrated for simplicity but more, such as four or eight such planes, may instead be used.
  • the memory cell array of the chip 15 may not be divided into planes.
  • each plane has its own column control circuits 45 and 47 that are operable independently of each other.
  • the circuits 45 and 47 receive addresses of their respective memory cell array from the address portion 19 of the system bus 13, and decode them to address a specific one or more of respective bit lines 49 and 51.
  • the word lines 53 are addressed through row control circuits 55 in response to addresses received on the address bus 19.
  • Source voltage control circuits 57 and 59 are also connected with the respective planes, as are p-well voltage control circuits 61 and 63. If the memory chip 15 has a single array of memory cells, and if two or more such chips exist in the system, the array of each chip may be operated similarly to a plane or sub-array within the multi-plane chip described above.
  • Data are transferred into and out of the planes 41 and 43 through respective data input/output circuits 65 and 67 that are connected with the data portion 17 of the system bus 13.
  • the circuits 65 and 67 provide for both programming data into the memory cells and for reading data from the memory cells of their respective planes, through lines 69 and 71 connected to the planes through respective column control circuits 45 and 47.
  • controller 11 controls the operation of the memory chip
  • each memory chip also contains some controlling circuitry that executes commands from the controller 11 to perform such functions.
  • Interface circuits 73 are connected to the control and status portion 21 of the system bus 13. Commands from the controller are provided to a state machine 75 that then provides specific control of other circuits in order to execute these commands.
  • Control lines 77 — 81 connect the state machine 75 with these other circuits as shown in Figure 2. Status information from the state machine 75 is communicated over lines 83 to the interface 73 for transmission to the controller 11 over the bus portion 21.
  • a NAND architecture of the memory cell arrays 41 and 43 is currently preferred, although other architectures, such as NOR, can also be used instead.
  • Examples of NAND flash memories and their operation as part of a memory system may be had by reference to United States patents nos. 5,570,315, 5,774,397, 6,046,935, 6,373,746, 6,456,528, 6,522,580, 6,771,536 and 6,781,877 and United States Patent Application Publication No. 2003/0147278.
  • a large number of global bit lines are provided, only four such lines 91 - 94 being shown in Figure 2 for simplicity of explanation.
  • a number of series connected memory cell strings 97 — 104 are connected between one of these bit lines and a reference potential.
  • a plurality of charge storage memory cells 107 - 110 are connected in series with select transistors 1 1 1 and 1 12 at either end of the string.
  • select transistors of a string are rendered conductive, the string is connected between its bit line and the reference potential.
  • One memory cell within that string is then programmed or read at a time.
  • Word lines 115 - 118 of Figure 3 individually extend across the charge storage element of one memory cell in each of a number of strings of memory cells, and gates 119 and 120 control the states of the select transistors at each end of the strings.
  • the memory cell strings that share common word and control gate lines 1 15 - 120 are made to form a block 123 of memory cells that are erased together. This block of cells contains the minimum number of cells that are physically erasable at one time.
  • One row of memory cells, those along one of the word lines 115 - 118, are programmed at a time.
  • the rows of a MAND array are programmed in a prescribed order, in this case beginning with the row along the word line 118 closest to the end of the strings connected to ground or another common potential.
  • the row of memory cells along the word line 117 is programmed next, and so on, throughout the block 123.
  • the row along the word line 115 is programmed last.
  • a second block 125 is similar, its strings of memory cells being connected to the same global bit lines as the strings in the first block 123 but having a different set of word and control gate lines.
  • the word and control gate lines are driven to their proper operating voltages by the row control circuits 55. If there is more than one plane or sub-array in the system, such as planes 1 and 2 of Figure 2, one memory architecture uses common word lines extending between them. There can alternatively be more than two planes or sub-arrays that share common word lines. In other memory architectures, the word lines of individual planes or sub-arrays are separately driven.
  • the memory system may be operated to store more than two detectable levels of charge in each charge storage element or region, thereby to store more than one bit of data in each.
  • the charge storage elements of the memory cells are most commonly conductive floating gates but may alternatively be non- conductive dielectric charge trapping material, as described in United States Patent Application Publication No. 2003/0109093.
  • FIG 4 conceptually illustrates an organization of the flash memory cell array 7 (Figure 1) that is used as an example in further descriptions below.
  • Four planes or sub-arrays 131 - 134 of memory cells may be on a single integrated memory cell chip, on two chips (two of the planes on each chip) or on four separate chips. The specific arrangement is not important to the discussion below. Of course, other numbers of planes, such as 1, 2, 8, 16 or more may exist in a system.
  • the planes are individually divided into blocks of memory cells shown in Figure 4 by rectangles, such as blocks 137, 138, 139 and 140, located in respective planes 131 — 134. There can be dozens or hundreds of blocks in each plane.
  • the block of memory cells is the unit of erase, the smallest number of memory cells that are physically erasable together.
  • the blocks are operated in larger metablock units.
  • One block from each plane is logically linked together to form a metablock.
  • the four blocks 137 — 140 are shown to form one metablock 141.
  • AU of the cells within a metablock are typically erased together.
  • the blocks used to form a metablock need not be restricted to the same relative locations within their respective planes, as is shown in a second metablock 143 made up of blocks 145 - 148.
  • the memory system can be operated with the ability to dynamically form metablocks of any or all of one, two or three blocks in different planes. This allows the size of the metablock to be more closely matched with the amount of data available for storage in one programming operation.
  • the individual blocks are in turn divided for operational purposes into pages of memory cells, as illustrated in Figure 5.
  • the memory cells of each of the blocks 131 — 134 are each divided into eight pages PO — P7. Alternatively, there may be 16, 32 or more pages of memory cells within each block.
  • the page is the unit of data programming and reading within a block, containing the minimum amount of data that are programmed at one time.
  • a page is formed of memory cells along a word line within a block.
  • such pages within two or more blocks may be logically linked into metapages.
  • a metapage 151 is illustrated in Figure 5, being formed of one physical page from each of the four blocks 131 - 134.
  • the metapage 151 for example, includes the page P2 in of each of the four blocks but the pages of a metapage need not necessarily have the same relative position within each of the blocks.
  • the memory system can also be operated to form metapages of any or all of one, two or three pages in separate blocks in different planes. This allows the programming and reading operations to adaptively match the amount of data that may be conveniently handled in parallel and reduces the occasions when part of a metapage remains unprogrammed with data.
  • a metapage formed of physical pages of multiple planes contains memory cells along word line rows of those multiple planes. Rather than programming all of the cells in one word line row at the same time, they are more commonly alternately programmed in two or more interleaved groups, each group storing a page of data (in a single block) or a metapage of data (across multiple blocks).
  • a unit of peripheral circuits including data registers and a sense amplifier need not be provided for each bit line but rather are time-shared between adjacent bit lines. This economizes on the amount of substrate space required for the peripheral circuits and allows the memory cells to be packed with an increased density along the rows. Otherwise, it is preferable to simultaneously program every cell along a row in order to maximize the parallelism available from a given memory system.
  • the simultaneous programming of data into every other memory cell along a row is most conveniently accomplished by providing two rows of select transistors (not shown) along at least one end of the NAND strings, instead of the single row that is shown.
  • the select transistors of one row then connect every other string within a block to their respective bit lines in response to one control signal, and the select transistors of the other row connect intervening every other string to their respective bit lines in response to another control signal. Two pages of data are therefore written into each row of memory cells.
  • the amount of data in each logical page is typically an integer number of one or more sectors of data, each sector containing 512 bytes of data, by convention.
  • Figure 6 shows a logical data page of two sectors 153 and 155 of data of a page or metapage.
  • Each sector usually contains a portion 157 of 512 bytes of user or system data being stored and another number of bytes 159 for overhead data related either to the data in the portion 157 or to the physical page or block in which it is stored.
  • the number of bytes of overhead data is typically 16 bytes, making the total 528 bytes for each of the sectors 153 and 155.
  • the overhead portion 159 may contain an ECC calculated from the data portion 157 during programming, its logical address, an experience count of the number of times the block has been erased and re- programmed, one or more control flags, operating voltage levels, and/or the like, plus an ECC calculated from such overhead data 159.
  • the overhead data 159, or a portion of it, may be stored in different pages in other blocks.
  • FIG. 7 illustrates the most common interface between a host and such a mass memory system.
  • the host deals with data files generated or used by application software or firmware programs executed by the host.
  • a word processing data file is an example, and a drawing file of computer aided design (CAD) software is another, found mainly in general computer hosts such as PCs, laptop computers and the like.
  • CAD computer aided design
  • a document in the pdf format is also such a file.
  • a still digital video camera generates a data file for each picture that is stored on a memory card.
  • a cellular telephone utilizes data from files on an internal memory card, such as a telephone directory.
  • a PDA stores and uses several different files, such as an address file, a calendar file, and the like.
  • the memory card may also contain software that operates the host.
  • Memory systems especially memory systems embodied in removable cards, may communicate with different hosts via a standard interface. Different hosts may use different interfaces for communication with memory systems. Two categories of interfaces are those using a logical addressing system with a common logical address space and those using a file based addressing system.
  • a common logical interface between the host and the memory system is illustrated in Figure 7.
  • a continuous logical address space 161 is large enough to provide addresses for all the data that may be stored in the memory system.
  • the host address space is typically divided into increments of clusters of data. Each cluster may be designed in a given host system to contain a number of sectors of data, somewhere between 4 and 64 sectors being typical.
  • a standard sector contains 512 bytes of data and some overhead data.
  • Files 1, 2 and 3 are shown in the example of Figure 7 to have been created.
  • An application program running on the host system creates each file as an ordered set of data and identifies it by a unique name or other reference. Enough available logical address space not already allocated to other files is assigned by the host to File 1.
  • File 1 is shown to have been assigned a contiguous range of available logical addresses. Ranges of addresses are also commonly allocated for specific purposes, such as a particular range for the host operating software, which are then avoided for storing data even if these addresses have not been utilized at the time the host is assigning logical addresses to the data.
  • the Directory and FAT are typically stored in the non-volatile memory, as well as in a host memory, and are frequently updated by the host as new files are stored, other files deleted, files modified and the like.
  • the host may deallocate the logical addresses previously allocated to the deleted file by updating the Directory and FAT table to show that they are now available for use with other data files.
  • only the directory is updated when a file is deleted and FAT entries remain for obsolete clusters of data.
  • a logical address used in the FAT may be referred to as a Logical Block Address (LBA), so an interface using such logical addressing over a logical address space that is commonly used for data from different files may be referred to as an LBA interface.
  • LBA Logical Block Address
  • the host is not concerned about the physical locations where the memory system controller chooses to store the files.
  • the typical host only knows its logical address space and the logical addresses that it has allocated to its various files.
  • the memory system through a typical host/card interface, only knows the portions of the logical address space to which data have been written but does not know the logical addresses allocated to specific host files, or even the number of host files.
  • the memory system controller converts the logical addresses provided by the host for the storage or retrieval of data into unique physical addresses within the flash memory cell array where host data are stored.
  • a block 163 represents a working table of these logical-to-physical address conversions, which is maintained by the memory system controller.
  • the memory system controller is programmed to store data files within the blocks and metablocks of a memory array 165 in a manner to maintain the performance of the system at a high level.
  • Four planes or sub-arrays are used in this illustration. Data are preferably programmed and read with the maximum degree of parallelism that the system allows, across an entire metablock formed of a block from each of the planes.
  • At least one metablock 167 is usually allocated as a reserved block for storing operating firmware and data used by the memory controller.
  • Another metablock 169, or multiple metablocks may be allocated for storage of host operating software, the host FAT table and the like. Most of the physical storage space remains for the storage of data files.
  • the memory controller does not generally know, however, how the data received have been allocated by the host among its various file objects. All the memory controller typically knows from interacting with the host is that data written by the host to specific logical addresses are stored in corresponding physical addresses as maintained by the controller's logical-to-physical address table 163.
  • a few extra blocks of storage capacity are provided than are necessary to store the amount of data within the address space 161.
  • One or more of these extra blocks may be provided as redundant blocks for substitution for other blocks that may become defective during the lifetime of the memory.
  • the logical grouping of blocks contained within individual metablocks may usually be changed for various reasons, including the substitution of a redundant block for a defective block originally assigned to the metablock.
  • One or more additional blocks, such as metablock 171 are typically maintained in an erased block pool.
  • the controller converts the logical addresses assigned by the host to physical addresses within a metablock in the erased block pool.
  • Other metablocks not being used to store data within the logical address space 161 are then erased and designated as erased pool blocks for use during a subsequent data write operation.
  • Data compaction typically involves reading all valid data metapages from a metablock and writing them to a new metablock, ignoring metapages with invalid data in the process.
  • the metapages with valid data are also preferably arranged with a physical address order that matches the logical address order of the data stored in them.
  • the number of metapages occupied in the new metablock will be less than those occupied in the old metablock since the metapages containing invalid data are not copied to the new metablock.
  • the old block is then erased and made available to store new data.
  • the additional metapages of capacity gained by the consolidation can then be used to store other data.
  • metapages of valid data with contiguous or near contiguous logical addresses are gathered from two or more metablocks and rewritten into another metablock, usually one in the erased block pool. When all valid data metapages are copied from the original two or more metablocks, they may be erased for future use.
  • Data consolidation and garbage collection take time and can affect the performance of the memory system, particularly if data consolidation or garbage collection needs to take place before a command from the host can be executed.
  • Such operations are normally scheduled by the memory system controller to take place in the background as much as possible but the need to perform these operations can cause the controller to have to give the host a busy status indicator until such an operation is completed.
  • An example of where execution of a host command can be delayed is where there are not enough pre-erased metablocks in the erased block pool to store all the data that the host wants to write into the memory and data consolidation or garbage collection is needed first to clear one or more metablocks of valid data, which can then be erased. Attention has therefore been directed to managing control of the memory in order to minimize such disruptions.
  • One challenge to efficiently control operation of memory arrays with very large erase blocks is to match and align the number of data sectors being stored during a given write operation with the capacity and boundaries of blocks of memory.
  • One approach is to configure a metablock used to store new data from the host with less than a maximum number of blocks, as necessary to store a quantity of data less than an amount that fills an entire metablock.
  • the use of adaptive metablocks is described in United States Patent Application JNo. 10/749,189, filed December 30, 2003, entitled “Adaptive Metablocks.”
  • the fitting of boundaries between blocks of data and physical boundaries between metablocks is described in patent applications Serial No. 10/841,118, filed May 7, 2004, and Serial No. 11/016,271, filed December 16, 2004, entitled “Data Run Programming.”
  • the memory controller may also use data from the FAT table, which is stored by the host in the non-volatile memory, to more efficiently operate the memory system.
  • One such use is to learn when data has been identified by the host to be obsolete by deallocating their logical addresses. Knowing this allows the memory controller to schedule erasure of the blocks containing such invalid data before it would normally learn of it by the host writing new data to those logical addresses. This is described in United States Patent Application Serial No.
  • An alternative interface between a host and memory system for the storage of mass amounts of data eliminates use of the logical address space.
  • the host instead logically addresses each file by a unique f ⁇ leTD (or other unique reference) and offset addresses of units of data (such as bytes) within the file.
  • This file address is given directly to the memory system controller, which then keeps its own table of where the data of each host file are physically stored.
  • This new interface can be implemented with the same memory system as described above with respect to Figures 2 — 6.
  • the primary difference with what is described above is the manner in which that memory system communicates with a host system.
  • This file-based interface is illustrated in Figure 8, which should be compared with the logical address interface of Figure 7.
  • An identification of each of the Files 1 , 2 and 3 and offsets of data within the files of Figure 8 are passed directly to the memory controller.
  • This logical address information is then translated by a memory controller function 173 into physical addresses of metablocks and metapages of the memory 165.
  • the memory system knows the locations of data making up each file, these data may be erased soon after a host deletes the file. This is not generally the case for a typical logical address interface. Further, by identifying host data by file objects instead of using logical addresses, the memory system controller can store the data in a manner that reduces the need for frequent data consolidation and collection. The frequency of data copy operations and the amount of data copied are thus significantly reduced, thereby increasing the data programming and reading performance of the memory system.
  • Examples of file-based interfaces include those using direct data file storage.
  • Direct data file storage memory systems are described in pending United States patent applications, Serial Nos. 11/060,174, 11/060,248 and 11/060,249, all filed on February 16, 2005 naming either Alan W. Sinclair alone or with Peter J. Smith, and Provisional Application No. 60/705,388 filed by Alan W. Sinclair and Barry Wright, and entitled “Direct Data File Storage in Flash Memories” (hereinafter collectively referenced as the "Direct Data File Storage Applications”).
  • the entire logical address space 161 is preferably divided into these logical files, so the number of logical files depends upon the size of the logical address space and of the individual logical files.
  • Each of the logical files contains data of a group of contiguous logical addresses across the space 161.
  • the amount of data within each of the logical files is preferably made to be the same, and that amount equal to the data storage capacity of one metablock in the memory 165.
  • Unequal sizes of the logical files and/or sizes different from the storage capacity of a block or metablock of the memory are certainly possible but not preferred.
  • Data within each of the individual files a — j are represented by logical offset addresses within the files.
  • the file identifier and data offsets of the logical files are converted at 173 into physical addresses within the memory 165.
  • the logical files a - j are stored directly in the memory 165 by the same processes and protocols described in the Direct Data File Storage Applications. The process is the same as that used to store data files 1 - 3 of Figure 9 in the memory 165, except that the known amount of data in each logical file can make this easier, especially if that amount is equal to the capacity of a block or metablock of the memory. It is shown in Figure 9 that each of the logical files a — j is mapped to a different one of the metablocks of the memory 165.
  • Tt is also desirable that the file based data storage interact with the host in the same or an equivalent manner as present logical address memory systems with which the host has been designed to interface.
  • mapping individual logical files into corresponding individual memory metablocks essentially the same performance and timing characteristics are achieved with the direct data file interface memory system as when a logical address space interface is used.
  • the data file based backend storage system of Figure 9 designed to work through a traditional logical address space interface with a host, can also have a direct data file interface added. Both host data files from the file interface and logical files converted by from the logical interface are translated into memory metablock addresses. The data are then stored in those addresses of the memory by executing a direct data file protocol.
  • This protocol includes the direct data file storage techniques of the Direct Data File Storage Applications previously listed.
  • a memory system accept logically addressed data from a host and store it in a manner that keeps data from a single host file together in one or more blocks that do not contain data from many or any other files. In this way, some of the advantages of file-based storage may be realized even with a host that sends data in the form of sectors having logical addresses from a logical address space that is common to all files.
  • a host sends information regarding a sector of data to a memory system prior to sending the sector of data.
  • This information may be used by the memory system to store the sector with other sectors of the same file. Tn this way, sectors from the same file are kept together in particular blocks that may be dedicated to storing only that file (though some blocks may store data from more than one file).
  • the information sent by the host may be in the form of FAT and directory sectors that give allocation information on the sectors that are about to be sent. This is in reverse order to the usual sequence where a host sends sectors of data and subsequently sends allocation information in the form of FAT and directory sectors. Also, in prior systems, the memory system does not generally use the contents of FAT and directory sectors to modify its operations.
  • One aim of a logically-addressed file storage scheme is to accept logically fragmented data from a host and store the file in a physical arrangement that is less fragmented than the logical arrangement.
  • a file that is mapped to two or more portions of logical address space that arc not contiguous (there arc other logical addresses between the two portions) is stored contiguously in the physical memory array.
  • Storing the file in a physically contiguous manner may mean that all the data of a file is stored in a single block, or when the data in the file exceeds the capacity of a block, one or more blocks are occupied exclusively by data from the file and only one block contains data from the file and other data that are not from the file.
  • the blocks that store data from the file need not be in any particular arrangement.
  • "contiguous" in this context does not mean that the blocks containing the file are located together but refers to the arrangement of data within individual blocks.
  • Figure 10 shows a logically-addressed file storage scheme according to an embodiment of the present invention.
  • File 1, file 2 and file 3 are sent by a host for storage in memory array 180.
  • File-to-logical address conversion 160 is performed by the host in a similar manner to that shown in Figure 7 so that files 1, 2 and 3 are mapped to a common logical address space 161.
  • Files may become logically fragmented by this mapping as shown by data file 2 which occupies two portions of logical address space 161 that are separated by an intermediate portion that is not occupied by data of file 2.
  • data file 3 is split into two portions.
  • files may become much more fragmented with files occupying many separated portions of logical address space.
  • File-to-logical address conversion information 182 is generated when data files 1, 2 and 3 are mapped to logical address space by file-to-logical address conversion 160. File-to-logical address conversion information 182 is passed to the memory. However, unlike many prior systems, in this case file-to-logical conversion information 182 is sent to the memory before the data that it refers to. Thus, information reflecting the mapping of file 2 to two different logical address ranges of logical address space 161 is sent to the memory before the sectors of data of those logical address ranges are sent. File-to-logical address conversion information 182 allows logical-to physical address translation 184 to be done in a way that uses file-to-logical address conversion information 182 to determine the physical locations where individual sectors arc stored.
  • Figure 10 shows metablock 167 allocated as a reserved block; metablock 169 allocated for storage of host operating software, the host FAT table and the like; and metablock 171 maintained in an erased block pool as before.
  • Figure 10 also shows File 1 stored in one metablock, File 2 in another metablock and File 3 occupying two other metablocks. Even though File 2 is mapped to two separate portions of logical address space 161, the two portions of File 2 are stored together as a result of the logical to physical address translation 184.
  • File 3 is logically fragmented into two parts occupying two portions of logical address space 161 that are separated from each other. Additional data that are not part of File 3 are mapped to the intervening portion of logical address space.
  • Figure 11 shows an example of File A that is mapped to logical address space 161 and is logically fragmented into four portions by this mapping.
  • File-to-logical address conversion information 182 regarding this mapping is sent to the memory before the data are sent to the memory.
  • the logical addresses to which portions of File A are mapped are identified with File A by file-to-logical address information 182.
  • Figure 11 shows the logical to physical translation 184 that takes place in the memory.
  • the portions of File A that are mapped to separated portions of logical address space 161 are mapped to contiguous portions of physical memory array 180.
  • metablock 4 is filled with data from File A and metablock 7 is partially filled with data from File A.
  • the data in metablock 7 may later be combined with data from other files so that space in the memory array is not wasted.
  • metablock 4 remains dedicated to storing only data from File A. Once File A is closed, the memory may consolidate the data in metablock 7 with other similar data from, other files.
  • a scheme for carrying out such consolidation of partial metablocks is given in the Direct Data File applications where residual file data from multiple files are combined in a single common block in an efficient manner.
  • FIG. 12 shows how file allocation information may be stored.
  • Files A and B are stored in a memory.
  • a directory contains entries for both file A and file B.
  • a directory entry contains various information about a file including the address of the first cluster of the file. Thus, for file A the directory entry indicates that cluster 2 is the first cluster, so the first FAT entry for file A is the entry for cluster 2. For file B, the directory entry indicates that the first cluster is cluster 0.
  • the FAT contains cluster entries that indicate the next cluster for that file. Thus, when the location of the first FAT entry for a file is obtained from the directory, subsequent FAT entries are indicated by the FAT entry for the previous cluster allocated to that file. FAT entries may be considered to be "chained" because of the way one FAT entry points to the location of the next FAT entry for a particular file.
  • cluster 2 is indicated by the directory as the first cluster.
  • the entry for cluster 2 indicates that cluster 3 is the next cluster for File A.
  • the entry for cluster 3 indicates that cluster 4 is the next cluster for File A.
  • the entry for cluster 4 indicates an End of File (EoF).
  • cluster 4 is the last cluster allocated to File A.
  • the directory indicates that cluster 0 is the first cluster.
  • the entry for cluster 0 indicates that cluster 1 is the next cluster for File B.
  • the entry for cluster 1 indicates that cluster 5 is the next cluster for File B.
  • the entry for cluster 5 indicates that cluster 6 is the next cluster for File B and the entry for cluster 6 indicates an End of File.
  • cluster 6 is the last cluster of File B.
  • FAT and directory information is generally maintained by a host and is stored in the nonvolatile memory on a regular basis by sending FAT sectors and directory sectors.
  • Previous schemes have used Directory and FAT structures to store file-to- logical address information. However, unlike previous schemes, a scheme according to an embodiment of the present invention sends filc-to-logical address information before the data are sent to the memory. In a typical prior system, FAT and directory sectors were only sent after the data to which they referred were sent and stored in the memory. One reason to delay sending FAT and directory sectors is to avoid having incorrect information recorded in nonvolatile memory in case of a loss of power before the data was written. Tn one embodiment, a scheme avoids this problem by only writing part of the FAT for a file prior to storing the file to which it refers. In this way, if a loss of power occurs the partial FAT indicates that writing the file was not completed and that the file data may not be usable.
  • Tn an exemplary notification scheme, FAT and directory sectors are sent by the host to inform the memory about the file allocation of sectors of data that are to be sent by the host. It is not generally necessary to send file allocation information for each cluster of host data sent. In general, where a host sends sequential clusters of sectors, the memory assumes that the clusters belong to the same file. Thus, where a single file is sent as a stream of sequential clusters, the host may just identify the file before the first cluster is sent and send an end of file indicator after the last sector.
  • Figure 13 shows an example of the host sending File A of Figure 12 to the memory. First, a directory sector 301 is sent indicating that cluster 2 is the first cluster of File A.
  • sectors of cluster 2 are sent and are stored by the memory in a new block 302 of the memory array because this is the start of a new host file.
  • sectors of clusters 3 and 4 are received sequentially and are stored in the same block with sectors of cluster 2.
  • the host sends a FAT sector 303 with an End of File entry for cluster 4 indicating that it is the last cluster in file A.
  • Full FAT information for file A may also be sent at this point because the whole of file A has been stored.
  • the memory can close file A and could perform reclaim operations if desired. This shows an example of a file that is sent in a logically sequential manner and without any intermediate writing to other files.
  • Figure 14 shows the example of a host sending File B of Figure 12.
  • a directory sector 410 is sent indicating that the first cluster of File B is cluster 0.
  • the sectors of cluster 0 are sent and stored in a new block 412 because these are the first sectors of a new file.
  • the sectors of cluster 1 are received and because these are sequential to the sectors of cluster 0, it is assumed that they are also from File B, so they arc also stored in block 412.
  • a FAT sector 414 is received that contains a FAT entry for cluster 1 and the pointer for this entry indicates that cluster 5 is the next cluster in file B.
  • FAT sector 414 may not contain an entry for cluster 5 at this point because cluster 5 has not yet been sent by the host.
  • FAT sector 414 informs the memory controller that although there is a jump in logical address from cluster 1 to cluster 5, the sectors of cluster 5 contain the next data from File B after cluster 1. Then, when the sectors of cluster 5 are received, they are stored with the sectors of cluster 1 in block 412. Then, cluster 6 is received and is also stored in block 412 because it is sequential to cluster 5. Subsequently, a FAT sector 416 is received that contains an End of File entry for cluster 6. File B can then be closed and reclaim operations can be performed if necessary on the block containing File B. In some cases, the memory may assume that when there is a jump in logical address that the host will continue writing the next cluster of the same file.
  • Figure 14 may be considered an example of a logically non-sequential writing of a file without intermediate writing to other files because, though there is a jump in logical address between sectors of cluster 1 and sectors of cluster 5, the host sends File B over a time period that is dedicated to sending File B (i.e. no sectors of data from other files are sent in this time).
  • Figure 15A shows two files C and D mapped by a host to part of a logical address space. In this case, two files C and D are not only fragmented in logical address space but are also sent in a temporally fragmented manner.
  • the clusters of files C and D are sent by the host in logical order so that cluster 10 is sent first, then cluster 11, then cluster 12 and so on. This involves some changes from one file to another even though the clusters are sent in logically sequential order. The memory is informed of these changes between files by the host.
  • Figure 15B shows how the host informs the memory when the host starts writing to a different file.
  • a directory sector 520 is sent indicating that cluster 10 is the first cluster of file C.
  • the sectors of cluster 10 are sent by the host and are stored in the memory array in a new block 522 because they are the first sectors of a new file.
  • the host sends another directory sector 524 indicating that cluster 11 is the first cluster of file D.
  • cluster 11 is send and is stored in another new block 526.
  • cluster 12 is received and is stored with cluster 11 in block 526.
  • the memory system assumes that, because cluster 12 is sequential to cluster 11 and the host has not indicated otherwise, that cluster 12 belongs to the same file as cluster 11.
  • a FAT sector is sent by the host with an entry for cluster 10.
  • the entry for cluster 10 includes a pointer to the next cluster for the file of cluster 10 (file C). Tn this case the pointer indicates that the next cluster of file C is cluster 13. Then, when cluster 13 is received, even though it is logically sequential to the last cluster received (cluster 12) the memory system knows that cluster 13 is allocated to file C and so the sectors of cluster 13 are stored in block 522 with the sectors of cluster 10.
  • the host may send an indication that a cluster is the last cluster of a particular file by a FAT sector including an End of File entry for the cluster. This allows the file to be closed and allows the memory system to carry out reclaim operations on the blocks containing the file as described below.
  • the metablocks containing the file data are then marked as ready for reclaim operations.
  • the techniques used to reclaim memory space in a memory system using techniques of the present invention are similar to those described in the Direct Data File Storage applications.
  • a file is closed there may be one or more metablocks that are full of data from the file but there is usually one metablock that is only partially filled with data from the file.
  • the host may copy residual file data from one file to a metablock that contains residual file data from another file. Which residual file data arc moved and the destination to which they are moved are chosen to keep the amount of unused memory space small.
  • a metablock containing residual file data occupying 70% (or nearly 70%) of a metablock A metablock containing portions of data from more than one file may be considered a common block.
  • direct data file storage techniques may be combined with techniques of the present application, embodiments of the present invention generally use logical addresses to manage data within the memory array, not file identifiers as used in direct data file storage.
  • a memory system stores files in one or more dedicated metablocks and one common block in the memory array so that when the file is no longer needed by the host, the dedicated metablocks may be erased immediately for reuse and the common block may be scheduled for garbage collection.
  • Directory and FAT information sent by the host generally indicates when the host has deleted a file by removing the Directory entry for that file. In some cases, FAT entries may reflect this deletion.
  • a memory system may determine from the directory that a file has been deleted by the host and therefore, any metablock containing only data from that file may be erased. Such a metablock may be added to a queue of metablocks to be erased at this point as part of ongoing reclaim operations.
  • a common block containing data from the file may be added to a queue of metablocks to be garbage collected so that the space occupied by obsolete data can be reclaimed.
  • reclaim operations may be scheduled in an efficient manner. Examples of such scheduling are given in US Patent Application No. 11/259,423, entitled “Scheduling of reclaim operations in non-volatile memory,” filed on October 25, 2005.
  • One advantage of a notification scheme based on FAT and directory sectors is that it uses signals that are already in general use in an LBA interface.
  • the FAT and directory sectors are sent at different times compared with many prior systems, but they contain valid information and are generally compatible with prior LBA interfaces.
  • a host using a notification scheme according to an embodiment of the present invention would be compatible with a memory system that did not use such a notification scheme.
  • Such a memory system would store the FAT and directory sectors without using them to determine where sectors of host data were stored.
  • FAT sectors stored in this way are valid because they contain entries for clusters of data that have already been stored.
  • the incomplete nature of the FAT information for a file may indicate that the memory system had not completed storing data for that file when power was lost.
  • FAT and directory control data
  • Sending two or more identical FAT sectors may indicate subsequent host behavior to a memory system.
  • a host may indicate to a memory system that the host does not require immediate access to the memory system and that power will be maintained. This may be indicated by sending duplicate FAT sectors in succession. Only one of these sectors may be written by the memory system, or both may be written.
  • the memory system determines that power will be maintained and the host does not require any immediate access, so the memory system may enter an idle state.
  • the memory system may perform housekeeping operations such as reclaim operations to garbage collect metablocks containing obsolete data and consolidate metablocks containing unwritten portions.
  • An idle state is terminated by receipt of another host command.
  • the memory system may indicate a busy status to the host while carrying out housekeeping operations in idle mode.
  • a busy status indicator informs the host that the memory system is carrying out housekeeping operations, but does not prevent the host from sending a command to terminate housekeeping operations and start executing the new command.
  • a host may indicate an imminent power-down by sending an identical FAT sector three times. The memory system may react to such a signal by entering a shut-down state.
  • the memory system indicates a busy status to the host until it has stored any data in nonvolatile memory that was not yet stored and performed any other operations to make it safe to power down.
  • the host waits until the memory system is no longer busy before removing power.
  • Other host behavior may also be indicated by a host by sending multiple identical FAT or directory sectors.
  • a host may also identify a particular file for deletion using repeated sectors of control information.
  • When a memory system receives an indication from a host that a particular file should be deleted the file is put in a queue for garbage collection.
  • a host may identify a particular file for erase using repeated sectors of control information.
  • the memory system puts the file in a queue for garbage collection and immediately proceeds to perform garbage collection to remove all the data of the file from the nonvolatile memory array.
  • a memory system determines that the host does not provide notification signals and then stores data in a manner that does not require such signals.
  • the memory system may make this determination when it first receives communication from a host. For example if the memory system receives sectors of data to be written without any prior FAT or directory sectors, then the memory may determine that the host is not enabled for such signals and may select a data storage scheme that ignores the file allocation of sectors in choosing where to store them.
  • an "identify drive" command from a host allows a host to determine whether a memory system is capable of using notification signals.
  • a default data storage scheme for use by a memory system connected to a host that does not support notification signals may store data as shown in Figure 7 without regard to the file allocation of a particular sector. Examples of such storage schemes are provided in US Patent Applications No. 10/750,155, filed on December 30, 2003; Nos. 10/917,888; 10/917,867; 10/917,889 and 10/917,725, filed on August 13, 2004.
  • a notification scheme may not be limited to communication according to an existing interface.
  • Additional commands may be defined for providing allocation information from a host to a memory system. Hosts and cards using such additional commands generally require a hand-shaking routing when first connected so that they can identify that the use of such additional commands is possible. In general, hosts and cards capable of using such additional commands will also be capable of operating without additional commands when connected to a host or card that does not have the capability to use the additional commands. Thus, backward compatibility is maintained for memory systems and hosts using any such new commands. Additional commands may also be provided that are not related to conveying file allocation information. For example, an explicit command may be defined for a host to erase or delete a particular file.

Abstract

L'invention concerne des fichiers qui sont corrélés à une plage d'adresses logiques par un hôte, devenant logiquement fragmentés avant d'être envoyés à un système de mémoire. Ultérieurement, les parties fragmentées logiquement sont assemblées de nouveau lorsqu'elles sont stockées en blocs dans le système de mémoire. L'hôte fournit des informations au système de mémoire concernant une corrélation de données de fichier vers adresse logique avant l'envoi des données. La mémoire sélectionne des emplacements de stockage pour les données sur la base des fichiers auxquels les données appartiennent.
EP06848548A 2005-12-13 2006-12-07 Stockage de fichier adresse logiquement Ceased EP1960863A2 (fr)

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US11/300,568 US20070136553A1 (en) 2005-12-13 2005-12-13 Logically-addressed file storage systems
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TWI385520B (zh) * 2008-02-29 2013-02-11 Via Tech Inc 儲存單元管理方法及系統
JP2009211234A (ja) * 2008-03-01 2009-09-17 Toshiba Corp メモリシステム
TWI492050B (zh) * 2010-04-12 2015-07-11 Phison Electronics Corp 儲存裝置、記憶體控制器及資料保護方法
US9727570B2 (en) * 2011-06-03 2017-08-08 Apple Inc. Mount-time unmapping of unused logical addresses in non-volatile memory systems
TWI489272B (zh) 2012-04-03 2015-06-21 Phison Electronics Corp 保護資料的方法、記憶體控制器與記憶體儲存裝置
CN103377149B (zh) * 2012-04-16 2016-05-11 群联电子股份有限公司 保护数据的方法、存储器控制器与存储器储存装置
KR101993704B1 (ko) 2012-08-24 2019-06-27 삼성전자주식회사 플래시 메모리를 기반으로 하는 저장 장치 및 플래시 메모리를 제어하는 메모리 컨트롤러의 쓰기 메모리 블록 할당 방법
US9952769B2 (en) * 2015-09-14 2018-04-24 Microsoft Technology Licensing, Llc. Data storage system with data storage devices operative to manage storage device functions specific to a particular data storage device
US10430085B2 (en) 2016-11-08 2019-10-01 Micron Technology, Inc. Memory operations on data
US10261876B2 (en) * 2016-11-08 2019-04-16 Micron Technology, Inc. Memory management

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1069420A (ja) * 1996-08-29 1998-03-10 Sony Corp 情報記録装置、情報記録再生装置、情報記録方法および情報再生方法
TWI246064B (en) * 2002-07-29 2005-12-21 Milsys Ltd Data storage and processing device, electronic appliance, electronic system and method of operating an appliance that responds to a plurality of commands
WO2005103903A1 (fr) * 2004-04-20 2005-11-03 Matsushita Electric Industrial Co., Ltd. Systeme de stockage non volatile

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2007070763A3 *

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