EP1958067A2 - Systeme de controleur numerique a memoire flash a base de microcontroleur - Google Patents

Systeme de controleur numerique a memoire flash a base de microcontroleur

Info

Publication number
EP1958067A2
EP1958067A2 EP06838496A EP06838496A EP1958067A2 EP 1958067 A2 EP1958067 A2 EP 1958067A2 EP 06838496 A EP06838496 A EP 06838496A EP 06838496 A EP06838496 A EP 06838496A EP 1958067 A2 EP1958067 A2 EP 1958067A2
Authority
EP
European Patent Office
Prior art keywords
command
module
microcontroller
flash memory
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06838496A
Other languages
German (de)
English (en)
Inventor
Daniel Scott Cohen
Matthew Todd Wich
Jason Joseph Ziomek
Rocendo Bracamontes
Shude Lu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of EP1958067A2 publication Critical patent/EP1958067A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G06F2212/2022—Flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G11C29/16—Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines

Definitions

  • the present invention relates to Flash memory digital controller systems, and more particularly to microcontroller based flash memory digital controller systems.
  • the improved digital controller system should be based on a standard microcontroller coupled to a separate command decoder and burst read controller.
  • the present invention addresses such a need.
  • a digital control system including a microcontroller for handling timed events, a command decoder for interpreting user commands, a separate burst controller for handling burst reads of the Flash memory, a program buffer for handling page writes to the Flash memory, a page transfer controller for handling data transfers from the Flash core to the program buffer as well as address control for page writes from the program buffer to the Flash memory, a memory control register block for storing and adjusting memory control and memory test mode signals, a memory plane interface for multiplexing addresses into the Flash memory and accelerating program, erase, and recovery verification, and an I/O Mux module for multiplexing data out of the system, and a general purpose I/O port (GPIO) that can be read and written by the microcontroller for use in test and debug.
  • GPIO general purpose I/O port
  • Figure 1 illustrates a preferred embodiment of a digital controller system in accordance with the present invention.
  • Figure 2 illustrates in more detail the preferred embodiment of the digital controller system in accordance with the present invention.
  • the present invention provides a microcontroller based digital controller system.
  • the following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements.
  • Various modifications to the preferred embodiment will be readily apparent to those skilled in the art and the generic principles herein may be applied to other embodiments.
  • the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.
  • FIG. 1 illustrates a preferred embodiment of a digital controller system in accordance with the present invention.
  • Figure 2 illustrates in more detail the preferred embodiment of the digital controller system in accordance with the present invention.
  • the digital controller system 100 comprises a microcontroller 107. Separately from the microprocessor 107, the digital controller system 100 comprises a page transfer module 101, a program buffer module 102, a memory plane interface 103, a burst read module 104, a input/output (I/O) multiplexer (MUX) module 105, a command decoder 106, and a register module 108, the functions of which are further described below.
  • I/O input/output
  • the non-volatile Flash memory module can be embedded in or external to the digital controller system 100.
  • the digital controller system 100 is built around a standard microcontroller system 107, but having additional "intelligence" built into the command decoder 106.
  • the command decoder 106 serves to provide a means for detecting and managing user commands and waking up the microcontroller 107 when the command requires a complex "timed" command.
  • the burst read module 104 provides a means of detecting a burst read request and responding accordingly.
  • a "timed" command is a command which cannot be executed in one cycle, but rather requires a series of events to occur in order for the command to be fully executed.
  • timed events include programming and erasing the Flash memory, setting or clearing non-volatile lock bits, page transfers from the Flash memory to the program buffer, and various test mode and extended commands.
  • the use of a standard microcontroller 107 to handle timed events provide flexibility that is not offered by hardwired state machines. If the algorithm for interfacing to the Flash memory module needs to be tweaked, it can be done more readily by a simple mask change to the ROM that stores the microcontroller's firmware.
  • the command decoder 106 serves as a user interface, allowing commands to be received and managed independently of the microcontroller 107.
  • the command decoder 106 serves as a "traffic cop" for the digital controller system 100 and acts on legal commands and ignores illegal ones. When a command is acted on, it is either done so solely by the command decoder 106 or by waking up the microcontroller 107.
  • An example of a command not requiring the use of the microcontroller 107 is a read command, or write to the burst control register, or soft/hard lock registers.
  • An example of a command requiring the use of the microcontroller 107 is a program or erase, or any other timed command.
  • the microcontroller 107 can be turned off or put to sleep when there is no timed event underway. This saves power which is vital in low power battery operated systems.
  • the microcontroller 107 need not be concerned with new commands, command prioritization, or management while it is working on a command. This provides code efficiency and allows for quicker processing of timed events which is crucial for quick programming and erasing of the Flash memory, a key metric of competitiveness.
  • the command clock is decoupled from the microcontroller clock, allowing the microcontroller 107 to run at a set speed asynchronously to the clock of the system 100 where the digital controller/Flash module will be used. This also allows quick responses to user commands even where multi-cycle timed events will occur.
  • the ready signal can be dropped instantly by the command decoder 106 despite the fact that it could take some time for the microcontroller 107 to recognize the command.
  • the microcontroller 107 serves as a test interface to the digital controller system 100 that provides for:
  • the burst read module 104 contains a state machine for interpreting burst read commands, and counters for addressing the Flash memory, which serves to provide hardware acceleration for the burst read function. This is critical since the burst read function must operate at a significantly higher speed than normal asynchronous reads.
  • the burst read module 104 also controls the initial access time of the burst read data by controlling the initial latency between the latching of the starting address and the raising of the data valid signal. This functionality creates a general purpose microprocessor interface to the Flash memory, preventing the microcontroller 107 from having to become involved in the read operation.
  • the burst read module 104 also prevents the burst address from entering a busy plane in the Flash memory by looking at a stop/busy signal and allowing the address counter to finish counting through the current 64-bits of data before stopping.
  • the external interface to the user contains a 16-bit data word, however, to support high burst speeds, 64-bits are read at a time. While the four 16-bit words are being multiplexed out, the next 64 bits are being read. This eliminates the read latency after the initial latency and allows the burst function to operate at a higher data rate.
  • the burst read module 104 also provides the burst enable signal and address to the memory plane interface 103, which in turn handles the multiplexing of the address into the Flash memory depending on the type of operation that is occurring. In the case of a burst read, the burst address will be multiplexed in.
  • the page transfer module 101 contains a counter for addressing the Flash memory and the program buffer module 102. This provides hardware acceleration of the page transfer function, where a page of data is copied from the Flash memory to the program buffer module 102.
  • the firmware can initiate a page transfer and then simply poll the "done” signal to know when the transfer has completed. This saves many cycles of firmware controlled address incrementation and data read/writes.
  • the program buffer module 102 pre-set function can be done quickly by setting a data register to a known value and then simply counting through the page address as the data register is written to all locations. This saves valuable code space and firmware developer effort.
  • the program buffer module 102 contains a one page (4 Kbit or 256 16-bit words) byte addressable SRAM that serves as a page buffer for programming into the Flash memory.
  • the program buffer module 102 has a logical size of 256 x 16 and is physically composed of two 256 x 8 bit SRAMs, making it possible to easily support byte addressing. It can be addressed by the user, by the command decoder 106, or by the firmware through the page transfer module's 101 address counter, allowing it to be read and written by both the user and the firmware. It also contains a status register that keeps track of which segment has been written to. In the preferred embodiment, there are 16 bits per word, 256 words per page and 32 words per segment. Therefore, there are 8 segments per page. The status register is 8 bits wide with each bit representing one of the 32 segments.
  • the memory plane interface 103 handles the multiplexing of address buses from different sources into the Flash memory module so that it can be accessed by the user (in the case of random reads), the burst read module 104 (in the case of burst reads), the firmware (for program and verify functions), and/or the page transfer module 101 (for copying data from the Flash memory to the program buffer) module 102.
  • Separating the memory interface into its own hierarchical unit makes it possible to have a clean address interface that is optimized for performance by prioritizing the burst address bus for high speed reads and by making it easier to minimize skew on the address buses, which is critical for low power operation of the asynchronous Flash memory.
  • the memory plane interface 103 contains novel circuitry that performs the following three functions that serve as hardware accelerators to the program and erase functions:
  • Program Okay Function As data is stored into the Flash memory, it is simultaneously read back out and compared to the data that is being programmed. If the data does not match, a new pattern is generated that contains O's only in the bit locations that need additional programming pulses. A bitwise AND of this pattern is assigned to a firmware readable register called "program_okay". If program_okay is LOW, then the new pattern must be programmed into the memory. If program_okay is HIGH, then no further programming is necessary.
  • Erase Okay Function A bitwise AND of the 64-bit data at the current address is stored in a firmware readable register called "erase_okay". Since an erased bit in the Flash memory is actually represented as a HIGH, this bit will indicate if all the bits in the 64 bit word are erased. A LOW value of erase_okay indicates to the firmware that additional erasing is necessary.
  • (a) don 't_recoverj54 register As noted previously, in the preferred embodiment, 64 bits (4 words) are read at a time. This allows the high speed burst read function to work. It should be noted that the 64 bit read is arbitrary and is only limited by the need for additional circuitry and power that would be required to read more bits at a time. When an erase is performed on a bit, it must be followed by a recover operation to ensure that the bit was not erased "too much”. All over-erased bits must be recovered (soft programmed).
  • the don 't_recover_64 register will be set by hardware.
  • a HIGH value indicates that no bits in the 64 bit slice are erased and therefore no recover (soft programming) is necessary.
  • a LOW value indicates that at least one bit in the slice is in the erased state and therefore recovery is necessary.
  • the firmware will then step through the addresses of the four 16-bit words that form this 64 bit slice and examine the don 'tjrecover register to narrow down where to actually do the recovery.
  • don 't_recover register is formed by examining the contents of a 64-bit slice, the don't_recover register is formed by just 16 bits. Because the smallest range of bits that can be recovered at a time is 16 bits, it is code and time efficient to further narrow down the 64 bit slice into 16-bit words and perform the recovery at this scope.
  • the register module 108 contains registers whose values are loaded during the firmware initialization routine and whose purpose is to control or tweak various trim settings on the Flash memory and its analog support components.
  • Various memory control signals are derived from individual bits or combination of bits in these registers. Some of these registers are for test while others are for normal operation. Examples include: enabling/disabling various steps during program and erase; trim values for various charge pumps used during read and program; oscillator frequency trim; and bandgap trim for controlling analog voltage regulation.
  • the register module 108 also contains some status registers or flags that are used by the firmware. These include the "error bit” that is set when a programming or erase error occurs, the suspend status register which indicates if an erase command has been suspended, and the "PORJu ⁇ it" register which indicates a Power On Reset has occurred.
  • the POR__init bit offers the advantage of allowing the firmware to make a decision as to whether the part is powering up in which case a full initialization is necessary, or whether the reset has occurred simply from a user initiated reset in which a significantly shorter initialization routine is used. This allows for faster boot up making a more competitive device.
  • the suspend status register offers advantages for the erase suspend and erase resume operations. Since an erase command involves many steps depending on the size of the data being erased, it is advantageous to keep track of how far along in the sequence the command has progressed so that if it is interrupted by a suspend command, the firmware can later know where to pick up again when the command is resumed.
  • the 8- bit suspend status register serves this purpose. As the firmware progresses through an erase command, it keeps track of each step in the SSR. When an erase resume command is issued, the firmware looks at the SSR to know what has already been done so that it needn't re-run completed steps. The POR_init and error bit registers are cleared by signals from the command decoder 106.
  • the I/O Mux module 105 accessible by the firmware, multiplexes data out of the system 100. It comprises a general purpose I/O (GPIO) 109 which provides advantages during debug and evaluation.
  • GPIO general purpose I/O
  • a four bit I/O is used due to size limitations on the die that didn't allow enough space for a full 8 bit I/O that would have matched the microcontroller's data bus.
  • firmware can output the first four bits of the bus and then the next four bits on a separate cycle.
  • the I/O is bidirectional and can be used by the firmware to read as well as write. Since the system 100 has a special instruction SRAM for running firmware out of RAM instead of ROM during debug and evaluation, the firmware can be modified as necessary during debug of firmware or hardware.
  • the GPIO 109 can be of immense help during this process.
  • the system comprises multiple subsystems including a microcontroller for handling timed events, a command decoder for interpreting user commands, a separate burst controller for handling burst reads of the Flash memory, a program buffer for handling page writes to the Flash memory, a page transfer controller for handling data transfers from the Flash core to the program buffer as well as address control for page writes from the program buffer to the Flash memory, a memory control register block for storing and adjusting memory control and memory test mode signals, a memory plane interface for multiplexing addresses into the Flash memory and accelerating program, erase, and recovery verification, and an I/O Mux module for multiplexing data out of the system, and a general purpose I/O port (GPIO) that can be read and written by the microcontroller for use in test and debug.
  • GPIO general purpose I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Microcomputers (AREA)
  • Debugging And Monitoring (AREA)
  • Stored Programmes (AREA)

Abstract

L'invention concerne un système de commande numérique comprenant un microcontrôleur pour manipuler des événements temporisés, un décodeur de commande pour interpréter des commandes utilisateur, un contrôleur de rafale séparé pour manipuler des lectures en rafale dans la mémoire flash, un tampon de programme pour manipuler des écritures de page dans la mémoire flash, un contrôleur de transfert de page pour manipuler des transferts de données du noyau flash au tampon de programme ainsi qu'une commande d'adresse pour des écritures sur page du tampon de programmes dans la mémoire flash, un bloc de registre de commande memoire pour stocker et régler une commande mémoire et des signaux en mode test mémoire, une interface mémoire plane pour multiplexer des adresses dans la mémoire flash memory et accélérer un programme, un effacement et une vérification de récupération, ainsi qu'un module multiplexeur d'E/S pour multiplexer des données hors du système, et un port d'E/S polyvalent (GPIO) auquel le microcontrôleur peut accéder en lecture et en écriture en vue d'une utilisation dans un test et un débogage.
EP06838496A 2005-11-28 2006-11-28 Systeme de controleur numerique a memoire flash a base de microcontroleur Withdrawn EP1958067A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/288,509 US7600090B2 (en) 2005-11-28 2005-11-28 Microcontroller based flash memory digital controller system
PCT/US2006/045564 WO2007062256A2 (fr) 2005-11-28 2006-11-28 Systeme de controleur numerique a memoire flash a base de microcontroleur

Publications (1)

Publication Number Publication Date
EP1958067A2 true EP1958067A2 (fr) 2008-08-20

Family

ID=38067979

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06838496A Withdrawn EP1958067A2 (fr) 2005-11-28 2006-11-28 Systeme de controleur numerique a memoire flash a base de microcontroleur

Country Status (6)

Country Link
US (2) US7600090B2 (fr)
EP (1) EP1958067A2 (fr)
JP (1) JP2009517741A (fr)
KR (1) KR20080077657A (fr)
TW (1) TW200822136A (fr)
WO (1) WO2007062256A2 (fr)

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Also Published As

Publication number Publication date
WO2007062256A3 (fr) 2009-05-07
KR20080077657A (ko) 2008-08-25
WO2007062256A2 (fr) 2007-05-31
JP2009517741A (ja) 2009-04-30
US20100017563A1 (en) 2010-01-21
US8316174B2 (en) 2012-11-20
US7600090B2 (en) 2009-10-06
TW200822136A (en) 2008-05-16
US20080040580A1 (en) 2008-02-14

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