EP1949354A2 - Controlling an energy recovery stage of a plasma screen - Google Patents

Controlling an energy recovery stage of a plasma screen

Info

Publication number
EP1949354A2
EP1949354A2 EP06831351A EP06831351A EP1949354A2 EP 1949354 A2 EP1949354 A2 EP 1949354A2 EP 06831351 A EP06831351 A EP 06831351A EP 06831351 A EP06831351 A EP 06831351A EP 1949354 A2 EP1949354 A2 EP 1949354A2
Authority
EP
European Patent Office
Prior art keywords
voltage
circuit
capacitive element
energy recovery
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06831351A
Other languages
German (de)
French (fr)
Inventor
Bertrand Rivet
Frédéric Gautier
Benoît Peron
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of EP1949354A2 publication Critical patent/EP1949354A2/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/16—Calculation or use of calculated indices related to luminance levels in display data

Definitions

  • the present invention generally relates to plasma screens which comprise two parallel plates each carrying electrode arrays and between which is present a gas from light discharges to regions of intersection between the electrodes of the different plates.
  • the present invention more particularly relates to the control of the electrode arrays of the screen in a so-called maintenance phase (sustain) in which the electrodes of each array are excited by an alternating voltage.
  • FIG. 1 represents, generally and very schematically, the structure of a plasma display panel (PDP) 1 of the type to which the present invention applies.
  • Two parallel plates designated by the overall reference 2 each carry electrodes generally perpendicular from one plate to another and parallel to each other on the same plate.
  • Each line L of the screen is defined by two electrodes 3 and 4 parallel to each other and each column C of the screen is defined by an electrode 5 in the other direction, carried by the other plate.
  • the intersection of a line L and a column C defines a pixel P of the screen. For lighting a pixel, a light discharge is organized between the electrodes 3 and 4 of a line L, addressed by the corresponding column 5.
  • the control of the screen 2 is performed by means of a column 6 for controlling the column electrodes (COL DRV) and control circuits 7 for a first network of electrodes (for example, 3) of line (SCAN RVD) say sweeping.
  • the circuit 7 is connected to a first power supply circuit 8 (PW CT).
  • the second electrode array (for example, 4) of so-called maintenance lines is directly connected to a power supply circuit 8 '(PW REF) (generally a reference potential).
  • the circuits 6, 7, 8 and 8 ' are controlled and synchronized by a unit 9 (CU) generally a computer or a wired logic circuit.
  • the present invention relates more particularly to a portion of the power supply circuits 8 and 8 '.
  • FIG. 2 very schematically shows in the form of blocks a typical example of circuit architecture 8 and 8 'associated with the control circuits of the scanning and maintenance electrodes of the type to which the present invention applies.
  • two lines 3 and 4 of the screen have been symbolized by their equivalent capacitance, the two electrodes of which are respectively connected to the scanning circuit 7 and to the energy supply circuit 8 '.
  • the control circuitry of each scanning electrode (contained in the block 7) are formed of dark switches ⁇ tionnant all or nothing to cause, on one of the electrodes of the line considered, different voltage levels at different phases of operation.
  • the various control signals have not been illustrated in the figures.
  • each scanning electrode is associated with several switches of the circuit 7 which serve to select those of the lines of the screen that will receive the different voltages. All the control circuits of the different electrodes have their respective power supply terminals interconnected to the common energy supply circuit 8.
  • the scanning electrode side circuit 8 comprises an addressing stage 11 (ADD / ER) designed to provide an addressing potential for electrodes selected by the control circuit 7. This addressing stage 11 may be completed by a erase stage at a different voltage.
  • the circuit 8 also comprises a stage 12 (BIAS) of prepolarization or precharging of the electrodes. It further comprises a floor receipt ⁇ peration energy 13 (PR) which applies more particu larly ⁇ the present invention, for imposing a potential on the electrodes 3 by removing surplus loads or loads causing missing during the maintenance phase ⁇ maintenance.
  • BIAS stage 12
  • PR floor receipt ⁇ peration energy 13
  • the circuit 8 ' is summed up with a stage 13' of energy recovery identical to the stage 13 on the scanning electrode side, to which all the lines 4 are connected together.
  • FIG. 3 very schematically represents a conventional example of stages 13 and 13 'of energy recovery of the type to which the present invention applies, connected to a panel 2 of electrodes 3 and 4 of a screen plasma.
  • the electrode panel 2 has been symbolized by the various lines 3 and 4 between which equivalent line capacitors C1 have been represented.
  • the entire panel 2, of which all the scanning electrodes 3 and respectively all the maintenance electrodes 4 are interconnected during the energy recovery phase, is equivalent to a capacitance Cp.
  • the interconnection of all the scanning electrodes is effected by means of the control circuit 7 and other on-off switches of the prepolarization 12 and addressing stages 11 (not shown in FIG. 23 of the electrodes 3 to an access terminal 31 to the stage 13.
  • each stage 13 or 13 'or Weber type energy recovery circuit is designed to impose a potential on the terminal 23 or 24 by discharging excess charges and causing these electrodes missing charges during the maintenance phase .
  • the stage 13 mainly comprises an inductive element L connecting, by a bidirectional switch 32, an electrode 33 of a capacitor Cs to the terminal 31 connectable to the common terminal (during the energy recovery phase) of the electrodes 3.
  • output terminal 31 of the stage 13 is connected by a switch M1 to a terminal 25 for applying a positive potential Vs and, by a switch M3, to a terminal 26 for applying a reference potential (typically the mass) .
  • each switch Ml or M3 is in parallel with a diode (typically the intrinsic diode of a MOS transistor constituting the switch) whose anode is connected to the terminal 31, respectively 26.
  • the switch 32 is typically consisting of two switches M5, M6 anti ⁇ parallel and each in series with a diode D5, D6 respectively.
  • the respective midpoints of the series associations of the transistor M5 and the diode D5 and the transistor M6 and the diode D6 are connected to the terminal 25 for applying the potential Vs of positive supply and to the terminal 25 of mass by means of D1 and D2 blocking diodes (clamping diodes).
  • D1 and D2 blocking diodes clampping diodes.
  • the same structure is found on the circuit side 13 'where a bidirectional switch 32' connects an electrode 33 'of a capacitor Cs' whose other electrode is at the reference potential, to a first terminal of an inductive element L' whose the other terminal is connected to terminal 31 'the floor outlet 13', 24 connectable to the common terminal electrode 4.
  • the terminal 31 is connectable to terminals 25 and 26 by inter ⁇ switches M2 and M4 (typically MOS transistors) and the bidirectional switch 32 'has the same structure as the switch 32 of the stage 13 (switches M7 and M8 in antiparallel and each in series with a diode D7 and D8 between the inductance L 'and the terminal 33', the respective midpoints of the series associations being connected by blocking diodes D1 'and D2' to the terminal 25 and the ground 26).
  • switches M2 and M4 typically MOS transistors
  • the switches M1, M2, M3, M4 constitute an H bridge, the switches M1 and M4 being intended to be closed at the same time as the switches M2 and M3.
  • a first so-called prepolarization or precharging phase uses stage 12 to excite the cells of the screen in order to pre-energize the contained gas and thereby lower the address voltage under which will subsequently discharge.
  • the excitation is carried out for example at a voltage of the order of 400 volts.
  • This prepolarization phase is followed by a so-called stabilization phase and then an erasure phase whose objective is to bring the scanning and maintenance electrodes to a potential of erasing the mass generally.
  • the erase and prepolarization phases have the effect of suppressing the charges in order to avoid unwanted ignitions.
  • addressing phase which is intended to provide a corresponding address voltage of a given level on the electrodes 3 according to the respective states of the addressing transistors of the circuits 7. The period during which the Addressing level is applied to the electrodes depends on the rank of the line in the screen.
  • This addressing phase is followed by the input phase (sustain) to which more particularly applies to the present invention.
  • a pulse train of constant duty cycle and amplitude Vs (of the order of 200 volts) is applied to the terminal 23.
  • the stages of recovery 13 of the electrodes 3 and 13 'of the electrodes 4 are used to facilitate the charging of the electrodes 3 (respecti vely ⁇ 4) at Vs and facilitate the discharge of these same electrodes in the respective low levels of the pulses.
  • the closures and openings of the switches (Ml, M4, M3, M2) are alternated with the rhythm of the Vs level pulses to be applied to the terminals 31 and 31 '.
  • the frequency of the pulse trains is of the order of 200 to 250 kHz and the average frequency on a subframe of the image of the holding periods is between 0 and 85 kHz.
  • the equivalent capacitance Cp of the screen is alternately charged and discharged by the resonant circuits of the scanning and maintenance electrodes by exploiting a charge level at Vs / 2 of the capacitors. Cs and Cs'.
  • Each energy recovery pulse starts by closing the switches M6 and M4 to circulate a current in the inductance L and bring the voltage Vp across the electrodes 3 at the voltage level Vs, followed by a resonance phase. following which the transistor M1 and the transistor M4 of the H-bridge are closed, and is terminated by a discharge phase by the closing of the transistor M5 (the transistor M4 remaining closed) allowing the disappearance of the voltage Vp by the resonant circuit L-Cs. The next pulse is performed on the maintenance electrode side 4 (transistors M8, M3, then M2, M3, then M3, M7) and so on.
  • the resonance phase serves in particular to reduce the losses in the H-bridge transistors and to facilitate the transition between the levels in order to avoid current peaks in the screen.
  • Dl 'and D2' of blocking of the stage serve to evacuate the overcurrent of diodes D5 and D6 (respectively D8 and D7) that lock at the end of the charging or discharging phase, and limit surges to protect the switches.
  • a disadvantage of the known circuits is that they require high voltage components, in particular for the switches M5 and M6 and the diodes D5 and D6.
  • the voltage Vs is of the order of 200 volts and each transistor M5 or M6 sees half of this supply voltage when the capacitor Cs is loaded at the value Vs / 2.
  • a problem arises at startup where the capacitor Cs is discharged and where one of the two transistors (M5) and one of the diodes (D6) then sees a voltage of the order of 200 volts, which requires the use of tran ⁇ sistors and diodes supporting several hundred volts. This increases the size of the transistors and increases the losses.
  • Another problem is related to an asymmetry between the charging and discharging phases due to impedances different from the switches M5 and M6.
  • Another disadvantage of the known circuit is that the blocking diode are long discharging currents recou ⁇ butent.
  • the present invention aims to overcome all or part of the disadvantages of known control circuits plasma screen.
  • the invention aims more particularly at enabling the use of lower voltage components in the energy recovery circuits.
  • the invention also aims to reduce the losses by allowing a reduction in size of the control switches of the energy recovery circuit.
  • the invention also aims at preserving the architecture of the conventional circuits and, in particular, at requiring no modification of the other control stages of the plasma screen.
  • the present invention aims to evacuate more quickly the overlap currents in the diodes of the bidirectional switches of the energy recovery circuits.
  • the present invention provides a method of controlling a power recovery stage of a plasma screen having a resonant circuit of at least one inductive element and a capacitive element, comprising at least one step of precharging the capacitive element to half of a supply voltage of one screen.
  • activation switches of the energy recovery stage ⁇ are inhibited during the precharging step, at least until the voltage across the terminals of the capacitive element has reached a first threshold depending on the supply voltage.
  • the step of precharging the capacitive element is inhibited when the voltage thereacross reaches a second threshold function from the upper supply voltage to the first.
  • the precharge of the capacitive element is obtained by means of a controllable current source.
  • the invention also provides a control circuit for an energy recovery stage of a plasma screen having a resonant circuit of at least one inductive element and at least one capacitive element, comprising: a controllable current source between a terminal of application of a supply voltage and the capa ⁇ citif element; and at least a first comparison comparator of the voltage across the capacitive element with respect to a first threshold for activating switching elements of the recovery circuit.
  • a second comparator compares the voltage across the capacitive element with respect to a second threshold greater than the first to control said current source.
  • the invention also provides an energy recovery stage of a plasma screen comprising a resonant circuit of at least one capacitor in series with a bidirectional switch and at least one inductive element between the midpoint of a first branch.
  • two blocking circuits each comprise a Zener diode in series with a diode between the terminal of the inductor connected to the bidirectional switch and two terminals for applying the supply voltage.
  • the invention also provides a plasma screen.
  • FIGS. have been previously described are intended to expose the state of the art and the problem posed;
  • FIG. 4 very schematically shows in the form of blocks an embodiment of an energy recovery circuit according to the present invention;
  • Fig. 5 is a detailed electrical diagram of one embodiment of the energy recovery circuit of Fig. 4;
  • FIG. 6 illustrates, by a timing diagram, the operation of the circuit of FIG. 5;
  • FIG. 7A, 7B, 7C, 7D, 7E, 7F, 7G, 7H, 71, 7J and 7K are timing diagrams illustrating the phase of energy recovery in a plasma screen according to an embodiment of the invention ; and FIG. 8 represents a variant of an energy recovery circuit according to the second aspect of the invention.
  • the same elements have been designated by the same references in the different figures and the chronograms have been drawn without respect of scale. For the sake of clarity, only the elements and operating steps that are useful for understanding the invention have been shown in the figures and will be described later. In particular, the generation of appropriate control signals to the operation of the switches has not been detailed, the invention being compatible with uti ⁇ lisation conventional such signals generation circuits. Similarly, the complete operation of a plasma display (particularly that of the other control stages of the scanning or maintenance electrodes) has not been detailed, the invention being again compatible with conventional systems. detailed description
  • a feature of an embodiment of the present invention is to preload the capacitor of the resonant circuit of a Weber-type energy recovery stage of a plasma display at half of the supply voltage.
  • FIG. 4 very schematically shows in the form of blocks an embodiment of a stage 43 of energy recovery of a plasma screen according to the present invention. invention. For simplicity, only one stage 43 on the scanning electrode side (3, FIGS. 1, 2 and 3) has been shown. The other stage on the electrodes side of maintenance has an identical structure.
  • inductor L and the capacitor Cs forming the resonant circuit and the Bidirectional switch ⁇ tional 32 consisting of two MOS transistors M5 and M6 each in series with a diode D5, D6, respectively, in anti-parallel between an electrode 33 capacitor Cs and a first terminal of inductance L.
  • the other terminal of inductor L is connected to a terminal 31 constituting a midpoint of a first branch of an H bridge connectable to the electrode board ( here a first transistor Ml in series with a second transistor M2 between two terminals 25 and 26 for applying the supply voltage Vs).
  • the blocking diodes (D1 and D2, FIG. 3) have not been shown.
  • the various switches are, for example, constituted by MOS transistors, which according to a preferred embodiment of the invention are sized to withstand a voltage approximately equivalent to half the supply voltage Vs, plus one value corresponding to the expected voltage peaks, for example, of the order of 10 to 15% of the voltage Vs.
  • the electrode 33 of the capacitor Cs is connected to the terminal 25 for applying the voltage Vs by a controllable current source 41.
  • the source 41 is controlled by a comparison circuit 42 (COMP Vcs / Vs) of the voltage Vcs across the capacitor Cs with respect to at least one threshold which is a function of the supply voltage Vs.
  • the role of the circuit 42 is to activate the current source 41 only during start-up periods when a precharge of the capacitor Cs is required. This feature will be detailed later in connection with Figure 5.
  • the switches M1, M2, M5 and M6 (as well as the switches of the other part of the H-bridge (M2, M4, FIG. 3)) are controlled synchronously by a circuit 45 (CTRL) whose outputs S are connected to the control terminals (gates) of the different switches.
  • CTRL circuit 45
  • FIG. 5 represents an example of a detailed diagram of an energy recovery stage of a plasma screen according to the present invention.
  • the different switches have been represented in the form of MOS transistors in contrast to the previous figures.
  • the controllable current source 41 consists of a transistor M41 in series with a resistor R41 between the terminal 25 and the anode of a diode D41 whose cathode is connected to the electrode 33 of the capacitor cs.
  • a bias resistor Rp connects the gate of the transistor M41 to the terminal 25 and a Zener diode DZ41 connects this gate to the anode of the diode D41 (the anode of the diode DZ41 being connected to the anode of the diode D41) .
  • Such a current source structure is conventional.
  • the source 41 is made controllable by means of a switch (MOS transistor MlO) connecting the anode of the diodes DZ41 and D41 to the ground 26.
  • MOS transistor MlO MOS transistor MlO
  • the source 41 charges the capacitor Cs.
  • the transistor MlO is on, the current source is connected to ground.
  • the diode DZ41 sets the value of the current by limiting the voltage across its resistive elements. In addition, it limits the gate-source voltage of the transistor MlO.
  • Other structures of controllable current source are conceivable.
  • the gate of the transistor MlO is connected at the output of a first comparator 421 of the circuit 42 whose role is to compare a voltage proportional to the voltage Vcs across the capacitor Cs with respect to a threshold VB.
  • the threshold Vth of the comparator 421 is fixed for example by a resistive bridge consisting of two resistors R1 and R2 fed in series by the voltage Vs.
  • the threshold voltage Vth is applied, for example, to the inverting input of the comparator 421 whose non-inverting input receives a voltage representative of the voltage at terminals of the capacitor Cs, obtained by a second resistive bridge consisting of three resistors R3, R4 and R5 in series between the terminal 33 and the ground.
  • the non-inverting input of the comparator 421 is connected to the midpoint between the resistors R4 and R5.
  • the output of the comparator 421 is connected to the gate of the transistor MlO (where appropriate, via the circuit 45).
  • a second comparator 422 of the circuit 42 compares the voltage Vth supplied by the bridge R1-R2 with respect to a second information representative of the voltage across the conden ⁇ sateur Cs different from the first.
  • This second voltage is taken at the midpoint of the series association of the resistors R3 and R4 connected to the non-inverting input of the comparator 422 whose inverting input is connected to the midpoint between the resistors R1 and R2.
  • the output of the comparator 422 is connected to the circuit 45 for controlling the switches.
  • the role of the two thresholds is to distinguish the activation of the energy recovery circuit (transistors M5, M6 and H-bridge consisting of transistors Ml, M3 and M2, M4 shown in dashed lines) of the activation or deactivation of the source. current 41 by the control of the transistor MlO.
  • the blocking diodes D1 and D2 have been represented between the transistors M5, respectively M6 and the diode D5 respectively D6.
  • FIG. 6 illustrates, by a chronogram representing the voltage Vcs across the capacitor Cs as a function of time, the operation of the circuit of FIG. 5.
  • the circuit 42 provides on the one hand a blocking signal of the transistor MlO by the comparator 421 while the comparator 422 gives the information to the block 45 that the voltage Vcs is lower than the first threshold VA so that the switches M5, M6, Ml and M3 are all open.
  • the voltage Vc across the capacitor increases substantially linearly by the load by means of the current source 41.
  • the comparator 422 switches and the control block 45 activates the phase energy recovery.
  • the current source 41 is not yet inhibited so that the voltage across the capacitor Cs continues to increase.
  • the threshold VA is chosen so that the recovery voltage VRM of the diodes D5 and D6 is lower than the Vs-VA level plus the overvoltages related to the switching operations.
  • the comparator 421 closes the transistor MlO, which eliminates the charge of the capacitor Cs by the current source 41.
  • the increase in voltage Vcs up to level Vs / 2 is continued by the resonant circuits.
  • the difference between the threshold VB and the level Vs / 2 is chosen as a function of the manufacturing tolerances of the various components and in particular of the technological dispersions during the manufacture of the resistances of the dividing bridges and the transistors.
  • the threshold VB must be sufficiently lower than the value Vs / 2 so as not to be crossed in case of technological dispersion between the constituents. This tolerance range You is illustrated in FIG. 6 by dashed lines. With these notations, VB ⁇ Vs / 2-Tol / 2.
  • FIG. 6 illustrates operation of an energy recovery stage once the preload conden ⁇ sateur Cs obtained.
  • These timing diagrams respectively illustrate examples of the behavior of the control signals (state of closure ⁇ ture or opening) of the transistors Ml, M2, M3, M4, M5, M6, M7, M8 and MlO (and MlO ') as well as the corresponding paces of the voltage Vp across the equivalent capacitance Cp of the plasma screen and the currents IL and IL 'in the inductances of the energy recovery stages.
  • the precharging illustrated in FIG. 6 occurs before the instant of activation of the stage at which, for example, the transistor M6 (FIG. 7F) is switched on, the transistor M4 (FIG. 7D) being already on. and the transistor MlO remaining blocked until time t2 (VA threshold) slightly later than time tl. From the moment tl, the current
  • FIG. 7K in the inductive element L charges the equivalent capacitor Cp (voltage Vp, FIG. 7J) until a level Vs (neglecting the voltage drops in the components in the on state) is reached at a time t4.
  • Vp voltage
  • Vs voltage drops in the components in the on state
  • t4 the diode D5 is blocked, and there is a phenomenon of recovery which causes an increase of the current in the inductance L.
  • This energy is discharged by the diodes D6 and D2 in a time ( ⁇ t, Figure 7K) which is fixed by the voltage across the inductance.
  • the duration ⁇ t must of course be less than the interval t5-t4.
  • the blocking of the transistor M6 is illustrated at time t4, knowing that its control can be slightly delayed by the automatic blocking of the diode D5.
  • the transistor M1 (FIG. 7A) is turned on from the instant t4.
  • transistor M5 is turned on at time t5 (FIG. 7E) at the same time (or slightly thereafter) as transistor M1 is off.
  • the transistors M4 and M5 are blocked from the instant t6 and the transistor M3 (FIG. 7C) is turned on at this instant t6 (in practice, slightly after the blocking of the transistor M4).
  • An advantage of the present invention is that the voltage seen by transistors M5 and M6 is now limited to half of the supply voltage (plus switching overvoltages).
  • Another advantage of the present invention is that in case of asymmetry due to impedance differences between the switches M5, M6, this asymmetry is compensated by the precharge system.
  • Another advantage of the present invention is that the thresholds adapt to possible variations of the supply voltage Vs.
  • Figure 8 shows an embodiment of a stage 43 of energy recovery according to a second aspect of the invention. For simplicity, the precharge elements of capacitor Cs at point 33 have not been shown.
  • a first zener diode DZ1 is interposed between the blocking diode D1 (whose anode is connected to the anode of the diode D5) and the terminal 25 for applying the supply voltage. Vs.
  • a second Zener diode DZ2 is interposed between the cathode of the diode D6 and that of the blocking diode D2 connected to the ground 26. The role of the Zener diodes DZ1 and DZ2 is to set a blocking voltage higher than that provided by the diodes D1 and D2.
  • One advantage of setting the clamping voltage by means of a Zener diode DZ1 or DZ2 is that it makes it possible to reduce the time ⁇ t of evacuation of the energy accumulated in the inductance L following the respective blockages of the diodes D5 and D6. This advantage is particularly noticeable with the increase in operating frequencies of the screens which reduces the available intervals.
  • the present invention is susceptible of various variations and modifications which will be apparent to those skilled in the art.
  • the switches described as being MOS transistors may be replaced by insulated gate bipolar transistors (IGBTs).
  • IGBTs insulated gate bipolar transistors
  • the dimensions to be given to the various constituents of the starting circuit of the invention are within the abilities of those skilled in the art from the functional indications given above.
  • the adap ⁇ tation generally digital control circuits of the plasma display to reflect the thresholds detected by the invention is also within the reach of the skilled person using conventional tools.

Abstract

The invention relates to a method and a circuit for controlling an energy recovery stage of a plasma screen comprising a resonant circuit of at least one inductive element (L) and of a capacitive element (Cs), in which the capacitive element is precharged halfway with a supply voltage (Vs) of the screen.

Description

COMMANDE D'UN ETAGE DE RECUPERATION D'ENERGIE D'UN ECRAN PLASMA CONTROLLING A ENERGY RECOVERY STAGE OF A PLASMA DISPLAY
Domaine de l' inventionField of the invention
La présente invention concerne de façon générale les écrans plasma qui comprennent deux plaques parallèles portant chacune des réseaux d'électrodes et entre lesquelles est présent un gaz provenant de décharges lumineuses à des régions d'intersection entre les électrodes des différentes plaques.The present invention generally relates to plasma screens which comprise two parallel plates each carrying electrode arrays and between which is present a gas from light discharges to regions of intersection between the electrodes of the different plates.
La présente invention concerne plus particulièrement la commande des réseaux d'électrodes de l'écran dans une phase dite d'entretien (sustain) dans laquelle les électrodes de chaque réseau sont excitées par une tension alternative. Exposé de l'art antérieurThe present invention more particularly relates to the control of the electrode arrays of the screen in a so-called maintenance phase (sustain) in which the electrodes of each array are excited by an alternating voltage. Presentation of the prior art
La figure 1 représente, de façon générale et très schématique, la structure d'un écran 1 à plasma (plasma display panel ou PDP) du type auquel s'applique la présente invention. Deux plaques parallèles désignées par la référence globale 2 portent chacune des électrodes généralement perpendiculaires d'une plaque à l'autre et parallèles entre elles sur une même plaque. Chaque ligne L de l'écran est définie par deux électrodes 3 et 4 parallèles entre elles et chaque colonne C de l'écran est définie par une électrode 5 dans l'autre direction, portée par l'autre plaque. L'intersection d'une ligne L et d'une colonne C définit un pixel P de l'écran. Pour l'allumage d'un pixel, une décharge lumineuse est organisée entre les électrodes 3 et 4 d'une ligne L, adressée par la colonne 5 correspondante.FIG. 1 represents, generally and very schematically, the structure of a plasma display panel (PDP) 1 of the type to which the present invention applies. Two parallel plates designated by the overall reference 2 each carry electrodes generally perpendicular from one plate to another and parallel to each other on the same plate. Each line L of the screen is defined by two electrodes 3 and 4 parallel to each other and each column C of the screen is defined by an electrode 5 in the other direction, carried by the other plate. The intersection of a line L and a column C defines a pixel P of the screen. For lighting a pixel, a light discharge is organized between the electrodes 3 and 4 of a line L, addressed by the corresponding column 5.
La commande de l'écran 2 est effectuée au moyen d'un circuit 6 de commande des électrodes de colonne (COL DRV) et de circuits 7 de commande d'un premier réseau d'électrodes (par exemple, 3) de ligne (SCAN DRV) dites de balayage. Le circuit 7 est relié à un premier circuit 8 de fourniture d'énergie (PW CT). Le deuxième réseau d'électrodes (par exemple, 4) de lignes dites d'entretien est relié directement à un circuit 8' (PW REF) de fourniture d'énergie (généralement un potentiel de référence). Les circuits 6, 7, 8 et 8 ' sont commandés et synchronisés par une unité 9 (CU) généralement un calculateur ou un circuit en logique câblée.The control of the screen 2 is performed by means of a column 6 for controlling the column electrodes (COL DRV) and control circuits 7 for a first network of electrodes (for example, 3) of line (SCAN RVD) say sweeping. The circuit 7 is connected to a first power supply circuit 8 (PW CT). The second electrode array (for example, 4) of so-called maintenance lines is directly connected to a power supply circuit 8 '(PW REF) (generally a reference potential). The circuits 6, 7, 8 and 8 'are controlled and synchronized by a unit 9 (CU) generally a computer or a wired logic circuit.
La présente invention concerne plus particulièrement une partie des circuits 8 et 8 ' de fourniture d'énergie.The present invention relates more particularly to a portion of the power supply circuits 8 and 8 '.
La figure 2 représente, de façon très schématique et sous forme de blocs, un exemple classique d'architecture de circuits 8 et 8 ' associés aux circuits de commande des électrodes de balayage et d'entretien du type auquel s'applique la présente invention. En figure 2, deux lignes 3 et 4 de l'écran ont été symbolisées par leur capacité équivalente dont les deux électrodes sont respectivement reliées au circuit de balayage 7 et au circuit de fourniture d'énergie 8'. Typi¬ quement, les circuits de commande de chaque électrode de balayage (contenus dans le bloc 7) sont formés d'interrupteurs fonc¬ tionnant en tout ou rien pour amener, sur une des électrodes de la ligne considérée, différents niveaux de tension à différentes phases de fonctionnement. Pour simplifier, les différents signaux de commande n'ont pas été illustrés aux figures. En pratique, chaque électrode de balayage est associée à plusieurs interrupteurs du circuit 7 qui servent à sélectionner celles des lignes de l'écran qui vont recevoir les différentes tensions. Tous les circuits de commande des différentes électrodes ont leurs bornes de fourniture d'énergie respectives interconnectées au circuit 8 de fourniture d'énergie commun. Le circuit 8 côté électrodes de balayage comporte un étage d'adressage 11 (ADD/ER) chargé d'apporter un potentiel d'adressage à des électrodes sélectionnées par le circuit de commande 7. Cet étage d'adressage 11 peut être complété par un étage d'effacement à une tension différente. Le circuit 8 comporte également un étage 12 (BIAS) de prépolarisation ou de précharge des électrodes . Il comporte en outre un étage de récu¬ pération d'énergie 13 (PR) auquel s'applique plus particu¬ lièrement la présente invention, destiné à imposer un potentiel sur les électrodes 3 en évacuant des charges en surplus ou en amenant des charges manquantes pendant la phase de fonction¬ nement dite d'entretien.FIG. 2 very schematically shows in the form of blocks a typical example of circuit architecture 8 and 8 'associated with the control circuits of the scanning and maintenance electrodes of the type to which the present invention applies. In FIG. 2, two lines 3 and 4 of the screen have been symbolized by their equivalent capacitance, the two electrodes of which are respectively connected to the scanning circuit 7 and to the energy supply circuit 8 '. ¬ Typi cally, the control circuitry of each scanning electrode (contained in the block 7) are formed of dark switches ¬ tionnant all or nothing to cause, on one of the electrodes of the line considered, different voltage levels at different phases of operation. For simplicity, the various control signals have not been illustrated in the figures. In practice, each scanning electrode is associated with several switches of the circuit 7 which serve to select those of the lines of the screen that will receive the different voltages. All the control circuits of the different electrodes have their respective power supply terminals interconnected to the common energy supply circuit 8. The scanning electrode side circuit 8 comprises an addressing stage 11 (ADD / ER) designed to provide an addressing potential for electrodes selected by the control circuit 7. This addressing stage 11 may be completed by a erase stage at a different voltage. The circuit 8 also comprises a stage 12 (BIAS) of prepolarization or precharging of the electrodes. It further comprises a floor receipt ¬ peration energy 13 (PR) which applies more particu larly ¬ the present invention, for imposing a potential on the electrodes 3 by removing surplus loads or loads causing missing during the maintenance phase ¬ maintenance.
Côté électrodes d'entretien, le circuit 8' se résume à un étage 13' de récupération d'énergie identique à l'étage 13 côté électrodes de balayage, auquel sont connectées ensemble toutes les lignes 4.On the maintenance electrode side, the circuit 8 'is summed up with a stage 13' of energy recovery identical to the stage 13 on the scanning electrode side, to which all the lines 4 are connected together.
La figure 3 représente, de façon très schématique, un exemple classique d'étages 13 et 13' de récupération d'énergie du type auquel s ' applique la présente invention, connectés à un panneau 2 d'électrodes 3 et 4 d'un écran plasma. Le panneau d'électrodes 2 a été symbolisé par les différentes lignes 3 et 4 entre lesquelles ont été représentées des capacités équivalentes Cl de ligne. L'ensemble du panneau 2, dont toutes les électrodes de balayage 3 et respectivement toutes les électrodes de main- tien 4 sont interconnectées pendant la phase de récupération d'énergie, est équivalent à une capacité Cp. L'interconnexion de toutes les électrodes de balayage s'effectue au moyen du circuit de commande 7 et d'autres interrupteurs en tout ou rien des étages (non représentés en figure 3) de prépolarisation 12 et d'adressage 11 relient respectivement la borne alors commune 23 des électrodes 3 à une borne d'accès 31 à l'étage 13. L'interconnexion de toutes les électrodes d'entretien 4 est structurelle et leur borne commune 24 est reliée à une borne d'accès 31' de l'étage 13'. Chaque étage 13 ou 13' ou circuit de récupération d'énergie dit de type Weber est destiné à imposer un potentiel sur la borne 23 ou 24 en évacuant des charges en surplus et en amenant à ces électrodes des charges manquantes pendant la phase d'entretien.FIG. 3 very schematically represents a conventional example of stages 13 and 13 'of energy recovery of the type to which the present invention applies, connected to a panel 2 of electrodes 3 and 4 of a screen plasma. The electrode panel 2 has been symbolized by the various lines 3 and 4 between which equivalent line capacitors C1 have been represented. The entire panel 2, of which all the scanning electrodes 3 and respectively all the maintenance electrodes 4 are interconnected during the energy recovery phase, is equivalent to a capacitance Cp. The interconnection of all the scanning electrodes is effected by means of the control circuit 7 and other on-off switches of the prepolarization 12 and addressing stages 11 (not shown in FIG. 23 of the electrodes 3 to an access terminal 31 to the stage 13. The interconnection of all the maintenance electrodes 4 is structural and their common terminal 24 is connected to an access terminal 31 'of the stage 13 '. Each stage 13 or 13 'or Weber type energy recovery circuit is designed to impose a potential on the terminal 23 or 24 by discharging excess charges and causing these electrodes missing charges during the maintenance phase .
L'étage 13 comporte principalement un élément inductif L reliant, par un commutateur bidirectionnel 32, une électrode 33 d'un condensateur Cs à la borne 31 connectable à la borne commune (pendant la phase de récupération d'énergie) des électrodes 3. La borne 31 de sortie de l'étage 13 est connectée par un interrupteur Ml à une borne 25 d'application d'un potentiel positif Vs et, par un interrupteur M3, à une borne 26 d'application d'un potentiel de référence (typiquement la masse) . En pratique, chaque interrupteur Ml ou M3 est en paral- lèle avec une diode (typiquement la diode intrinsèque d'un transistor MOS constituant l'interrupteur) dont l'anode est connectée à la borne 31, respectivement 26. Le commutateur 32 est typiquement constitué de deux interrupteurs M5, M6 en anti¬ parallèle et chacun en série avec une diode D5, D6 respec- tivement . Les points milieux respectifs des associations en série du transistor M5 et de la diode D5 et du transistor M6 et de la diode D6 sont reliés à la borne 25 d'application du potentiel Vs d'alimentation positif et à la borne 25 de masse par des diodes de blocage Dl et D2 (clamping diodes) . La même structure se retrouve côté circuit 13' où un interrupteur bidirectionnel 32' relie une électrode 33' d'un condensateur Cs' dont l'autre électrode est au potentiel de référence, à une première borne d'un élément inductif L' dont l'autre borne est reliée à la borne 31' de sortie de l'étage 13', connectable à la borne 24 commune des électrodes 4. La borne 31' est connectable aux bornes 25 et 26 par des inter¬ rupteurs M2 et M4 (typiquement des transistors MOS) et le commutateur bidirectionnel 32 ' a la même structure que le commutateur 32 de l'étage 13 (interrupteurs M7 et M8 en anti- parallèle et chacun en série avec une diode D7 et D8 entre l'inductance L' et la borne 33', les points milieux respectifs des associations en série étant connectés par des diodes de blocage Dl' et D2 ' à la borne 25 et à la masse 26) .The stage 13 mainly comprises an inductive element L connecting, by a bidirectional switch 32, an electrode 33 of a capacitor Cs to the terminal 31 connectable to the common terminal (during the energy recovery phase) of the electrodes 3. output terminal 31 of the stage 13 is connected by a switch M1 to a terminal 25 for applying a positive potential Vs and, by a switch M3, to a terminal 26 for applying a reference potential (typically the mass) . In practice, each switch Ml or M3 is in parallel with a diode (typically the intrinsic diode of a MOS transistor constituting the switch) whose anode is connected to the terminal 31, respectively 26. The switch 32 is typically consisting of two switches M5, M6 anti ¬ parallel and each in series with a diode D5, D6 respectively. The respective midpoints of the series associations of the transistor M5 and the diode D5 and the transistor M6 and the diode D6 are connected to the terminal 25 for applying the potential Vs of positive supply and to the terminal 25 of mass by means of D1 and D2 blocking diodes (clamping diodes). The same structure is found on the circuit side 13 'where a bidirectional switch 32' connects an electrode 33 'of a capacitor Cs' whose other electrode is at the reference potential, to a first terminal of an inductive element L' whose the other terminal is connected to terminal 31 'the floor outlet 13', 24 connectable to the common terminal electrode 4. the terminal 31 is connectable to terminals 25 and 26 by inter ¬ switches M2 and M4 (typically MOS transistors) and the bidirectional switch 32 'has the same structure as the switch 32 of the stage 13 (switches M7 and M8 in antiparallel and each in series with a diode D7 and D8 between the inductance L 'and the terminal 33', the respective midpoints of the series associations being connected by blocking diodes D1 'and D2' to the terminal 25 and the ground 26).
Les interrupteurs Ml, M2, M3, M4 constituent un pont en H, les interrupteurs Ml et M4 étant destinés à être fermés en même temps de même que les interrupteurs M2 et M3.The switches M1, M2, M3, M4 constitute an H bridge, the switches M1 and M4 being intended to be closed at the same time as the switches M2 and M3.
Un exemple de circuit de commande d'un écran plasma est décrit dans la demande internationale WO03/102907.An example of a control circuit of a plasma screen is described in the international application WO03 / 102907.
La commande de l ' écran se divise temporellement en trames et en sous trames d'affichage pendant lesquelles sont présentes différentes phases de fonctionnement. Dans chaque sous trame d'affichage, une première phase dite de prépolarisation ou de précharge utilise l'étage 12 pour exciter les cellules de l'écran afin de pré-exciter le gaz contenu et faire baisser ainsi la tension d'adressage sous laquelle s'effectuera par la suite la décharge. Pendant la phase de prépolarisation, l'excitation s'effectue par exemple sous une tension de l'ordre de 400 volts.The control of the screen splits temporally into frames and subframes of display during which are present different phases of operation. In each sub-display frame, a first so-called prepolarization or precharging phase uses stage 12 to excite the cells of the screen in order to pre-energize the contained gas and thereby lower the address voltage under which will subsequently discharge. During the prepolarization phase, the excitation is carried out for example at a voltage of the order of 400 volts.
Cette phase de prépolarisation est suivie d'une phase dite de stabilisation puis d'une phase d'effacement ayant pour objectif d'amener les électrodes de balayage et d'entretien à un potentiel d'effacement généralement la masse. Les phases d'effacement et de prépolarisation ont pour effet de supprimer les charges afin d'éviter des allumages non souhaités. On assiste ensuite à une phase dite d'adressage qui a pour objet d'apporter une tension d'adressage correspondant d'un niveau donné sur les électrodes 3 selon les états respectifs de transistors d'adressage des circuits 7. La période pendant laquelle le niveau d'adressage est appliqué aux électrodes dépend du rang de la ligne dans l'écran.This prepolarization phase is followed by a so-called stabilization phase and then an erasure phase whose objective is to bring the scanning and maintenance electrodes to a potential of erasing the mass generally. The erase and prepolarization phases have the effect of suppressing the charges in order to avoid unwanted ignitions. Then there is a so-called addressing phase which is intended to provide a corresponding address voltage of a given level on the electrodes 3 according to the respective states of the addressing transistors of the circuits 7. The period during which the Addressing level is applied to the electrodes depends on the rank of the line in the screen.
Cette phase d'adressage est suivie de la phase d'entre¬ tien (sustain) à laquelle s'applique plus particulièrement à la présente invention. Pendant cette phase, un train d'impulsions de rapport cyclique constant et d'amplitude Vs (de l'ordre de 200 volts) est appliqué sur la borne 23. Les étages de récupération 13 des électrodes 3, et 13' des électrodes 4, sont utilisés pour faciliter la charge des électrodes 3 (respecti¬ vement 4) au niveau Vs et faciliter la décharge de ces mêmes électrodes lors des niveaux bas respectifs des impulsions. Les fermetures et ouvertures des interrupteurs (Ml, M4, M3, M2) sont alternées au rythme des impulsions de niveau Vs à appliquer sur les bornes 31 et 31'. Il en résulte, sous l'effet du circuit de résonance constitué de l'inductance L et du condensateur Cs, l'application d'une tension alternative entre les lignes de balayage et d'entretien. Typiquement, la fréquence des trains d'impulsion est de l'ordre de 200 à 250 kHz et la fréquence moyenne sur une sous trame d'image des périodes de maintien est comprise entre 0 et 85 kHz.This addressing phase is followed by the input phase (sustain) to which more particularly applies to the present invention. During this phase, a pulse train of constant duty cycle and amplitude Vs (of the order of 200 volts) is applied to the terminal 23. The stages of recovery 13 of the electrodes 3 and 13 'of the electrodes 4, are used to facilitate the charging of the electrodes 3 (respecti vely ¬ 4) at Vs and facilitate the discharge of these same electrodes in the respective low levels of the pulses. The closures and openings of the switches (Ml, M4, M3, M2) are alternated with the rhythm of the Vs level pulses to be applied to the terminals 31 and 31 '. As a result, under the effect of the resonance circuit constituted by the inductance L and the capacitor Cs, the application of an alternating voltage between the scanning and maintenance lines. Typically, the frequency of the pulse trains is of the order of 200 to 250 kHz and the average frequency on a subframe of the image of the holding periods is between 0 and 85 kHz.
Pendant la phase d'entretien ou de récupération d'énergie, la capacité équivalente Cp de l'écran est alternativement chargée et déchargée par les circuits résonants des électrodes de balayage et d'entretien en exploitant un niveau de charge à Vs/2 des condensateurs Cs et Cs '.During the maintenance or energy recovery phase, the equivalent capacitance Cp of the screen is alternately charged and discharged by the resonant circuits of the scanning and maintenance electrodes by exploiting a charge level at Vs / 2 of the capacitors. Cs and Cs'.
Chaque impulsion de récupération d'énergie débute par une fermeture des interrupteurs M6 et M4 pour faire circuler un courant dans l'inductance L et amener la tension Vp aux bornes des électrodes 3 au niveau de tension Vs, suivie d'une phase de résonance à la suite de laquelle le transistor Ml et le transistor M4 du pont en H sont fermés, et est terminée par une phase de décharge par la fermeture du transistor M5 (le transistor M4 restant fermé) permettant la disparition de la tension Vp par le circuit résonant L-Cs. L'impulsion suivante est effectuée côté électrodes d'entretien 4 (transistors M8, M3, puis M2, M3, puis M3, M7) et ainsi de suite. La phase de résonance sert notamment à réduire les pertes dans les transistors du pont en H et à faciliter la transition entre les niveaux afin d'éviter les pics de courant dans l'écran.Each energy recovery pulse starts by closing the switches M6 and M4 to circulate a current in the inductance L and bring the voltage Vp across the electrodes 3 at the voltage level Vs, followed by a resonance phase. following which the transistor M1 and the transistor M4 of the H-bridge are closed, and is terminated by a discharge phase by the closing of the transistor M5 (the transistor M4 remaining closed) allowing the disappearance of the voltage Vp by the resonant circuit L-Cs. The next pulse is performed on the maintenance electrode side 4 (transistors M8, M3, then M2, M3, then M3, M7) and so on. The resonance phase serves in particular to reduce the losses in the H-bridge transistors and to facilitate the transition between the levels in order to avoid current peaks in the screen.
Au début de la phase de résonance, les diodes Dl et D2At the beginning of the resonance phase, the diodes D1 and D2
(respectivement Dl' et D2 ' ) de blocage de l'étage servent à évacuer le courant de recouvrement des diodes D5 et D6 (respectivement D8 et D7) qui se bloquent à la fin de la phase de charge ou décharge, et à limiter les surtensions pour protéger les interrupteurs.(respectively Dl 'and D2') of blocking of the stage serve to evacuate the overcurrent of diodes D5 and D6 (respectively D8 and D7) that lock at the end of the charging or discharging phase, and limit surges to protect the switches.
Un inconvénient des circuits connus est qu'ils requièrent des composants haute tension notamment pour les interrupteurs M5 et M6 et les diodes D5 et D6. En pratique, la tension Vs est de l'ordre de 200 volts et chaque transistor M5 ou M6 voit la moitié de cette tension d'alimentation quand le condensateur Cs est chargé à la valeur Vs/2. Un problème se pose toutefois au démarrage où le condensateur Cs est déchargé et où l'un des deux transistors (M5) et une des diodes (D6) voit alors une tension de l'ordre de 200 volts, ce qui oblige à utiliser des tran¬ sistors et diodes supportant plusieurs centaines de volts. Cela accroît la taille des transistors et augmente les pertes. Un autre problème est lié à une dissymétrie entre les phases de charge et de décharge en raison d'impédances différentes des interrupteurs M5 et M6.A disadvantage of the known circuits is that they require high voltage components, in particular for the switches M5 and M6 and the diodes D5 and D6. In practice, the voltage Vs is of the order of 200 volts and each transistor M5 or M6 sees half of this supply voltage when the capacitor Cs is loaded at the value Vs / 2. However, a problem arises at startup where the capacitor Cs is discharged and where one of the two transistors (M5) and one of the diodes (D6) then sees a voltage of the order of 200 volts, which requires the use of tran ¬ sistors and diodes supporting several hundred volts. This increases the size of the transistors and increases the losses. Another problem is related to an asymmetry between the charging and discharging phases due to impedances different from the switches M5 and M6.
Ces problèmes se retrouvent bien entendu du côté des interrupteurs M7 et M8 et des diodes D7 et D8. Un autre inconvénient est que la tension Vp obtenue entre les électrodes 3 et 4 à la résonance n'est pas égale à la tension Vs. Cela provoque d'éventuels pics lors des commuta¬ tions .These problems are of course found on the side of switches M7 and M8 and diodes D7 and D8. Another disadvantage is that the voltage Vp obtained between the electrodes 3 and 4 at resonance is not equal to the voltage Vs. This causes potential peaks at commuta ¬ tions.
Un autre inconvénient des circuits connus est que les diodes de blocage sont longues à évacuer les courants de recou¬ vrement .Another disadvantage of the known circuit is that the blocking diode are long discharging currents recou ¬ vrement.
Résumé de l' inventionSummary of the invention
La présente invention vise à pallier tout ou partie des inconvénients des circuits de commande connus d'écran à plasma.The present invention aims to overcome all or part of the disadvantages of known control circuits plasma screen.
L'invention vise plus particulièrement à permettre l'utilisation de composants plus basse tension dans les circuits de récupération d'énergie. L ' invention vise également à diminuer les pertes en permettant une diminution de taille des interrupteurs de commande du circuit de récupération d'énergie.The invention aims more particularly at enabling the use of lower voltage components in the energy recovery circuits. The invention also aims to reduce the losses by allowing a reduction in size of the control switches of the energy recovery circuit.
L'invention vise également à préserver l'architecture des circuits classiques et, en particulier, à ne nécessiter aucune modification des autres étages de commande de l'écran plasma.The invention also aims at preserving the architecture of the conventional circuits and, in particular, at requiring no modification of the other control stages of the plasma screen.
Selon un deuxième aspect, la présente invention vise à évacuer plus rapidement les courants de recouvrement dans les diodes des interrupteurs bidirectionnels des circuits de récupération d'énergie.According to a second aspect, the present invention aims to evacuate more quickly the overlap currents in the diodes of the bidirectional switches of the energy recovery circuits.
Pour atteindre tout ou partie des ces objets ainsi que d'autres, la présente invention prévoit un procédé de commande d'un étage de récupération d'énergie d'un écran plasma compor- tant un circuit résonant d'au moins un élément inductif et d'un élément capacitif, comportant au moins une étape de précharge de l'élément capacitif à la moitié d'une tension d'alimentation de 1 'écran.To achieve all or part of these and other objects, the present invention provides a method of controlling a power recovery stage of a plasma screen having a resonant circuit of at least one inductive element and a capacitive element, comprising at least one step of precharging the capacitive element to half of a supply voltage of one screen.
Selon un mode de mise en oeuvre de la présente invention, des commutateurs d'activation de l'étage de récupé¬ ration d'énergie sont inhibés pendant l'étape de précharge, au moins jusqu'à ce que la tension aux bornes de l'élément capacitif ait atteint un premier seuil fonction de la tension d ' alimentation . Selon un mode de mise en oeuvre de la présente inven¬ tion, l'étape de précharge de l'élément capacitif est inhibée lorsque la tension à ses bornes atteint un deuxième seuil fonction de la tension d'alimentation supérieur au premier.According to an embodiment of the present invention, activation switches of the energy recovery stage ¬ are inhibited during the precharging step, at least until the voltage across the terminals of the capacitive element has reached a first threshold depending on the supply voltage. According to an embodiment of the present inven ¬, the step of precharging the capacitive element is inhibited when the voltage thereacross reaches a second threshold function from the upper supply voltage to the first.
Selon un mode de mise en oeuvre de la présente invention, la précharge de l'élément capacitif est obtenue au moyen d'une source de courant commandable.According to an embodiment of the present invention, the precharge of the capacitive element is obtained by means of a controllable current source.
L ' invention prévoit également un circuit de commande d'un étage de récupération d'énergie d'un écran plasma ayant un circuit résonant d'au moins un élément inductif et au moins un élément capacitif, comportant : une source de courant commandable entre une borne d'application d'une tension d'alimentation et l'élément capa¬ citif ; et au moins un premier comparateur de comparaison de la tension aux bornes de l'élément capacitif par rapport à un premier seuil pour activer des éléments de commutation du circuit de récupération.The invention also provides a control circuit for an energy recovery stage of a plasma screen having a resonant circuit of at least one inductive element and at least one capacitive element, comprising: a controllable current source between a terminal of application of a supply voltage and the capa ¬ citif element; and at least a first comparison comparator of the voltage across the capacitive element with respect to a first threshold for activating switching elements of the recovery circuit.
Selon un mode de réalisation de la présente invention, un deuxième comparateur compare la tension aux bornes de l'élément capacitif par rapport à un deuxième seuil supérieur au premier pour commander ladite source de courant .According to one embodiment of the present invention, a second comparator compares the voltage across the capacitive element with respect to a second threshold greater than the first to control said current source.
L'invention prévoit également un étage de récupération d'énergie d'un écran plasma comportant un circuit résonant d'au moins un condensateur en série avec un interrupteur bidirec- tionnel et au moins un élément inductif entre le point milieu d'une première branche d'un pont en H et la masse, ledit point milieu étant relié à des premières électrodes de l'écran et l'interrupteur bidirectionnel étant constitué d'une association en antiparallèle de deux interrupteurs chacun en série avec une diode .The invention also provides an energy recovery stage of a plasma screen comprising a resonant circuit of at least one capacitor in series with a bidirectional switch and at least one inductive element between the midpoint of a first branch. an H-bridge and the ground, said midpoint being connected to first electrodes of the screen and the bidirectional switch consisting of an antiparallel association of two switches each in series with a diode.
Selon un mode de réalisation de la présente invention, deux circuits de blocage comprennent chacun une diode Zener en série avec une diode entre la borne de l'inductance reliée à l'interrupteur bidirectionnel et deux bornes d'application de la tension d'alimentation.According to one embodiment of the present invention, two blocking circuits each comprise a Zener diode in series with a diode between the terminal of the inductor connected to the bidirectional switch and two terminals for applying the supply voltage.
L ' invention prévoit également un écran plasma . Brève description des dessinsThe invention also provides a plasma screen. Brief description of the drawings
Ces objets, caractéristiques et avantages, ainsi que d' autres de la présente invention seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi lesquelles : les figures 1 à 3 qui ont été décrites précédemment sont destinées à exposer l'état de la technique et le problème posé ; la figure 4 représente, de façon très schématique et sous forme de blocs, un mode de réalisation d'un circuit de récupération d'énergie selon la présente invention ; la figure 5 est un schéma électrique détaillé d'un mode de réalisation du circuit de récupération d'énergie de la figure 4 ; la figure 6 illustre, par un chronogramme, le fonctionnement du circuit de la figure 5 ; les figures 7A, 7B, 7C, 7D, 7E, 7F, 7G, 7H, 71, 7J et 7K sont des chronogrammes illustrant la phase de récupération d'énergie dans un écran à plasma selon un mode de mise en oeuvre de l'invention ; et la figure 8 représente une variante d'un circuit de récupération d'énergie selon le deuxième aspect de l'invention. De mêmes éléments ont été désignés par les mêmes références aux différentes figures et les chronogrammes ont été tracés sans respect d'échelle. Pour des raisons de clarté, seuls les éléments et étapes de fonctionnement qui sont utiles à la compréhension de l'invention ont été représentés aux figures et seront décrits par la suite. En particulier, la génération des signaux de commande adaptés au fonctionnement des interrupteurs n'a pas été détaillée, l'invention étant compatible avec l'uti¬ lisation de circuits classiques de génération de tels signaux. De même, le fonctionnement complet d'un écran à plasma (notam- ment celui des autres étages de commande des électrodes de balayage ou d'entretien) n'a pas été détaillé, l'invention étant là encore compatible avec les systèmes classiques. Description détailléeThese and other objects, features, and advantages of the present invention will be set forth in detail in the following description of particular embodiments in a nonlimiting manner in connection with the accompanying drawings, in which: FIGS. have been previously described are intended to expose the state of the art and the problem posed; FIG. 4 very schematically shows in the form of blocks an embodiment of an energy recovery circuit according to the present invention; Fig. 5 is a detailed electrical diagram of one embodiment of the energy recovery circuit of Fig. 4; FIG. 6 illustrates, by a timing diagram, the operation of the circuit of FIG. 5; FIGS. 7A, 7B, 7C, 7D, 7E, 7F, 7G, 7H, 71, 7J and 7K are timing diagrams illustrating the phase of energy recovery in a plasma screen according to an embodiment of the invention ; and FIG. 8 represents a variant of an energy recovery circuit according to the second aspect of the invention. The same elements have been designated by the same references in the different figures and the chronograms have been drawn without respect of scale. For the sake of clarity, only the elements and operating steps that are useful for understanding the invention have been shown in the figures and will be described later. In particular, the generation of appropriate control signals to the operation of the switches has not been detailed, the invention being compatible with uti ¬ lisation conventional such signals generation circuits. Similarly, the complete operation of a plasma display (particularly that of the other control stages of the scanning or maintenance electrodes) has not been detailed, the invention being again compatible with conventional systems. detailed description
Une caractéristique d'un mode de réalisation de la présente invention est de précharger le condensateur du circuit résonant d'un étage de récupération d'énergie de type Weber d'un écran plasma à la moitié de la tension d'alimentation.A feature of an embodiment of the present invention is to preload the capacitor of the resonant circuit of a Weber-type energy recovery stage of a plasma display at half of the supply voltage.
La figure 4 représente, de façon très schématique et sous forme de blocs, un mode de réalisation d'un étage 43 de récupération d'énergie d'un écran plasma selon la présente invention. Pour simplifier, seul un étage 43 côté électrodes de balayage (3, figures 1, 2 et 3) a été représenté. L'autre étage côté électrodes d'entretien a une structure identique.FIG. 4 very schematically shows in the form of blocks an embodiment of a stage 43 of energy recovery of a plasma screen according to the present invention. invention. For simplicity, only one stage 43 on the scanning electrode side (3, FIGS. 1, 2 and 3) has been shown. The other stage on the electrodes side of maintenance has an identical structure.
On retrouve l'inductance L et le condensateur Cs formant le circuit résonant ainsi que l'interrupteur bidirec¬ tionnel 32 constitué de deux transistors MOS M5 et M6 en série chacun avec une diode D5, respectivement D6, en anti-parallèle entre une électrode 33 du condensateur Cs et une première borne de l'inductance L. L'autre borne de l'inductance L est connectée à une borne 31 constituant un point milieu d'une première branche d'un pont en H connectable au panneau d'électrodes (ici un premier transistor Ml en série avec un deuxième transistor M2 entre deux bornes 25 et 26 d'application de la tension d'alimentation Vs). Pour simplifier, les diodes de blocage (Dl et D2, figure 3) n'ont pas été représentées.Include the inductor L and the capacitor Cs forming the resonant circuit and the Bidirectional switch ¬ tional 32 consisting of two MOS transistors M5 and M6 each in series with a diode D5, D6, respectively, in anti-parallel between an electrode 33 capacitor Cs and a first terminal of inductance L. The other terminal of inductor L is connected to a terminal 31 constituting a midpoint of a first branch of an H bridge connectable to the electrode board ( here a first transistor Ml in series with a second transistor M2 between two terminals 25 and 26 for applying the supply voltage Vs). For simplicity, the blocking diodes (D1 and D2, FIG. 3) have not been shown.
Les différents interrupteurs sont, par exemple, constitués de transistors MOS, qui selon un mode de mise en oeuvre préféré de l'invention, sont dimensionnés pour supporter une tension approximativement équivalente à la moitié de la tension d'alimentation Vs, majorée d'une valeur correspondant aux pics de tension attendus, par exemple, de l'ordre de 10 à 15 % de la tension Vs.The various switches are, for example, constituted by MOS transistors, which according to a preferred embodiment of the invention are sized to withstand a voltage approximately equivalent to half the supply voltage Vs, plus one value corresponding to the expected voltage peaks, for example, of the order of 10 to 15% of the voltage Vs.
Selon le mode de réalisation représenté en figure 4, l'électrode 33 du condensateur Cs est reliée à la borne 25 d'application de la tension Vs par une source de courant 41 commandable. La source 41 est commandée par un circuit de comparaison 42 (COMP Vcs/Vs) de la tension Vcs aux bornes du condensateur Cs par rapport à au moins un seuil fonction de la tension d'alimentation Vs. Le rôle du circuit 42 est d'activer la source de courant 41 uniquement pendant des périodes de démarrage où une précharge du condensateur Cs est requise. Cette fonctionnalité sera détaillée ultérieurement en relation avec la figure 5.According to the embodiment shown in FIG. 4, the electrode 33 of the capacitor Cs is connected to the terminal 25 for applying the voltage Vs by a controllable current source 41. The source 41 is controlled by a comparison circuit 42 (COMP Vcs / Vs) of the voltage Vcs across the capacitor Cs with respect to at least one threshold which is a function of the supply voltage Vs. The role of the circuit 42 is to activate the current source 41 only during start-up periods when a precharge of the capacitor Cs is required. This feature will be detailed later in connection with Figure 5.
Les commutateurs Ml, M2, M5 et M6 (ainsi que les commutateurs de l'autre partie du pont en H (M2, M4, figure 3)) sont commandés de façon synchronisée par un circuit 45 (CTRL) dont des sorties S sont connectées aux bornes de commande (grilles) des différents interrupteurs.The switches M1, M2, M5 and M6 (as well as the switches of the other part of the H-bridge (M2, M4, FIG. 3)) are controlled synchronously by a circuit 45 (CTRL) whose outputs S are connected to the control terminals (gates) of the different switches.
La figure 5 représente un exemple de schéma détaillé d'un étage de récupération d'énergie d'un écran plasma selon la présente invention. Les différents interrupteurs ont été représentés sous la forme de transistors MOS contrairement aux figures précédentes .FIG. 5 represents an example of a detailed diagram of an energy recovery stage of a plasma screen according to the present invention. The different switches have been represented in the form of MOS transistors in contrast to the previous figures.
Selon ce mode de réalisation, la source de courant commandable 41 est constituée d'un transistor M41 en série avec une résistance R41 entre la borne 25 et l'anode d'une diode D41 dont la cathode est reliée à l'électrode 33 du condensateur Cs. Une résistance de polarisation Rp relie la grille du transistor M41 à la borne 25 et une diode Zener DZ41 relie cette grille à l'anode de la diode D41 (l'anode de la diode DZ41 étant connectée à l'anode de la diode D41) . Une telle structure de source de courant est classique. La source 41 est rendue commandable au moyen d'un interrupteur (transistor MOS MlO) reliant l'anode des diodes DZ41 et D41 à la masse 26. Quand le transistor MlO est bloqué, la source 41 charge le condensateur Cs. Quand le transistor MlO est passant, la source de courant est connectée à la masse. La diode DZ41 fixe la valeur du courant en limitant la tension aux bornes de ses éléments résistifs. De plus, elle limite la tension grille-source du transistor MlO. D'autres structures de source de courant commandable sont envisageables.According to this embodiment, the controllable current source 41 consists of a transistor M41 in series with a resistor R41 between the terminal 25 and the anode of a diode D41 whose cathode is connected to the electrode 33 of the capacitor cs. A bias resistor Rp connects the gate of the transistor M41 to the terminal 25 and a Zener diode DZ41 connects this gate to the anode of the diode D41 (the anode of the diode DZ41 being connected to the anode of the diode D41) . Such a current source structure is conventional. The source 41 is made controllable by means of a switch (MOS transistor MlO) connecting the anode of the diodes DZ41 and D41 to the ground 26. When the transistor MlO is off, the source 41 charges the capacitor Cs. When the transistor MlO is on, the current source is connected to ground. The diode DZ41 sets the value of the current by limiting the voltage across its resistive elements. In addition, it limits the gate-source voltage of the transistor MlO. Other structures of controllable current source are conceivable.
La grille du transistor MlO est reliée en sortie d'un premier comparateur 421 du circuit 42 dont le rôle est de comparer une tension proportionnelle à la tension Vcs aux bornes du condensateur Cs par rapport à un seuil VB. Le seuil Vth du comparateur 421 est fixé par exemple, par un pont résistif constitué de deux résistances Rl et R2 alimentées en série par la tension Vs. La tension seuil Vth est appliquée, par exemple, à l'entrée inverseuse du comparateur 421 dont l'entrée non inverseuse reçoit une tension représentative de la tension aux bornes du condensateur Cs, obtenue par un deuxième pont résistif constitué de trois résistances R3, R4 et R5 en série entre la borne 33 et la masse. L'entrée non inverseuse du comparateur 421 est reliée au point milieu entre les résistances R4 et R5. La sortie du comparateur 421 est reliée à la grille du transistor MlO (le cas échéant, par l'intermédiaire du circuit 45). Les résistances Rl à R5 fixent un seuil VB = VsR2 (R3+R4+R5) / (R2+Rl)R5 pour la tension Vcs .The gate of the transistor MlO is connected at the output of a first comparator 421 of the circuit 42 whose role is to compare a voltage proportional to the voltage Vcs across the capacitor Cs with respect to a threshold VB. The threshold Vth of the comparator 421 is fixed for example by a resistive bridge consisting of two resistors R1 and R2 fed in series by the voltage Vs. The threshold voltage Vth is applied, for example, to the inverting input of the comparator 421 whose non-inverting input receives a voltage representative of the voltage at terminals of the capacitor Cs, obtained by a second resistive bridge consisting of three resistors R3, R4 and R5 in series between the terminal 33 and the ground. The non-inverting input of the comparator 421 is connected to the midpoint between the resistors R4 and R5. The output of the comparator 421 is connected to the gate of the transistor MlO (where appropriate, via the circuit 45). The resistors R1 to R5 set a threshold VB = VsR2 (R3 + R4 + R5) / (R2 + R1) R5 for the voltage Vcs.
Un deuxième comparateur 422 du circuit 42 compare la tension Vth fournie par le pont R1-R2 par rapport à une deuxième information représentative de la tension aux bornes du conden¬ sateur Cs différente de la première. Cette deuxième tension est prise au point milieu de l'association en série des résistances R3 et R4 reliées à l'entrée non inverseuse du comparateur 422 dont l'entrée inverseuse est reliée au point milieu entre les résistances Rl et R2. En fait, cela revient à comparer la tension Vcs par rapport à un seuil VA (=VsR2 (R3+R4+R5) / (R5+R4) (R2+R1) ) inférieur au seuil VB. La sortie du comparateur 422 est reliée au circuit 45 de commande des interrupteurs. Le rôle des deux seuils est de distinguer l'activation du circuit de récupération d'énergie (transistors M5, M6 et pont en H constitué des transistors Ml, M3 et M2, M4 représentés en pointillés) de l'activation ou désactivation de la source de courant 41 par la commande du transistor MlO. En figure 5, les diodes de blocage Dl et D2 ont été représentées entre les transistors M5, respectivement M6 et la diode D5 respectivement D6.A second comparator 422 of the circuit 42 compares the voltage Vth supplied by the bridge R1-R2 with respect to a second information representative of the voltage across the conden ¬ sateur Cs different from the first. This second voltage is taken at the midpoint of the series association of the resistors R3 and R4 connected to the non-inverting input of the comparator 422 whose inverting input is connected to the midpoint between the resistors R1 and R2. In fact, this amounts to comparing the voltage Vcs with respect to a threshold VA (= VsR2 (R3 + R4 + R5) / (R5 + R4) (R2 + R1)) lower than the threshold VB. The output of the comparator 422 is connected to the circuit 45 for controlling the switches. The role of the two thresholds is to distinguish the activation of the energy recovery circuit (transistors M5, M6 and H-bridge consisting of transistors Ml, M3 and M2, M4 shown in dashed lines) of the activation or deactivation of the source. current 41 by the control of the transistor MlO. In FIG. 5, the blocking diodes D1 and D2 have been represented between the transistors M5, respectively M6 and the diode D5 respectively D6.
La figure 6 illustre, par un chronogramme représentant la tension Vcs aux bornes du condensateur Cs en fonction du temps, le fonctionnement du circuit de la figure 5. Initialement (instant tO) le condensateur Cs est déchargé. Le circuit 42 fournit d'une part un signal de blocage du transistor MlO par le comparateur 421 tandis que le comparateur 422 donne l'information au bloc 45 que la tension Vcs est inférieure au premier seuil VA de sorte que les interrupteurs M5, M6, Ml et M3 sont tous ouverts. La tension Vcs aux bornes du condensateur croît sensiblement linéairement par la charge au moyen de la source de courant 41. A un instant tl où le niveau de tension Vcs atteint le seuil VA, le comparateur 422 commute et le bloc 45 de commande active la phase de récupération d'énergie. La source de courant 41 n'est pas encore inhibée de sorte que la tension aux bornes du condensateur Cs continue à croître.FIG. 6 illustrates, by a chronogram representing the voltage Vcs across the capacitor Cs as a function of time, the operation of the circuit of FIG. 5. Initially (instant t0) the capacitor Cs is discharged. The circuit 42 provides on the one hand a blocking signal of the transistor MlO by the comparator 421 while the comparator 422 gives the information to the block 45 that the voltage Vcs is lower than the first threshold VA so that the switches M5, M6, Ml and M3 are all open. The voltage Vc across the capacitor increases substantially linearly by the load by means of the current source 41. At a time t1 when the voltage level Vcs reaches the threshold VA, the comparator 422 switches and the control block 45 activates the phase energy recovery. The current source 41 is not yet inhibited so that the voltage across the capacitor Cs continues to increase.
De préférence, le seuil VA est choisi pour que la tension de recouvrement VRM des diodes D5 et D6 soit inférieure au niveau Vs-VA majoré des surtensions liées aux commutations.Preferably, the threshold VA is chosen so that the recovery voltage VRM of the diodes D5 and D6 is lower than the Vs-VA level plus the overvoltages related to the switching operations.
A un instant t2 où le seuil VB est atteint par la tension Vcs, le comparateur 421 ferme le transistor MlO, ce qui supprime la charge du condensateur Cs par la source de courant 41. Comme le fonctionnement du circuit de récupération d'énergie a démarré à l'instant tl, l'augmentation de la tension Vcs jusqu'au niveau Vs/2 (instant t3) se poursuit par les circuits résonants .At a time t2 when the threshold VB is reached by the voltage Vcs, the comparator 421 closes the transistor MlO, which eliminates the charge of the capacitor Cs by the current source 41. As the operation of the energy recovery circuit has started at time t1, the increase in voltage Vcs up to level Vs / 2 (time t3) is continued by the resonant circuits.
De préférence, la différence entre le seuil VB et le niveau Vs/2 est choisie en fonction des tolérances de fabri- cation des différents composants et notamment des dispersions technologiques lors de la fabrication des résistances des ponts diviseurs et des transistors . Le seuil VB doit être suffisamment inférieur à la valeur Vs/2 pour ne pas être franchi en cas de dispersion technologique entre les constituants. Cette plage de tolérance Toi est illustrée en figure 6 par des pointillés. Avec ces notations, VB <Vs/2-Tol/2.Preferably, the difference between the threshold VB and the level Vs / 2 is chosen as a function of the manufacturing tolerances of the various components and in particular of the technological dispersions during the manufacture of the resistances of the dividing bridges and the transistors. The threshold VB must be sufficiently lower than the value Vs / 2 so as not to be crossed in case of technological dispersion between the constituents. This tolerance range You is illustrated in FIG. 6 by dashed lines. With these notations, VB <Vs / 2-Tol / 2.
Les figures 7A à 7K illustrent le fonctionnement d'un étage de récupération d'énergie une fois la précharge du conden¬ sateur Cs obtenue. Ces chronogrammes illustrent respectivement des exemples d'allures des signaux de commande (état de ferme¬ ture ou d'ouverture) des transistors Ml, M2, M3, M4, M5, M6, M7, M8 et MlO (et MlO') ainsi que les allures correspondantes de la tension Vp aux bornes de la capacité équivalente Cp de l'écran plasma et des courants IL et IL' dans les inductances des étages de récupération d'énergie. La précharge illustrée par la figure 6 intervient avant l'instant tl d'activation de l'étage auquel, par exemple, le transistor M6 (figure 7F) est commuté à l'état passant, le transistor M4 (figure 7D) étant déjà passant et le transistor MlO restant bloqué jusqu'à l'instant t2 (seuil VA) légèrement postérieur à l'instant tl. A partir de l'instant tl, le courant7A to 7K illustrate operation of an energy recovery stage once the preload conden ¬ sateur Cs obtained. These timing diagrams respectively illustrate examples of the behavior of the control signals (state of closure ¬ ture or opening) of the transistors Ml, M2, M3, M4, M5, M6, M7, M8 and MlO (and MlO ') as well as the corresponding paces of the voltage Vp across the equivalent capacitance Cp of the plasma screen and the currents IL and IL 'in the inductances of the energy recovery stages. The precharging illustrated in FIG. 6 occurs before the instant of activation of the stage at which, for example, the transistor M6 (FIG. 7F) is switched on, the transistor M4 (FIG. 7D) being already on. and the transistor MlO remaining blocked until time t2 (VA threshold) slightly later than time tl. From the moment tl, the current
(figure 7K) dans l'élément inductif L charge le condensateur équivalent Cp (tension Vp, figure 7J) jusqu'à atteindre un niveau Vs (en négligeant les chutes de tension dans les composants à l'état passant) à un instant t4. A cet instant t4, la diode D5 se bloque, et on assiste à un phénomène de recouvrement qui provoque une augmentation du courant dans l'inductance L. Cette énergie est évacuée par les diodes D6 et D2 en un temps (Δt, figure 7K) qui est fixé par la tension aux bornes de l'inductance. La durée Δt doit bien entendu être inférieure à l'intervalle t5-t4. Le blocage du transistor M6 est illustré à l'instant t4, sachant que sa commande peut être légèrement retardée grâce au blocage automatique de la diode D5. Le transistor Ml (figure 7A) est rendu passant à partir de l'instant t4. Vers la fin de la phase de récupération d'énergie, le transistor M5 est rendu passant à un instant t5 (figure 7E) en même temps (ou légèrement après) que le transistor Ml est bloqué. On assiste alors un fonctionnement du circuit résonant dans l ' autre sens par une décharge de la capacité Cp jusqu ' à un instant t6 où la disparition du courant IL dans l'inductance L provoque le blocage de la diode D6 et un phénomène de recou¬ vrement opposé à celui de la diode D5. Les transistors M4 et M5 sont bloqués à partir de l'instant t6 et le transistor M3 (figure 7C) est rendu passant à cet instant t6 (en pratique, légèrement après le blocage du transistor M4) .(FIG. 7K) in the inductive element L charges the equivalent capacitor Cp (voltage Vp, FIG. 7J) until a level Vs (neglecting the voltage drops in the components in the on state) is reached at a time t4. At this instant t4, the diode D5 is blocked, and there is a phenomenon of recovery which causes an increase of the current in the inductance L. This energy is discharged by the diodes D6 and D2 in a time (Δt, Figure 7K) which is fixed by the voltage across the inductance. The duration Δt must of course be less than the interval t5-t4. The blocking of the transistor M6 is illustrated at time t4, knowing that its control can be slightly delayed by the automatic blocking of the diode D5. The transistor M1 (FIG. 7A) is turned on from the instant t4. Towards the end of the energy recovery phase, transistor M5 is turned on at time t5 (FIG. 7E) at the same time (or slightly thereafter) as transistor M1 is off. There is then an operation of the resonant circuit in the other direction by a discharge of the capacitance Cp up to a time t6 where the disappearance of the current IL in the inductor L causes the blocking diode D6 and a phenomenon of recou ¬ opposite to that of diode D5. The transistors M4 and M5 are blocked from the instant t6 and the transistor M3 (FIG. 7C) is turned on at this instant t6 (in practice, slightly after the blocking of the transistor M4).
A partir de l'instant tθ', le fonctionnement décrit ci-dessus en relation avec l'étage de récupération d'énergie côté électrodes de balayage se reproduit sur l'étage de récupération d'énergie côté électrodes d'entretien par la deuxième branche du pont en H. Ce fonctionnement est illustré en partie droite des chronogrammes des figures 7A à 7K (instants tθ', tl', t2', t4', t5' et t6').From the instant tθ ', the operation described above in relation to the energy recovery stage on the scanning electrodes side is reproduced on the maintenance electrode side energy recovery stage by the second branch. of the H-bridge. This operation is illustrated in right part of the timing diagrams of Figures 7A to 7K (times t0 ', tl', t2 ', t4', t5 'and t6').
Si entre l'instant t6 et le début tθ' de la phase de récupération d'énergie côté électrodes d'entretien, la tension aux bornes du condensateur Cs chute de trop, on assiste à une nouvelle précharge de celui-ci par la source de courant 41.If between the time t6 and the start tθ 'of the energy recovery phase on the maintenance electrode side, the voltage across the capacitor Cs drops too much, it is again preloaded by the source of the capacitor Cs. current 41.
Un avantage de la présente invention est que la tension vue par les transistors M5 et M6 est désormais limitée à la moitié de la tension d'alimentation (majorée des surtensions de commutation) .An advantage of the present invention is that the voltage seen by transistors M5 and M6 is now limited to half of the supply voltage (plus switching overvoltages).
Un autre avantage de la présente invention est qu'en cas de dissymétrie due aux différences d'impédances entre les interrupteurs M5, M6, cette dissymétrie est compensée par le système de précharge. Un autre avantage de la présente invention est que les seuils s'adaptent à d'éventuelles variations de la tension d'alimentation Vs.Another advantage of the present invention is that in case of asymmetry due to impedance differences between the switches M5, M6, this asymmetry is compensated by the precharge system. Another advantage of the present invention is that the thresholds adapt to possible variations of the supply voltage Vs.
La figure 8 représente un mode de réalisation d'un étage 43 de récupération d'énergie selon un deuxième aspect de l'invention. Pour simplifier, les éléments de précharge du condensateur Cs au point 33 n'ont pas été représentés.Figure 8 shows an embodiment of a stage 43 of energy recovery according to a second aspect of the invention. For simplicity, the precharge elements of capacitor Cs at point 33 have not been shown.
On retrouve la même structure que dans les étages de récupération d'énergie précédents.We find the same structure as in previous energy recovery stages.
Selon cet aspect de l'invention, une première diode Zener DZl est intercalée entre la diode Dl de blocage (dont l'anode est connectée à l'anode de la diode D5) et la borne 25 d'application de la tension d'alimentation Vs. Une deuxième diode Zener DZ2 est intercalée entre la cathode de la diode D6 et celle de la diode de blocage D2 reliée à la masse 26. Le rôle des diodes Zener DZl et DZ2 est de fixer une tension de blocage supérieure à celle apportée par les diodes Dl et D2.According to this aspect of the invention, a first zener diode DZ1 is interposed between the blocking diode D1 (whose anode is connected to the anode of the diode D5) and the terminal 25 for applying the supply voltage. Vs. A second Zener diode DZ2 is interposed between the cathode of the diode D6 and that of the blocking diode D2 connected to the ground 26. The role of the Zener diodes DZ1 and DZ2 is to set a blocking voltage higher than that provided by the diodes D1 and D2.
A la différence du circuit de la figure 5 où la circulation du courant lors de la phase de recouvrement (après l'instant t6, figures 7A à 7K) passe (pour les phases négatives) par la diode D6, l'inductance L, le transistor M3 et la diode D2, ce courant est selon le mode de réalisation de la figure 8 rebouclé par la diode D2 et la diode DZ2 sans parcourir la diode D6. Le même fonctionnement se produit lors des phases positives par la diode DZl.In contrast to the circuit of FIG. 5 where the flow of the current during the recovery phase (after time t6, FIGS. 7A to 7K) passes (for the negative phases) by the diode D6, the inductance L, the transistor M3 and the diode D2, this current is according to the embodiment of FIG. 8 looped by the diode D2 and the diode DZ2 without going through the diode D6. The same operation occurs during the positive phases by the diode DZ1.
Un avantage qu ' il y a à fixer la tension de blocage au moyen d'une diode Zener DZl ou DZ2 est que cela permet de réduire le temps Δt d'évacuation de l'énergie accumulée dans l'inductance L suite aux blocages respectifs des diodes D5 et D6. Cet avantage est particulièrement sensible avec l'augmentation des fréquences de fonctionnement des écrans qui réduit les intervalles disponibles .One advantage of setting the clamping voltage by means of a Zener diode DZ1 or DZ2 is that it makes it possible to reduce the time Δt of evacuation of the energy accumulated in the inductance L following the respective blockages of the diodes D5 and D6. This advantage is particularly noticeable with the increase in operating frequencies of the screens which reduces the available intervals.
Bien entendu, la présente invention est susceptible de diverses variantes et modifications qui apparaîtront à l'homme de l'art. Par exemple, les interrupteurs décrits comme étant des transistors MOS peuvent être remplacés par des transistors bipolaires à grille isolé (IGBT) . De plus, les dimensions à donner aux différents constituants du circuit de démarrage de l'invention sont à la portée de l'homme du métier à partir des indications fonctionnelles données ci-dessus. En outre, l'adap¬ tation des circuits de commande généralement numériques de l'écran plasma pour tenir compte des seuils détectés par l'invention est également à la portée de l'homme du métier en utilisant des outils classiques. Of course, the present invention is susceptible of various variations and modifications which will be apparent to those skilled in the art. For example, the switches described as being MOS transistors may be replaced by insulated gate bipolar transistors (IGBTs). In addition, the dimensions to be given to the various constituents of the starting circuit of the invention are within the abilities of those skilled in the art from the functional indications given above. In addition, the adap ¬ tation generally digital control circuits of the plasma display to reflect the thresholds detected by the invention is also within the reach of the skilled person using conventional tools.

Claims

REVENDICATIONS
1. Procédé de commande d'un étage de récupération d'énergie d'un écran plasma comportant un circuit résonant d'au moins un élément inductif (L) et d'un élément capacitif (Cs), caractérisé en ce qu'il comporte au moins une étape de précharge de l'élément capacitif à la moitié d'une tension d'alimentation (Vs) de l'écran.1. A method for controlling a power recovery stage of a plasma screen comprising a resonant circuit of at least one inductive element (L) and a capacitive element (Cs), characterized in that it comprises at least one step of precharging the capacitive element to half of a supply voltage (Vs) of the screen.
2. Procédé selon la revendication 1, dans lequel des commutateurs d'activation de l'étage de récupération d'énergie sont inhibés pendant l'étape de précharge, au moins jusqu'à ce que la tension aux bornes de l'élément capacitif (Cs) ait atteint un premier seuil (VA) fonction de la tension d ' alimentation .The method according to claim 1, wherein activation switches of the energy recovery stage are inhibited during the precharging step, at least until the voltage across the capacitive element ( Cs) has reached a first threshold (VA) depending on the supply voltage.
3. Procédé selon la revendication 2, dans lequel l'étape de précharge de l'élément capacitif (Cs) est inhibée lorsque la tension à ses bornes atteint un deuxième seuil (VB) fonction de la tension d'alimentation supérieur au premier.3. Method according to claim 2, wherein the step of precharging the capacitive element (Cs) is inhibited when the voltage across its terminals reaches a second threshold (VB) function of the supply voltage greater than the first.
4. Procédé selon l'une quelconque des revendications 1 à 3, dans lequel la précharge de l'élément capacitif (Cs) est obtenue au moyen d'une source de courant commandable (41) . 4. Method according to any one of claims 1 to 3, wherein the precharge of the capacitive element (Cs) is obtained by means of a controllable current source (41).
5. Circuit de commande d'un étage de récupération d'énergie d'un écran plasma ayant un circuit résonant d'au moins un élément inductif (L) et d'au moins un élément capacitif (Cs), caractérisé en ce qu'il comporte : une source de courant commandable (41) entre une borne (25) d'application d'une tension d'alimentation (Vs) et l'élément capacitif ; et au moins un premier comparateur (421) de comparaison de la tension aux bornes de l'élément capacitif par rapport à un premier seuil (VA) pour activer des éléments de commutation du circuit de récupération.5. Circuit for controlling a power recovery stage of a plasma screen having a resonant circuit of at least one inductive element (L) and at least one capacitive element (Cs), characterized in that it comprises: a controllable current source (41) between a terminal (25) for applying a supply voltage (Vs) and the capacitive element; and at least one first comparator (421) for comparing the voltage across the capacitive element with respect to a first threshold (VA) to activate switching elements of the recovery circuit.
6. Circuit selon la revendication 5, dans lequel un deuxième comparateur (421) compare la tension aux bornes de l'élément capacitif (Cs) par rapport à un deuxième seuil (VB) supérieur au premier pour commander ladite source de courant (41) .6. Circuit according to claim 5, wherein a second comparator (421) compares the voltage across the capacitive element (Cs) with respect to a second threshold (VB). greater than the first for controlling said current source (41).
7. Etage de récupération d'énergie d'un écran plasma comportant un circuit résonant d'au moins un condensateur (Cs) en série avec un interrupteur bidirectionnel (43) et au moins un élément inductif (L) entre le point milieu d'une première branche d'un pont en H et la masse, ledit point milieu étant relié à des premières électrodes de l'écran et l'interrupteur bidirectionnel étant constitué d'une association en anti- parallèle de deux interrupteurs (M5, M6) chacun en série avec une diode (D5, D6) , caractérisé en ce qu'il comporte un circuit selon la revendication 5 ou 6.7. Stage of energy recovery of a plasma screen comprising a resonant circuit of at least one capacitor (Cs) in series with a bidirectional switch (43) and at least one inductive element (L) between the midpoint of a first branch of an H-bridge and the ground, said midpoint being connected to first electrodes of the screen and the bidirectional switch consisting of an anti-parallel association of two switches (M5, M6) each in series with a diode (D5, D6), characterized in that it comprises a circuit according to claim 5 or 6.
8. Etage selon la revendication 7, comportant deux circuits de blocage comprenant chacun une diode Zener (DZl, DZ2) en série avec une diode (Dl, D2) entre la borne de l'inductance (L) reliée à l'interrupteur bidirectionnel et deux bornes (25, 26) d'application de la tension d'alimentation.8. The stage according to claim 7, comprising two blocking circuits each comprising a Zener diode (DZ1, DZ2) in series with a diode (D1, D2) between the terminal of the inductor (L) connected to the bidirectional switch and two terminals (25, 26) for applying the supply voltage.
9. Ecran plasma comportant au moins un étage de récupération d'énergie conforme à l'une quelconque des reven- dications 7 et 8. 9. A plasma screen having at least one energy recovery stage according to any one of claims 7 and 8.
EP06831351A 2005-11-18 2006-11-17 Controlling an energy recovery stage of a plasma screen Withdrawn EP1949354A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0553511A FR2893753A1 (en) 2005-11-18 2005-11-18 CONTROLLING A ENERGY RECOVERY STAGE OF A PLASMA DISPLAY
PCT/FR2006/051189 WO2007057616A2 (en) 2005-11-18 2006-11-17 Controlling an energy recovery stage of a plasma screen

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EP1949354A2 true EP1949354A2 (en) 2008-07-30

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DE102007036973A1 (en) * 2007-02-24 2008-09-04 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. A pixel cell, a method of operating a pixel cell, a method of determining a position of a maximum of an envelope of an analog amplitude modulated signal, a device for determining a charge amount, apparatus and method for determining an amount of charge on a capacitive element, apparatus and method, and setting a circuit node a predetermined voltage, apparatus and method for charge-based analog / digital conversion and apparatus and method for charge-based signal processing
US11705167B2 (en) * 2021-03-31 2023-07-18 Changxin Memory Technologies, Inc. Memory circuit, method and device for controlling pre-charging of memory

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JP3201603B1 (en) 1999-06-30 2001-08-27 富士通株式会社 Driving device, driving method, and driving circuit for plasma display panel
KR100416081B1 (en) * 1999-07-29 2004-01-31 삼성에스디아이 주식회사 Apparatus for detecting over-current in Plasma Display Panel
US6396674B1 (en) * 2000-04-11 2002-05-28 Ford Global Technologies, Inc. System and method for monitoring the operation of a power converter
JP2004133406A (en) * 2002-10-11 2004-04-30 Samsung Sdi Co Ltd Apparatus and method for driving plasma display panel
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WO2007057616A3 (en) 2007-08-23
WO2007057616A2 (en) 2007-05-24
US20090141014A1 (en) 2009-06-04
US8339388B2 (en) 2012-12-25
FR2893753A1 (en) 2007-05-25

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