EP1941377A2 - Interface de noeud de reseau entre un microcontroleur et un module de communication flexray, noeud de reseau flexray et procede de transmission d'ambassades par l'intermediaire d'une telle interface - Google Patents

Interface de noeud de reseau entre un microcontroleur et un module de communication flexray, noeud de reseau flexray et procede de transmission d'ambassades par l'intermediaire d'une telle interface

Info

Publication number
EP1941377A2
EP1941377A2 EP06807000A EP06807000A EP1941377A2 EP 1941377 A2 EP1941377 A2 EP 1941377A2 EP 06807000 A EP06807000 A EP 06807000A EP 06807000 A EP06807000 A EP 06807000A EP 1941377 A2 EP1941377 A2 EP 1941377A2
Authority
EP
European Patent Office
Prior art keywords
memory
data
message
flexray
state machine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06807000A
Other languages
German (de)
English (en)
Inventor
Josef Newald
Markus Ihle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP1941377A2 publication Critical patent/EP1941377A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40208—Bus networks characterized by the use of a particular bus standard
    • H04L2012/40241—Flexray

Definitions

  • the present invention relates to a subscriber interface between a FlexRay communication module which is connected to a FlexRay
  • Communication link is connected, via which messages are transmitted, and which comprises a message memory for buffering messages from the FlexRay communication link or for the FlexRay communication link, and a FlexRay communication block associated with the microcontroller, a microprocessor and a direct memory access (DMA) controller for a data exchange with the message memory.
  • a message memory for buffering messages from the FlexRay communication link or for the FlexRay communication link
  • a FlexRay communication block associated with the microcontroller, a microprocessor and a direct memory access (DMA) controller for a data exchange with the message memory.
  • DMA direct memory access
  • the invention also relates to a FlexRay subscriber who has a microcontroller, a FlexRay communication module, which is connected to a FlexRay device.
  • the Communication connection is connected, via which messages are transmitted, and has a subscriber interface between the microcontroller and the communication module.
  • the microcontroller includes a microprocessor and a direct memory access (DMA) controller.
  • the communication module comprises a message memory for temporary storage messages from the FlexRay communications link or for the FlexRay communications link.
  • the present invention also relates to a method for data transmission between a message memory of a FlexRay device.
  • Communication module which is connected to a FlexRay communication link, via which messages are transmitted, and a direct memory access (DMA) controller of a microcontroller.
  • DMA direct memory access
  • the FlexRay protocol defines a fast, deterministic and fault-tolerant bus system, especially for use in a motor vehicle.
  • the data transmission according to the FlexRay protocol is carried out according to a Time Division Multiple Access (TDMA) method.
  • TDMA Time Division Multiple Access
  • the data transmission via the communication connection is carried out in regularly recurring transmission cycles, each of which is divided into several data frames, which are also referred to as time slots.
  • the participants or the messages to be transmitted are assigned fixed time slots in which they have exclusive access to the communication connection.
  • the time slots are repeated in the specified transmission cycles, so that the time at which a message is transmitted over the bus can be accurately predicted and the bus access is deterministic.
  • FlexRay divides the transmission cycle, which can also be referred to as cycle or bus cycle, into a static and a dynamic part.
  • the fixed time slots are located in the static part at the beginning of a bus cycle.
  • the time slots are allocated dynamically.
  • exclusive bus access is now only possible for a short time, for one or more so-called minislots. Only if a bus access occurs within a minislot, the time slot is extended by the required time. Thus, bandwidth is only consumed when it is actually needed.
  • FlexRay communicates via two physically separate lines of the communication link at a maximum data rate of 10 MBiVs (10 MBaud). Every 5 ms, and even every 2.5 ms in some communication systems, one bus cycle is completed.
  • the two channels correspond to the physical layer, in particular the OSI (Open System Architecture) layer model.
  • the two channels are mainly used for the redundant and thus fault-tolerant transmission of messages, but can also transmit different messages, which would then double the data rate. FlexRay can also be operated at lower data rates.
  • the participants or the distributed components in the communication network need a common time base, the so-called global time.
  • clock synchronization synchronization messages are transmitted in the static part of the cycle. Using a special algorithm according to the FlexRay specification, the local time of a subscriber is corrected in such a way that all local clocks synchronize to one global clock.
  • a FlexRay device which can also be referred to as a FlexRay network node or host, contains a participant or host processor, a FlexRay or communication controller, and a bus guardian in bus monitoring.
  • the user processor delivers and processes the data that is transmitted via the FlexRay communication controller and the FlexRay communication connection.
  • messages or message objects can be stored with eg. For example, up to 254 bytes of data can be configured.
  • an interface module consisting of two parts, wherein the one component independent of the subscriber and the other sub-module is subscriber-specific.
  • the subscriber-specific sub-module which is also referred to as Customer CPU Interface (CIF) connects a customer-specific subscriber in the form of a subscriber-specific host CPU to the FlexRay communication module.
  • the subscriber-independent submodule also referred to as the Generic CPU Interface (GIF) represents a generic, that is to say general, CPU interface, via which different customer-specific subordinate components, in other words Customer CPU Interfaces (CIFs), can be used. Connect CPUs to the FlexRay communication block.
  • the interface can be flexibly adapted by simple variation of the subscriber-specific sub-module to any trained or kind of participants.
  • the sub-blocks can also be implemented within the one interface block in each case in software, ie each sub-module as a software function.
  • the state machine in the FlexRay communication block may be hardwired into hardware.
  • the sequences can also be hardwired into hardware.
  • the state machine can also be freely programmable in the communication module via the subscriber interface by the subscriber.
  • the information preferably contains the access type and / or the access type and / or the access address and / or the data size and / or control information.
  • the message memory of the FlexRay communication module is preferably designed as a single-ported RAM (Random Access Memory).
  • This RAM memory stores the messages or message objects, ie the actual user data, together with configuration and status data.
  • the exact structure of the message memory of the known communication module can be found in the cited document DE 10 2005 034 744.
  • a FlexRay subscriber has to coordinate and control the data transfer between the message memory of the FlexRay communication blocks and the subscriber via a microprocessor and a DMA controller.
  • the messages in the message memory are not stored sequentially, ie consecutively, but are specifically distributed to specific areas of the message memory.
  • the DMA controller can only access data from contiguous areas of the message memory. This has the consequence that the DMA controller for data transmission between message memory and participants in the prior art has to be set up and started several times. Each setup and startup of the DMA controller requires the transmission of a significant amount of data in configuration, coordination, and control parameters.
  • the end of the data transfer is communicated to the microprocessor, for example by means of polling by the microprocessor or by an interrupt command triggered by the DMA controller. Both require significant resources (computing and storage capacity) in the microprocessor. It is therefore worthwhile in the prior art hardly or only in exceptional cases to program the DMA controller for data transmission. In summary, the connection of the DMA controller to the FlexRay communication module in the prior art is not optimal.
  • the present invention is therefore based on the object to provide a way to better connect the DMA controller of the microcontroller to the FlexRay communication module to allow faster and especially resource-saving data transfer between the message memory of the communication module and the DMA controller ,
  • the subscriber interface has a state machine, which after configuration by the microprocessor of the microcontroller, a data transfer between the Message memory of the FlexRay communication block and the DMA controller independently coordinates and controls.
  • the interposition of a state machine between the microcontroller of a FlexRay subscriber and a FlexRay communication module of the subscriber is proposed, which changes the subscriber interface in such a way that it pays to set up and start the DMA controller of the microcontroller.
  • the state machine ensures that the data or messages to be transmitted are presented in an optimized manner to the DMA controller in such a way that it can also transmit larger amounts of data or multiple messages with a single call to the DMA controller. According to the invention, so to speak, a single access from the previously required many small accesses is composed.
  • the microcontroller of the participant's microcontroller first configures the state machine and tells it to read or write, which messages (message numbers) to transmit, and how long the messages to be transmitted are. With the help of this information, the state machine then accesses the FlexRay communication module in such a way that the desired data or messages between the message memory and the DMA controller are transmitted in read or write mode. To a certain extent, the state machine provides the intelligence of the DMA controller, which it requires for more complex access to larger amounts of data, in particular multiple messages, possibly even in distributed address areas of the message memory.
  • the state machine generates a virtual contiguous address space, making the use of the DMA controller makes sense, since the number of data to be transmitted (to set up the DMA controller) and the number of interrupts (at the end of a DMA controller cycle) is significantly reduced.
  • the DMA controller reads from or writes to the same
  • the DMA controller always accesses an output buffer of the FlexRay communication module for reading data and always an input buffer for writing data.
  • the subscriber interface has configuration and status registers to which the microcontroller of the microcontroller has access to configure the state machine.
  • the microprocessor thus configures the state machine by writing appropriate configuration parameters into the configuration and status registers of the subscriber interface.
  • the registers can be implemented as flip-flops or be part of a large memory, for example a random access memory (RAM), ie RAM.
  • the configuration parameters relate, for example, to the following information: read or write data transmission;
  • the subscriber interface has a sequence memory in which references to specific messages stored in the message memory and information about the messages are stored, wherein the state machine for coordinating and controlling the data transfer calls entries of the sequence memory.
  • the sequence memory is preferably designed as a RAM and comprises a plurality, preferably 128, fields with sequence entries.
  • the sequence entries comprise, for example, an identifier (eg a number) of the sequence entry, an identifier or a reference (eg a buffer number) to one or more messages (so-called buffers) of the message memory or the buffer memory, and the size of the message (the buffer).
  • the various sequence entries can be called by the state machine according to specifications of the microprocessor targeted.
  • the sequence entries can be called up unchanged in the saved form or in adapted form. To call in an adapted form, the call of the sequence entry includes certain parameter values for adapting variable parameters of the sequence entry.
  • sequence entries in the sequence memory preferably relate to frequently occurring transmission sequences, which are stored in advance and are called when needed. In this way, by calling a single sequence or subsequence (one or more sequence entries) a large data transfer between the message memory and the DMA controller can be triggered.
  • the configuration parameters that are transferred from the microprocessor of the microcontroller to the configuration and status registers at the beginning of the data transfer may also include an identifier (eg, the numbers) of one or more sequence entries received from the state machine in the frame the data transfer to be called.
  • the messages to be transmitted between the message memory and the subscriber each comprise a header segment, in particular with configuration data and control data, and a data segment with user data
  • the state machine comprising the Data transfer between the message memory and the DMA controller controls such that for each message the header segment is read in front of the data segment.
  • the state machine preferably controls the data transmission between the message memory and the DMA controller in such a way that the data contained in the header segment is evaluated before the data segment is read in and the reading of the data segment is controlled as a function of the result of the evaluation of the data of the header segment.
  • the status is read. In this way, with empty data in the data segment, it is possible to prevent the entire data segment from being transmitted. Rather, those address ranges of the data segment can be selected which contain payload data (so-called payload); the address areas with empty data are ignored during transmission and simply skipped. In this way, the transmission rate can be increased.
  • the FlexRay communication module has at least one buffer memory, preferably at least one input buffer memory and at least one output buffer memory, for temporarily storing data to be transmitted between the message memory of the communication module and the DMA controller, preferably for buffering at least a message stored in the message memory, the state machine transmitting the data between the message
  • the at least one buffer memory is arranged between the message memory of the FlexRay communication module and the state machine of the subscriber interface.
  • an output buffer is provided for read access to the message memory and an input buffer for write access.
  • the at least one buffer memory comprises a partial buffer memory and a shadow memory associated with the partial buffer memory, wherein the state machine coordinates and controls the data transmission such that writing or reading to the partial buffer memory and the shadow memory takes place alternately.
  • the FlexRay communication module has the control register associated with at least one buffer memory, to which the state machine for coordinating and controlling the
  • Data transfer between the message memory and the at least one buffer has access.
  • About the control register can be communicated to the communication module, whether new data for transmission concern (and should be transferred) and to which address in the message memory they are stored or from which address they are to be picked.
  • the subscriber interface be a state machine, which, after being configured by the microprocessor of the microcontroller, autonomously coordinates and controls data transmission between the message memory of the FlexRay communication module and the DMA controller.
  • a state machine which is arranged as part of a subscriber interface between the microcontroller and the FlexRay communication module, be configured by a microprocessor of the microcontroller and the Data transfer after the configuration of the state machine is independently coordinated and controlled.
  • Microcontroller configuration parameters are stored in the configuration and status register of the subscriber interface.
  • references to certain messages stored in the message memory and information about the messages are stored in a sequence memory of the subscriber interface, wherein entries of the sequence memory are called by the state machine for coordination and control of the data transmission.
  • the FlexRay communication module has at least one buffer memory, preferably at least one input buffer memory and at least one output buffer memory, for buffering data to be transferred between the message memory of the communication module and the DMA controller, preferably for buffering at least one message stored in the message memory, wherein coordination and control parameters are stored for controlling and coordinating the data transmission from the state machine in the control registers associated with at least one buffer memory.
  • FIG. 1 shows a communication module and its connection to a communication connection and a communication or host participants of a FlexRay communication system in a schematic representation
  • FIG. 2 shows a specific embodiment of the communication module of Figure 1 and its connection in detail
  • Figure 3 shows the structure of a message memory of the communication module of Figure 2;
  • Figure 4 to 6 the architecture and the process of a data access in the direction from the subscriber to the message memory in a schematic representation
  • FIGS. 7 to 9 show the architecture and the process of data access in the direction from the message memory to the subscriber;
  • Figure 10 is a schematic representation of the structure of a message manager and finite state machines contained therein;
  • FIG. 11 shows components of the communication module from FIGS. 1 and 2 as well as the subscriber and the corresponding data paths controlled by the message administrator in a schematic representation
  • FIG. 12 shows the access distribution to the message memory with reference to the data paths in FIG. 11;
  • FIG. 13 shows a subscriber interface according to the invention with a
  • FIG. 14 shows the state machine between the FlexRay
  • Figure 15 shows the waveforms in the context of a read via the subscriber interface according to the invention.
  • Figure 16 shows the waveforms in the context of a read via the subscriber interface according to the invention.
  • a FlexRay communication module 100 for connecting a subscriber or host 102 to a FlexRay Communication link 101, ie the physical layer of the FlexRay.
  • This is formed, for example, as a FlexRay data bus, which preferably has two transmission lines.
  • the FlexRay communication module 100 is connected via a connection 107 to the subscriber or subscriber processor 102 and via a connection 106 to the communication connection 101.
  • a first arrangement 105 serves for storing, in particular clipboard, at least part of the messages to be transmitted.
  • a second arrangement 104 is connected via the connections 107 and 108.
  • a third arrangement 103 is connected between the communication link 101 and the first arrangement 105 via the connections 106 and 109, whereby a very flexible inputting and outputting of data as part of messages, in particular FlexRay messages in and out of the first arrangement 105 with warranty Data integrity at optimal speed can be achieved.
  • the second arrangement 104 contains an input buffer or input buffer 201 (input buffer IBF), an output buffer or output buffer 202 (Output Buffer OBF) and an interface module consisting of two parts 203 and 204, wherein one sub-module 203 is subscriber-independent and the second sub-module 204 is subscriber-specific.
  • the subscriber-specific sub-component 204 (Customer CPU Interface CIF) connects a subscriber-specific host CPU 102, that is to say a customer-specific sub-module 102.
  • a bidirectional data line 216, an address line 217 and a control input 218 is provided. Also provided with 219 is an interrupt or interrupt output.
  • the subscriber-specific sub-module 204 is connected to a subscriber-independent sub-module 203 (Generic CPU Interface, GIF), ie the FlexRay communication module or the FlexRay IP module has a generic, ie general, CPU interface 203 to which corresponding subscriber-specific sub-blocks 204, so customer CPU interfaces CIF connect a large number of different customer-specific host CPUs 102.
  • GIF Generic CPU Interface
  • the input buffer or input buffer 201 and the output buffer or output buffer 202 may be formed in a common memory device or in separate memory devices.
  • the input buffer memory 201 serves for the buffering of messages for transmission to a message memory 300.
  • the input buffer module 201 is preferably designed such that it contains two complete messages each comprising a header segment or header segment, in particular with configuration data and a data segment or payload Can save segment.
  • the input buffer 201 is formed in two parts (partial buffer memory and shadow memory), whereby the transmission between subscriber CPU 102 and message memory 300 can be accelerated by alternately writing the two parts of the input buffer memory or by changing access.
  • the output buffer 202 (output buffer 202) is used for buffering messages for transmission from the message memory 300 to the subscriber CPU 102.
  • the output buffer 202 is also designed to: that two complete messages consisting of header segment, in particular with configuration data and data segment, ie payload segment, can be stored.
  • the output buffer 202 is divided into two parts, a partial buffer memory and a shadow memory, which can accelerate the transmission between participants or host CPU 102 and message memory 300 here by alternately reading the two parts, the transmission or by access change.
  • This second assembly 104 consisting of the blocks 201 to 204 is connected to the first assembly 105 as shown.
  • the arrangement 105 consists of a message handler 200 (message handler MHD) and a message memory 300 (message RAM).
  • the message manager 200 controls the data transfer between the input buffer 201 and the output buffer 202 and the message memory 300. Likewise, it controls the data transfer in the other direction via the third device 103.
  • the message memory 300 is preferably single-ported RAM executed. This RAM memory stores the messages or embassy objects, ie the actual data, together with configuration and status data. The exact structure of the message memory 300 is shown in more detail in FIG.
  • the third arrangement 103 consists of the blocks 205 to 208. According to the two channels of the FlexRay Physical Layer, this arrangement 103 is divided into two data paths with two data directions each. This is illustrated by the links 213 and 214, which show the two data directions for channel A with RxA and TxA for receive (RxA) and transmit (TxA) and for channel B with RxB and TxB. Connection 215 indicates an optional bidirectional control input.
  • the connection of the third arrangement 103 takes place via a first buffer memory 205 for channel B and a second buffer memory 206 for channel A.
  • These two buffer memories Transient Buffer RAMs: RAM A and RAM B serve as temporary storage for the data transfer from or to the first arrangement 105.
  • these two buffer memories 205 and 206 are connected to an interface module 207 and 208, respectively, containing the FlexRay protocol controller or bus protocol - Controller consisting of a transmit / receive shift register and the FlexRay protocol finite state machine, included.
  • the two buffer memories 205 and 206 thus serve as temporary storage for the data transfer between the shift registers of the interface modules or FlexRay protocol controllers 207 and 208 and the message memory 300.
  • the data fields, ie the payload segment or data segment are advantageously provided by each buffer memory 205 or 206 stored in two FlexRay messages.
  • GTU Global Time Unit
  • SUC General System Control
  • Block 211 shows the network and error management (Network and Error Management NEM) as described in FlexRay protocol specification v2.0.
  • block 212 shows the interrupt control (INT) managing the status and error interrupt flags and the interrupt outputs 219 to the subscriber CPU 102 controls or controls.
  • Block 212 also includes an absolute and a relative timer for generating the time interrupts or timer interrupts.
  • message objects or messages can be configured with up to 254 data bytes.
  • the message memory 300 is in particular a message RAM memory (Message RAM), which z. B. can save up to a maximum of 128 message objects. All functions that affect the treatment or administration of the messages themselves are implemented by the message handler or message handler 200. These are z.
  • Message RAM message RAM
  • All functions that affect the treatment or administration of the messages themselves are implemented by the message handler or message handler 200. These are z.
  • As the acceptance filtering transfer of messages between the two FlexRay protocol controller blocks 207 and 208 and the message memory 300, so the message RAM and the control of the transmission order and the provision of configuration data or status data.
  • An external CPU that is to say an external processor of the subscriber processor 102, can access the registers of the FlexRay communication module 100 directly via the subscriber interface 107 with the subscriber-specific part 204. It uses a variety of registers. These registers are used to control the FlexRay protocol controllers, ie the interface modules 207 and 208, the message handler (MHD) 200, the global time unit (GTU) 209, the general system controller (SUC) 210, the Network and error management unit (NEM) 211, the interrupt controller (interrupt controller INT) 212 and the access to the message RAM, so the message memory 300 to configure and control and also to display the corresponding status. At least parts of these registers will be discussed in more detail in Figures 4 to 6 and 7 to 9.
  • Such a described FlexRay communication module 100 allows easy conversion. the FlexRay specification v2.0, which makes it easy to generate an ASIC or a microcontroller with the appropriate FlexRay functionality.
  • the FlexRay protocol specification in particular v2.0
  • the FlexRay protocol specification in particular v2.0
  • up to 128 messages or message objects can be configured.
  • the message memory 300 is advantageously designed as a FIFO (first-in-first-out), resulting in a configurable reception F FO.
  • Each message or message object in memory can be configured as a ReceivedBuffer, TransmitBuffer object, or as part of the configurable ReceiveField.
  • acceptance filtering on frame ID, channel ID and cycle counter in the FlexRay network is possible. Conveniently, the network management is thus supported.
  • maskable module interrupts are also provided.
  • FIG. 3 describes in detail the division of the message memory 300.
  • a message memory is required for the provision of messages to be sent (transmit buffer Tx) as well as the storage of messages received without errors (receive buffer Rx).
  • a FlexRay protocol allows messages with a data range, ie a payload range from 0 to 254 bytes.
  • the message memory 300 is part of the FlexRay communication module 100.
  • the method described below and the corresponding message memory 300 write the storage of messages to be sent as well as received messages, in particular using a Random Access Memory (RAM), whereby it is possible by the mechanism described to store a variable number of blobs in a message memory of predetermined size.
  • RAM Random Access Memory
  • the number of storable messages is dependent on the size of the data areas of the individual messages, whereby on the one hand the size of the required memory can be minimized without restricting the size of the data areas of the messages and on the other hand an optimal utilization of the memory takes place.
  • this variable division of a particular RAM-based message memory 300 for a FlexRay Communication Controller will be described in more detail.
  • a message memory with a defined word length of n bits, for example 8, 16, 32, etc., as well as a predefined memory depth of m words is given by way of example (m, n as natural numbers).
  • the message memory 300 is divided into two segments, a header segment or header segment HS and a data segment DS (Payload Section, Payload Segment).
  • a header area HB and a data area DB are created per message.
  • header areas or header areas HB0, HB1 to HBk and data areas DB0, DB1 to DBk are thus created.
  • first and second data the first data corresponding to configuration data and / or status data relating to the FlexRay message and stored in a header area HB (HBO, HB1, ..., HBk) in each case.
  • the second data which correspond to the actual user data that is to be transmitted, are correspondingly stored in data areas DB (DBO, DBl,..., DBk).
  • the Distribution between header segment HS and data segment DS is now variable in the message memory 300, ie there is no predetermined boundary between the areas.
  • the division between head segment HS and data segment DS is dependent on the number k of messages and the second data volume, ie the extent of the actual user data, a message or all k messages together.
  • the configuration data KDO, KD1 to KDk of the respective message is now assigned directly to a pointer element or data pointer DPO, DPI to DPk.
  • each head area HBO, HB 1 to HBk is assigned a fixed number of memory words, here two, so that always a configuration data KD (KDO, KD 1, ..., KDk) and a pointer element DP (DPO, DPI , ..., DPk) are stored together in a header area HB.
  • the data segment DS includes for storing the actual message data DO, Dl to Dk.
  • This data segment (or data section) DS depends in its data volume from the respective data volume of the stored message data, here z. For example, in DBO six words, DBl one word and DBk two words.
  • the respective pointer elements DPO, DPI to DPk thus always point to the beginning, ie to the start address of the respective data area DBO, DB1 to DBk, in which the data DO, D1 to Dk of the respective messages 0, 1 to k are stored.
  • the division of the message memory 300 between header segment HS and data segment DS is variable and depends on the number k of messages themselves and the respective data volume of a message and thus the entire second data volume. If fewer messages are configured, the header segment HS becomes smaller and the freed area in the message memory 300 can be used as an addition to the data segment DS for the storage of data. This variability ensures optimal memory utilization, which also allows the use of smaller memory.
  • the free data segment FDS in particular its size, also depends on the combination of The number k of messages stored and the respective second data volume of the messages is thus minimal and can even be zero.
  • the first and second data ie the configuration data KD (KDO, KDl, ..., KDk) and the actual data D (DO, Dl, ..., Dk) in a predetermined Store sequence so that the order of the header areas HBO to HBk in the header segment HS and the order of the data areas DBO to DBk in the data segment DS is identical. Then could even be dispensed with a pointer element under certain circumstances.
  • the message memory is associated with a fault detection generator, in particular a parity bit generator element and a fault detection tester, in particular a parity bit test element, to ensure the correctness of the stored data in HS and DS by per memory word or per area (HB and / or DB) a checksum just in particular as a parity bit can be stored.
  • a fault detection generator in particular a parity bit generator element
  • a fault detection tester in particular a parity bit test element
  • the user can decide in programming whether to use a larger number of messages with a small data field or whether he wants to use a smaller number of messages with a large data field.
  • the available storage space is optimally utilized.
  • the user has the option to share a data storage area for different messages.
  • the size of the message memory 300 can be adapted to the needs of the application by adapting the memory depth (number m of words) of the memory used, without changing the other functions of the communication controller.
  • the host CPU access that is to say writing and reading of configuration data or status data and of the actual data via the buffer memory arrangement 201 and 202, will now be described in greater detail with reference to FIGS. 4 to 6 and 7 to 9.
  • the aim is to produce a decoupling with regard to the data transmission in such a way that the data integrity can be ensured and at the same time a high transmission speed is ensured.
  • the control of these processes via the message manager 200, which will be described later in more detail in Figures 10, 11 and 12.
  • FIGS. 4, 5 and 6 the write accesses to the message memory 300 by the host CPU of the subscriber CPU 102 via the input buffer 201 are first explained in greater detail.
  • FIG. 4 once again shows the communications module 100, with only the parts of the communications module 100 relevant here being shown for reasons of clarity.
  • the message manager 200 responsible for controlling the processes and two control registers 403 and 404 which, as shown, can be accommodated outside the message manager 200 in the communication module 100, but can also be contained in the message administrator 200 itself.
  • 403 represents the input request register (Input Buffer Command Request
  • IBCR Input Buffer Command Mask Register
  • IBMR Input Buffer Command Mask Register
  • the accesses are controlled via the input request register 403 and via the input mask register 404.
  • the numbers from 0 to 31 in FIG. 5 show the respective bit positions in 403 by way of example here for a width of 32 bits. The same applies to the register 404 and the bit positions 0 to 31 in the mask register 404 from FIG. 6.
  • the bit positions 0 to 5, 15, 16 to 21 and 31 of the register 403 have a special function with regard to the sequence control.
  • an identifier IBRH Input Buffer Request Host
  • an identifier IBRS Input Buffer Request Shadow
  • register 15 of 403 IBSYH and in register 31 of 403 IBSYS are registered as access identifiers.
  • the host CPU 102 writes the data of the message to be transferred into the input buffer memory 201.
  • the host CPU 102 can only send the configuration and header data KD of a message for the header segment HS of the message buffer.
  • Which part of a message, that is to say configuration data and / or the actual data, is to be transmitted is determined by the special data identifiers LHSH and LDSH in the input tag register 404.
  • LHSH Load Header Section Host
  • LDSH Load Data Section Host
  • start bit or the start identifier STXRH is set in bit position 2 of the input mask register 404, after the transfer of the respective configuration data and / or actual data to be transmitted to the message memory 300, a send request (transmission Request) for the corresponding message object. Ie. The automatic transmission of a transmitting message object is controlled, in particular started, by this start identifier STXRH.
  • the counterpart corresponding thereto for the shadow memory 401 is the start identifier STXRS (Set Transmission X Request Shadow), which is contained by way of example in bit position 18 of the input marking register 404 and, in the simplest case, is also designed as one bit.
  • STXRS Set Transmission X Request Shadow
  • the function of STXRS is analogous to the function of STXRH, referring only to the shadow memory 401.
  • the host CPU 102 When the host CPU 102 writes the message ID, in particular, the message object number in the message memory 300 into which the data of the input buffer memory 201 is to be transferred to the bit positions 0 to 5 of the input request register 403, that is, after IBRH, the partial buffer memory 400 of FIG Input buffer memory 201 and the associated shadow memory 401 are swapped, respectively, and the respective access of host CPU 102 and message memory 300 to the two sub-memories 400 and 401 is interchanged, as indicated by the semicircular arrows.
  • This z. B. also the data transfer, so the data transfer to the message memory 300 started.
  • the data transmission to the message memory 300 itself takes place from the shadow memory 401.
  • the register areas IBRH and IBRS are exchanged.
  • IBRS thus shows the identifier of the message, ie the number of the message object for the one transmission, ie a transfer from the shadow memory 401 is in progress or which message object, ie which area in the message memory 300 as the last data (KD and / or D) has received the shadow memory 401.
  • IBSYS Input Buffer Busy Shadow
  • IBSYH input buffer busy host
  • IBSYH input buffer busy host
  • the mechanism thus described allows the host CPU 102 to continuously transfer data to the message objects contained in the message memory 300, consisting of the header area HB and the data area DB, provided that the access speed of the host CPU 102 to the input buffer memory 201 is less than or equal to the internal one Data transfer rate of the FlexRay IP module, ie the communication block 100.
  • FIGS. 7, 8 and 9 the read accesses to the message memory 300 by the host CPU or user CPU 102 via the output buffer 202 are explained in greater detail.
  • Figure 7 once again shows the communication module 100, where for reasons of clarity, only the relevant parts of the communication module 100 are shown here. On the one hand, this is the responsibility of controlling the processes.
  • 703 represents the output buffer command request register (OBCR) and 704 the output buffer command mask register (OBCM).
  • OBCR output buffer command request register
  • OBCM output buffer command mask register
  • This output buffer 202 is now likewise divided or doubled, as a partial buffer 701 and a shadow memory associated with the partial buffer memory 700.
  • a continuous access of the host CPU 102 to the messages or message objects respectively data of the Message memory 300 and thus data integrity and accelerated transmission are now ensured in the opposite direction from the message memory 300 to the host 102.
  • the accesses are controlled via the output request register 703 and via the output mask register 704.
  • the numbers from 0 to 31 represent the respective bit positions in 703 by way of example for a width of 32 bits (see FIG ).
  • register 704 and bit positions 0 to 31 in 704 see FIG.
  • bit positions 0 to 5, 8 and 9, 15 and 16 to 21 of register 703 have a special function with respect to the flow control of the read access.
  • an identifier OBRS Output Buffer Request Shadow
  • an identifier OBRH Output Buffer Request Host
  • an identifier OBSYS Output Buffer Busy Shadow
  • Excellent are also the digits 0 and 1 of the output mask register 704, wherein in the bit positions 0 and 1 with RDSS (Read Data Section Shadow) and RHSS (Read Header Section Shadow) other IDs are entered as data IDs. Further data identifiers are provided, for example, in bit positions 16 and 17 with RDSH (Read Data Section Host) and RHSH (Read Header Section Host). Here again, these data identifications are in the simplest form, namely designed in each case as one bit. In bit position 9 of the register 703, a start identifier REQ is entered. Furthermore, a switchover identifier VIEW is provided, which is entered by way of example in bit position 8 of register 703.
  • the host CPU 102 requests the data of a message object from the message memory 300 by writing the ID of the desired message, that is, in particular, the number of the desired message object to OBRS in the bit positions 0 to 5 of the register 703.
  • the host CPU 102 can read only the status or configuration data KD of a message from a header area or only the data D actually to be transmitted from the data area or both , Which part of the data is to be transferred from the header area and / or data area is thus set comparable to the opposite direction by RHSS and RDSS. That is, RHSS indicates whether the header data should be read, and RDSS indicates whether the actual data should be read.
  • a start identifier serves to start the transmission from the message memory 300 to the shadow memory 700. That if a bit is used as the identifier, as in the simplest case, the transmission from the message memory 300 to the bit memory 9 is set by setting bit REQ in bit position 9 in the output request register 703
  • Shadow memory 700 started.
  • the current transmission is again indicated by an access identifier, here again in the simplest case by a bit OBSYS in the register 703.
  • REQ bit can only be set if OBSYS is not set, ie no ongoing transmission is currently taking place.
  • the actual sequence could now on the one hand comparable to the opposite direction as described in Figures 4, 5 and 6 described (complementary register assignment) and done or in a variation by an additional identifier, namely a switchover VIEW in bit position 8 of the register 703.
  • the bit OBSYS is reset and by setting the bit VIEW in the output request register 703, the partial buffer memory 701 and the associated shadow memory 700 are exchanged or exchanged, and the host CPU 102 can now read the message memory requested by the message memory 300 message object, ie the corresponding message from the sub-buffer 701.
  • the register cells OBRS and OBRH are exchanged.
  • RHSS and RDSS are exchanged for RHSH and RDSH.
  • the bit VIEW can only be set if OBSYS is not set, ie no ongoing transmission takes place.
  • This output buffer 202 like the input buffer 201, is designed in two parts to provide continuous access by the host CPU 102 to the message objects residing in the message memory 300 are guaranteed.
  • the advantages of high data integrity and accelerated transmission are achieved.
  • the use of the described input and output buffers 201, 202 ensures that a host CPU 102 can access the message memory 300 uninterruptedly despite the module-internal latencies.
  • the data transmission, in particular the forwarding in the communication module 100, by the message manager 200 is made.
  • the message manager 200 is shown in FIG.
  • the message manager 200 can be represented in its functionality by a plurality of state machines or state machines, ie finite state machines, so-called finite state machines (FSM). In this case, at least three state machines and in a particular embodiment four finite state machines are provided.
  • a first finite-state machine is the IOBF-FSM and designated 501 (input / output buffer state machine).
  • This IOBF-FSM could also be divided into two finite-state machines per transmission direction with regard to the input buffer memory 201 or the output buffer memory 202.
  • IBF-FSM Input Buffer FSM
  • OBF-FSM Output Buffer FSM
  • IBF FSM, OBF-FSM, TBF1-FSM, TBF2-FSM, AFSM maximum of five state machines
  • a second finite-state machine is here divided in the course of the preferred embodiment into two blocks 502 and 503 and serves the two channels A and B with respect to the memory 205 and 206, as described for Fig. 2.
  • a finite-state machine can be provided in order to operate both channels A and B or, as in the preferred form, designate a finite-state machine TBF1-FSM as 502 (transient buffer 1 (206, RAM A State Machine) for channel A and for channel B a TBF2-FSM with 503 (Transient Buffer 2 (205, RAM B) State Machine).
  • TBF1-FSM designate a finite-state machine TBF1-FSM as 502 (transient buffer 1 (206, RAM A State Machine) for channel A and for channel B a TBF2-FSM with 503 (Transient Buffer 2 (205, RAM B) State Machine).
  • an arbiter finite state machine is indicated at 500.
  • the data (KD and / or D) are in a by a clock means such.
  • a VCO Voltage Controlled Oscillator
  • a quartz crystal, etc. generated or transferred from this adapted clock in the communication module 100.
  • the clock T can be generated in the block be or externally, z. B. as a bus clock, be given.
  • This arithmetic finite state machine AFSM 500 alternately gives access to the message memory 300 to one of the three finite state machines 501-503, in particular for one clock period T in each case.
  • the time available is corresponding to the access requirements of the individual state machines 501, 502, 503 to these requesting state machines. If an access request is made by only one finite-state machine, it will receive 100% of the access time, ie all the clocks T. If an access request is received from two state machines, each finite-state machine receives 50% of the access time. Finally, if an access request from three state machines occurs, each of the finite state machines will receive 1/3 of the access time. This optimally utilizes the available bandwidth.
  • the first finite-state machine 501 ie IOBF-FSM, performs the following actions as required:
  • the state machine 502 for channel A ie TBF1-FSM, performs the following actions:
  • TBF2-FSM is the finite state machine for channel B in block 503. This performs the data transfer from the selected message object in message memory 300 to buffer memory 205 of channel B and the data transfer from buffer 205 to the selected message object in the message memory 300.
  • the search function is analogous to TBFl-FSM for a matching message object in the message memory 300, wherein upon receipt the message object (Receive Buffer) is searched for storing a message received on channel B in the context of acceptance filtering and the next on transmission Channel B message to be sent or message object (transmit buffer).
  • FIG. 11 shows again the processes and the transmission paths.
  • the three state machines 501-503 control the respective data transfers between the individual parts.
  • the host CPU is shown again at 102, the input buffer memory at 201 and the output buffer memory at 202. With 300 the message memory is shown and the two buffer memories for channel A and channel B with 206 and 205.
  • the interface elements 207 and 208 are also shown.
  • the first state machine IOBF-FSM, designated 501 controls the data transfer ZlA and ZlB, ie from the input buffer memory 201 to the message memory 300 and from the message memory 300 to the output buffer 202.
  • the data is transmitted via data buses having a word width of, for example, 32 bits and any other bit number is possible.
  • This data transmission is controlled by TBFI-FSM, ie the state machine 502 for channel A.
  • the transmission Z3 between message memory 300 and buffer memory 205 is controlled by the state machine TBF2-FSM, ie 503.
  • the transfer of a complete message object via said transmission paths requires several clock periods T. Therefore, the transmission time is divided up by the arbiter, ie the AFSM 500, in relation to the clock periods T.
  • the data paths are between those of the message handler 200 controlled memory components shown.
  • data should advantageously be exchanged simultaneously at the same time only on one of the illustrated paths Z1A and Z1B as well as Z2 and Z3.
  • FIG. 12 shows an example of how the available system clocks T are divided by the arbiter, that is to say the AFSM 500, into the three requesting state machines.
  • access requests are made by state machine 501 and state machine 502, ie, half of the time is split between the two requesting state machines.
  • state machine 501 receives access in the clock periods T1 and T3 and state machine 502 in the clock periods T2 and T4.
  • phase 2 (II) the access is done only by the state machine 501, so that every three clock periods, ie 100% of the access time from T5 to T7 on IOBF-FSM accounts.
  • phase 3 (III) access requests are made by all three state machines 501 to 503, so that one third of the total access time takes place.
  • the arithmetic AFSM 500 then distributes the access time, for example, such that the finite state machine 501 in the clock periods T8 and TIl, the finite state machine 502 in the clock periods T9 and T12 and the finite state in the clock periods T10 and T13 - Machine 503 gets access.
  • the access takes place through two state machines, 502 and 503, on the two channels A and B of the communication module 100, so that an access distribution of the clock periods T14 and T16 on finite state machine 502 and in T15 and T17 on finite state machine 503.
  • the arithmetic state machine AFSM 500 thus ensures that if more than one of the three state machines 501-503 makes a request for access to the message memory 300, the access is intermittently and alternately split to the requesting state machines 501-503. This procedure ensures the integrity of the message objects stored in the message memory 300, that is, the data integrity. If, for example, the host CPU 102 wants to read out a message object via the output buffer 202 while a received message is being written to this message object, then either the old state or the new state will be read out, without which the accesses in the Message object in message memory 300 itself collide.
  • the described method allows the host CPU 102 to read or write any message object in the message memory 300 during operation without the selected message object for the duration of access of the host CPU 102 from participating in the data exchange on both channels of the FlexRay bus 101 would be blocked (Buffer Locking).
  • Buffer Locking the integrity of the data stored in the message memory 300 is ensured by the intermittent interleaving of the accesses, and the transmission speed is increased, even by utilizing the full bandwidth.
  • a communication participant according to the invention is designated in its entirety by the reference numeral 900.
  • the subscriber 900 is connected via a connection 106 to a communication link 101, which is designed, for example, as a FlexRay data bus. Subscriber 900 may communicate (or data or messages) with other connected subscribers (not shown).
  • the subscriber 900 comprises a microcontroller 102 (host CPU), and a communication controller 750 (so-called communication controller CC), which is embodied, for example, as a FlexRay communications controller.
  • the communication controller 705 comprises a FlexRay communication module 100, which has already been described in detail above.
  • the communication module 100 may be formed as an integral part of the communication controller 705 or as a separate component. To improve the connection between the FlexRay communication module 100 and the microcontroller 102, more precisely to improve the connection between a message memory 300 of the
  • the invention proposes to arrange a state machine 800 in the subscriber interface 107 (Customer Interface, CIF) between the communication module 100 and the microcontroller 102.
  • the state machine 800 is preferably hardwired.
  • the state machine 800 alters the subscriber interface 107 to make it worthwhile setting up and starting the DMA controller 812 of the microcontroller 102.
  • the state machine 800 ensures that the data or messages to be transmitted are presented to the DMA controller 812 in such an optimized manner that it can also transmit larger amounts of data or multiple messages with a single call to the DMA controller 812.
  • a single access is composed of the previously required many small accesses or are generated from many segmented address areas with data virtually less contiguous address areas, which can access the DMA controller 812 effectively.
  • latencies of the microprocessor 811 of the microcontroller 102 during data transfer can be avoided.
  • the subscriber-specific sub-component 204 (Customer CPU Interface; CIF) connects the state machine 800 to the FlexRay communications module 100.
  • CIF Customer CPU Interface
  • a bidirectional data line 216, an address line 217, and a control input 218 are provided.
  • Also provided with 219 is an interrupt or interrupt output.
  • the subscriber-specific sub-module 204 is connected to the subscriber-independent sub-module 203 (Generic CPU Interface, GIF), ie the FlexRay communications module 100 has a generic, ie general, CPU interface 203, to which corresponding subscriber-specific sub-modules 204 (CIF) Have a large number of different 900 custom subscriber connected. As a result, depending on the subscriber 900, only the partial module 204 must be varied, which means a significantly lower outlay. The CPU interface 203 and the remaining communication module 100 can be adopted unchanged.
  • the state machine 800 is preferably part of the subscriber-specific sub-module 204 (CIF). Of course, however, it is conceivable that the intelligent subscriber interface 107 according to the invention is designed as a separate component.
  • the subscriber interface 107 or the state machine 800 is connected to the microcontroller 102 via a plurality of lines.
  • a bidirectional data line 816, an address line 817 and a control input 818 are provided.
  • Also provided with 819 is an interrupt or interrupt output.
  • FIG. 15 shows the various signal curves for a read operation (read) in the sense of the method according to the invention.
  • the microcontroller 102 is shown in detail. It comprises a memory 810 which, for example, can be designed as a random access memory (RAM).
  • the memory 810 is for storing incoming messages before
  • the microcontroller 102 includes a microprocessor 811, a so-called host CPU, a DMA controller 812, and an interface 813 to peripheral modules (eg, a so-called expansion bus module ).
  • An internal arbitration unit is designated by reference numeral 814.
  • the subscriber interface 107 comprises the state machine 800.
  • the interface 107 comprises at least one register 802, which is, for example, 64 bits in size and which is used to configure the
  • State machine 800 or the data transfer controlled by state machine 800 serves.
  • corresponding bits are set in the configuration register 802, for example the direction of the data transmission (read, read or write, write), identifiers (for example message numbers) of the messages to be transmitted, order of transmission of the messages, length of the messages, or one of several pre-stored subsequences for data transmission.
  • the configuration parameters may also relate to the number of data words to be transmitted or any other information regarding the forthcoming data transmission.
  • the subscriber interface 107 has a sequence memory 804 which, for example, is designed as a random access memory (RAM). References to certain messages stored in the message memory 300 and information about the messages are stored in the sequence RAM 804.
  • the State machine 800 invokes entries of sequence memory 804 to coordinate and control the data transfer.
  • the sequence memory 804 comprises a plurality, preferably 128, fields with sequence entries.
  • the sequence entries relate, for example, to an identifier (eg a number) of the sequence entry, an identifier or a reference (eg a buffer number) to one or more messages (so-called buffers) of the message memory 300 or the buffer memory 201 or 202, and the size of the message (the buffer).
  • the various sequence entries can be called by the state machine according to specifications of the microprocessor targeted.
  • the sequence entries can be called up unchanged in the saved form or in adapted form.
  • the call of the sequence entry includes certain parameter values for adapting variable parameters of the sequence entry.
  • the sequence entries in the sequence memory 804 preferably relate to frequently occurring transmission sequences, which are stored in advance and are called when necessary. In this way, by calling a single sequence or subsequence (of one or more sequence entries), an extensive data transmission between the message memory 300 and the DMA controller 812 can be triggered.
  • the configuration parameters that are transferred from the microcontroller 811 of the microcontroller 102 into the configuration and status registers 802 at the beginning of the data transfer may also include an identifier (eg, the numbers) of one or more sequence entries that be called by the state machine 800 as part of the data transfer.
  • the reading process is initiated as soon as data transmitted via the FlexRay data bus 101 are stored in the message memory 300 of the FlexRay communication module 100. After receipt of the data in Message memory 300 may trigger an interrupt or a corresponding command to the microcontroller 102 are transmitted. However, it is also conceivable that the input of the data in the message memory 300 is detected by the microcontroller 102, for example by regular polling.
  • the microprocessor 811 configures the DMA controller 812 in a step 850.
  • the microprocessor 811 knows how much data to transmit, knows the size of the messages, and other information regarding the upcoming data transfer. In step 850, this information is at least partially communicated to the DMA controller 812 by the microprocessor 811.
  • the microprocessor 811 configures the state machine 800 in a step 852 by writing configuration parameters to the configuration register 802. The state machine 800 then receives a start command from the microprocessor 811 and then begins the actual data transfer.
  • An outer loop begins at the first data buffer to be transferred.
  • An inner loop begins at the first data word of the first data buffer to be transmitted.
  • the state machine 800 transmits a request / view command 854 to the output buffer 202 or to the configuration registers 703, 704 of the output buffer 202, respectively, to make the data word visible in the output buffer 202.
  • the data word is read out of the message memory 300 via the output buffer 202.
  • the state machine 800 fetches this data word from the output buffer 202 via the generic interface 203 (GIF) in a step 856.
  • GIF generic interface 203
  • header segment HS only the data segment DS or both, both header segment HS and data segment DS, can be transmitted.
  • a transfer of head segment HS and data segment DS is preferably first the head segment HS and then transfer the data segment DS, but the reverse order is also possible.
  • the output buffer 202 or a higher-level control unit of the FlexRay communication module 100 receives information and instructions as to which data word is to be transferred from the message memory 300 into the output buffer 202 next.
  • the data word from the output buffer 202 is now available in the state machine 800 for collection by the DMA controller 812. This is communicated to the DMA controller 812 through a Data Ready command 858. Thereafter, the DMA controller 812 reads in the ready data word in a step 860 and forwards it for further processing. Subsequently, the DMA controller 812 waits for the next data-ready signal 858.
  • the inner loop is incremented to the next data word of the first data buffer, and the above steps are repeated until the last data word of the first data buffer to be read in is successfully read.
  • the outer loop is incremented to the next data buffer to be transferred, and the above steps are repeated until all the data words of the last data buffer to be read have been successfully read.
  • the reading-in of a specific data buffer can take place, for example, by calling a corresponding subsequence from the sequence memory 804.
  • the DMA controller 812 notifies the microprocessor 811 of the end of the data transfer. This can, for example, by a suitable
  • All data transfer is controlled and coordinated by the state machine 800.
  • the host CPU 811 only has to initiate the data transfer by the request command 850, everything else is done by the state machine 800 done so that the greatest possible relief of the host CPU 811 of the microcontroller 102 is given.
  • a conventional subscriber interface 107 is expanded by a state machine 800.
  • At least one sequence of message buffers with associated payload length can be programmed into a memory, for example a RAM.
  • the memory is preferably also part of the subscriber interface 107 according to the invention.
  • a DMA controller 812 of the subscriber 102 For each retrieval of at least one of the partial or total sequences, a DMA controller 812 of the subscriber 102 only has to be triggered once.
  • the (partial) sequences are defined via start / end numbers. Through a maximum of 128 sequence entries, different orders, eg. As read / write. A simultaneous reading and writing via DMA does not take place.
  • a DMA sequence must always be completely processed before a new request command 850 can be started. In the event of an error, an interrupt is sent or a flag is set.
  • FIG. 16 shows the signal curves for writing data (Write) to the message memory 300 of the communication module 100.
  • the writing process is very similar to the reading process. In the following, essentially only the differences between reading and writing will be discussed in more detail.
  • the microprocessor 811 configures the DMA controller 812 in a step 850.
  • the microprocessor 811 configures the state machine 800 in a step 852 by writing configuration parameters to the configuration register 802.
  • the state machine 800 then receives a start command from the microprocessor 811 and then begins the actual data transfer.
  • the outer loop for the currently-to-be-exceeded data buffer and the inner loop for the current go through the transmitted data word of the current data buffer.
  • the input buffer memory 201 is filled in writing (inner loop) and then the command for internal storage in the message memory 300 is given (outer loop).
  • state machine 800 sends a data-ready signal 858 to DMA controller 812 to signal that it is ready to receive the current data word from DMA controller 812. Then, in a step 862, the DMA controller 812 transmits the pending data word to the state machine 800. From there, the data word is then transmitted in a step 864 to the input buffer 201 of the FlexRay communication module 100.
  • Control unit of the FlexRay communication module 100 receives in a step 866 information and instructions about where in the message memory 300, the stored in the input buffer 201 data word is to be stored.
  • suitable information is stored in one or more of the configuration registers 403, 404, for example by setting appropriate bits.
  • the data word is stored from the input buffer 201 at the corresponding location of the message memory 300, from where it is then transmitted alone or together with other data words from the message memory 300 via the FlexRay communication link 101.
  • the inner loop is incremented to the next data word of the first data buffer, and iterates through the above steps until the last data word of the first data buffer has been successfully written into the input buffer 201. Subsequently, the outer loop is on the next is incremented to be transmitted data buffer, and the above steps are again run until all data words of the last data buffer to be written have been successfully transmitted to the communication module 100.
  • the writing of a specific data buffer can, for example, be done by calling a corresponding subsequence from the sequence memory 804.
  • the DMA controller 812 notifies the microprocessor 811 of the end of the data transfer. This can be done, for example, by a suitable command (Data Transmission Ready) or by an interrupt command.
  • the invention relates to a method and a device for the transmission of data between a microprocessor (host CPU) and a peripheral device, for example in the form of a communication controller for communication, in particular in the FlexRay.
  • the peripheral device is preferably designed as a FlexRay communication controller 750, which is connected via a connection 106 to a FlexRay communication link 101, which is formed, for example, as a FlexRay data bus.
  • the microprocessor 811 and the peripheral device are part of a communications party 900.
  • Data communications between the microprocessor host CPU and the peripheral device 750 are typically limited in resources, i. the bandwidth is limited. This is typically the case when using a serial interface.
  • communication module 100 consists in the fact that the access becomes faster because the commands have the knowledge about the arrangement of the data, the type of accesses and the corresponding addresses in the form of a further state machine. In this way, the arrangement of the data, the type of access and / or the corresponding addresses automatically be provided so that they no longer supplied by the host CPU 811 and thus no longer need to be transmitted via the interface 107 or in detail over the connections 216 to 218. Furthermore, the type of access (read / write) can already be permanently installed in this device 107, as already mentioned, so no longer has to be transmitted.
  • the predefined or preprogrammed partial sequences with regard to the information about the data transmission are simply called up or activated and provided with additional values.
  • the sequences By calling one or more of the sequences, several message buffer contents can be transferred from or to the communication module 100 simply and quickly.

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Abstract

L'invention concerne une interface de noeud de réseau (107), entre un module de communication FlexRay (100), qui est relié à une connexion de communication FlexRay (101), par l'intermédiaire de laquelle des ambassades sont transmises et qui contient une mémoire d'ambassades (300) pour stocker temporairement des ambassades de la connexion de communication FlexRay (101) ou pour la connexion de communication FlexRay (100), ainsi qu'un microcontrôleur (102) associé au module de communication FlexRay (100), qui comporte un microprocesseur (811) et un contrôleur (812) à accès à mémoire direct (DMA) pour un échange de données avec la mémoire d'ambassades (300). Afin de mieux relier le contrôleur DMA (812) du microcontrôleur (102) au module de communication FlexRay (100), il est prévu que l'interface de noeud de réseau (107) présente un moteur d'état (800), qui coordonne et régule de manière automatique une transmission de données entre la mémoire d'ambassades (300) du module de communication FlexRay (100) et le contrôleur DMA (812), après configuration par le microprocesseur (811) du microcontrôleur (102).
EP06807000A 2005-10-06 2006-10-05 Interface de noeud de reseau entre un microcontroleur et un module de communication flexray, noeud de reseau flexray et procede de transmission d'ambassades par l'intermediaire d'une telle interface Withdrawn EP1941377A2 (fr)

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DE102005048582A DE102005048582A1 (de) 2005-10-06 2005-10-06 Teilnehmerschnittstelle zwischen einem Mikrocontroller und einem FlexRay-Kommunikationsbaustein, FlexRay-Teilnehmer und Verfahren zur Übertragung von Botschaften über eine solche Schnittstelle
PCT/EP2006/067085 WO2007039634A2 (fr) 2005-10-06 2006-10-05 Interface de noeud de reseau entre un microcontroleur et un module de communication flexray, noeud de reseau flexray et procede de transmission d'ambassades par l'intermediaire d'une telle interface

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US7984210B2 (en) * 2006-06-20 2011-07-19 Freescale Semiconductor, Inc. Method for transmitting a datum from a time-dependent data storage means
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CN101283338A (zh) 2008-10-08
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US20100161834A1 (en) 2010-06-24
JP2009511318A (ja) 2009-03-19

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