EP1900680A3 - Cap wafer having electrodes - Google Patents

Cap wafer having electrodes Download PDF

Info

Publication number
EP1900680A3
EP1900680A3 EP07115664A EP07115664A EP1900680A3 EP 1900680 A3 EP1900680 A3 EP 1900680A3 EP 07115664 A EP07115664 A EP 07115664A EP 07115664 A EP07115664 A EP 07115664A EP 1900680 A3 EP1900680 A3 EP 1900680A3
Authority
EP
European Patent Office
Prior art keywords
cap wafer
wafer substrate
oblique
electrode
penetrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07115664A
Other languages
German (de)
French (fr)
Other versions
EP1900680A2 (en
Inventor
Ji-hyuk 503-504 Jugong Green Ville Apartment Lim
Jun-sik 1104-1006 Jinangol-maeul Jugong 11danji Hwang
Woon-bae c/o Samsung Electro-Mechanics Co. Ltd. Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electro Mechanics Co Ltd
Original Assignee
Samsung Electro Mechanics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electro Mechanics Co Ltd filed Critical Samsung Electro Mechanics Co Ltd
Publication of EP1900680A2 publication Critical patent/EP1900680A2/en
Publication of EP1900680A3 publication Critical patent/EP1900680A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/0413—MIMO systems
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/094—Feed-through, via
    • B81B2207/095—Feed-through, via through the lid

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Pressure Sensors (AREA)

Abstract

A cap wafer, fabrication method, and a semiconductor chip arc provided. The cap wafer includes a cap wafer substrate; a penetrated electrode formed to penetrate the cap wafer substrate; and an electrode pad connected with a lower portion of the penetrated electrode on a lower surface of the cap wafer substrate, wherein the penetrated electrode has an oblique section which gradually widens from an upper surface to the lower surface of the cap wafer substrate. The fabrication method includes forming an oblique-via hole on a lower surface of a cap wafer substrate, the oblique-via hole having an oblique section which gradually narrows in a direction moving away from the lower surface of the cap wafer substrate; and forming a penetrated electrode in the oblique-via hole. The semiconductor chip includes a base wafer; a cap wafer; a cavity; a penetrated electrode; and a pad bonding layer.
EP07115664A 2006-09-15 2007-09-04 Cap wafer having electrodes Withdrawn EP1900680A3 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060089815A KR100750741B1 (en) 2006-09-15 2006-09-15 Cap wafer, semicondoctor chip having the same, and fabrication method thereof

Publications (2)

Publication Number Publication Date
EP1900680A2 EP1900680A2 (en) 2008-03-19
EP1900680A3 true EP1900680A3 (en) 2010-11-17

Family

ID=38537726

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07115664A Withdrawn EP1900680A3 (en) 2006-09-15 2007-09-04 Cap wafer having electrodes

Country Status (4)

Country Link
US (1) US7626258B2 (en)
EP (1) EP1900680A3 (en)
JP (1) JP4789836B2 (en)
KR (1) KR100750741B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9620390B2 (en) 2008-11-19 2017-04-11 Silex Microsystems Ab Method of making a semiconductor device having a functional capping

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US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
EP2575166A3 (en) 2007-03-05 2014-04-09 Invensas Corporation Chips having rear contacts connected by through vias to front contacts
US8193615B2 (en) 2007-07-31 2012-06-05 DigitalOptics Corporation Europe Limited Semiconductor packaging process using through silicon vias
JP4784641B2 (en) * 2008-12-23 2011-10-05 株式会社デンソー Semiconductor device and manufacturing method thereof
US8482132B2 (en) 2009-10-08 2013-07-09 International Business Machines Corporation Pad bonding employing a self-aligned plated liner for adhesion enhancement
US10297550B2 (en) * 2010-02-05 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC architecture with interposer and interconnect structure for bonding dies
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8343789B2 (en) 2010-08-17 2013-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Microstructure device with an improved anchor
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
KR20120077876A (en) 2010-12-31 2012-07-10 삼성전자주식회사 Heterojunction structures of different substrates joined and methods for fabricating the same
US9165792B2 (en) * 2012-09-25 2015-10-20 Infineon Technologies Ag Integrated circuit, a chip package and a method for manufacturing an integrated circuit
SE538311C2 (en) * 2013-08-26 2016-05-10 Silex Microsystems Ab Thin covering structure for MEMS devices
WO2017139542A1 (en) * 2016-02-11 2017-08-17 Skyworks Solutions, Inc. Device packaging using a recyclable carrier substrate
US10453763B2 (en) 2016-08-10 2019-10-22 Skyworks Solutions, Inc. Packaging structures with improved adhesion and strength
CN107764439B (en) * 2016-08-19 2020-01-24 上海丽恒光微电子科技有限公司 Preparation method of pressure sensor
CN108172553A (en) * 2018-01-17 2018-06-15 杭州暖芯迦电子科技有限公司 A kind of encapsulating structure and its packaging method of retina Using prosthesis chip

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1071126A2 (en) * 1999-07-23 2001-01-24 Agilent Technologies Inc Microcap wafer-level package with vias
US20040259325A1 (en) * 2003-06-19 2004-12-23 Qing Gan Wafer level chip scale hermetic package
US20050082653A1 (en) * 2003-09-26 2005-04-21 Tessera, Inc. Structure and method of making sealed capped chips
DE10393265T5 (en) * 2002-09-13 2005-09-15 Advantest Corp. Micro device and method for its production

Family Cites Families (12)

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Publication number Priority date Publication date Assignee Title
US5229647A (en) * 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
KR100394808B1 (en) * 2001-07-19 2003-08-14 삼성전자주식회사 Wafer level stack chip package and method for manufacturing the same
JP2004129223A (en) * 2002-07-31 2004-04-22 Murata Mfg Co Ltd Piezoelectric component and manufacturing method thereof
JP2004193297A (en) * 2002-12-11 2004-07-08 Dainippon Printing Co Ltd Wafer level package and its manufacturing method
KR100512971B1 (en) * 2003-02-24 2005-09-07 삼성전자주식회사 Manufacturing method of micro electro mechanical system using solder ball
US6841883B1 (en) * 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
JP2005109221A (en) * 2003-09-30 2005-04-21 Toshiba Corp Wafer-level package and its manufacturing method
US7109068B2 (en) * 2004-08-31 2006-09-19 Micron Technology, Inc. Through-substrate interconnect fabrication methods
US7061099B2 (en) * 2004-09-30 2006-06-13 Intel Corporation Microelectronic package having chamber sealed by material including one or more intermetallic compounds
JP2006173557A (en) * 2004-11-22 2006-06-29 Toshiba Corp Hollow type semiconductor apparatus and its manufacture
US7449355B2 (en) * 2005-04-27 2008-11-11 Robert Bosch Gmbh Anti-stiction technique for electromechanical systems and electromechanical device employing same
KR100731351B1 (en) * 2006-02-01 2007-06-21 삼성전자주식회사 Wafer level package for surface acoustic wave device and fablication method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1071126A2 (en) * 1999-07-23 2001-01-24 Agilent Technologies Inc Microcap wafer-level package with vias
DE10393265T5 (en) * 2002-09-13 2005-09-15 Advantest Corp. Micro device and method for its production
US20040259325A1 (en) * 2003-06-19 2004-12-23 Qing Gan Wafer level chip scale hermetic package
US20050082653A1 (en) * 2003-09-26 2005-04-21 Tessera, Inc. Structure and method of making sealed capped chips

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9620390B2 (en) 2008-11-19 2017-04-11 Silex Microsystems Ab Method of making a semiconductor device having a functional capping

Also Published As

Publication number Publication date
KR100750741B1 (en) 2007-08-22
JP4789836B2 (en) 2011-10-12
JP2008072082A (en) 2008-03-27
US20080067664A1 (en) 2008-03-20
EP1900680A2 (en) 2008-03-19
US7626258B2 (en) 2009-12-01

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Inventor name: LIM, JI-HYUK,503-504, JUGONG GREEN VILLE APARTMENT

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Inventor name: LIM, JI-HYUK,503-504, JUGONG GREEN VILLE APARTMENT

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