EP1859373A2 - Method for optimizing transistor performance in integrated circuits by diffusion sharing across cell boundaries - Google Patents

Method for optimizing transistor performance in integrated circuits by diffusion sharing across cell boundaries

Info

Publication number
EP1859373A2
EP1859373A2 EP06709805A EP06709805A EP1859373A2 EP 1859373 A2 EP1859373 A2 EP 1859373A2 EP 06709805 A EP06709805 A EP 06709805A EP 06709805 A EP06709805 A EP 06709805A EP 1859373 A2 EP1859373 A2 EP 1859373A2
Authority
EP
European Patent Office
Prior art keywords
cell
cells
diffusion
active
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06709805A
Other languages
German (de)
French (fr)
Inventor
Shannon Vance 3 Kenton Mews MORTON
Peter William Hughes
Trevor Kenneth Monk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nvidia Technology UK Ltd
Original Assignee
Icera LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Icera LLC filed Critical Icera LLC
Publication of EP1859373A2 publication Critical patent/EP1859373A2/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays

Definitions

  • This invention relates generally to integrated circuits, and more particularly to methods for optimising performance of logic cells within a standard cell library for large scale integration of semiconductor integrated circuits.
  • a standard cell is a pre-designed layout of transistors or non-specific collection of logic gates that are typically designed with computer assisted design (CAD) applications.
  • CAD computer assisted design
  • the cells are usually interconnected or wired together in a particular manner with means of a placement and routing tool to perform a specific type of logical operation in an application specific IC (ASIC) .
  • a conventional ASIC layout is typically defined by an ⁇ array of logic cells arranged in adjacent rows. Such a row 10 is shown in FIG. 1.
  • the row of cells is depicted for illustrative purposes as a layout representation of abutting logic cells 12,31,32,33,35 bound by power and ground rails 14,16.
  • Each logic cell defines a specific logic circuit.
  • the active areas or components of the logic cell include negative-channel diffusion 24, positive-channel diffusion 26, and gate 34 layers.
  • the components of the logic cells are wired internally with vias 28 and metal layer 18,20,22 to form simple logic (NMOS and PMOS) gates to perform Boolean and logic functions, for example INVERTER (or NOT) 12,35, AND, OR, NAND 31, NOR 32, 33 XOR, XNOR, ADDERS, FLIP-FLOP, and the like.
  • integrated circuit design rules must be observed, for example, minimum width of transistor width, minimum width of metal tracks, and the like.
  • An aspect of the invention provides a method for optimising transistor performance in an integrated circuit, comprises providing an integrated circuit having at least two cells, each cell having a logic function defined by the interconnection between active regions, non-active regions and power rails, each cell having an edge defined by a non-active region each cell having a connection between an active diffusion region and a power rail; identifying at least two adjacent cells each having a corresponding connection between an active region to the same power rail; and joining the respective active regions associated with each corresponding connection of each cell with an additional diffusion area across the boundary between the cells forming the connected diffusion of the two adjacent cells.
  • An aspect of the invention provides a method for building an integrated circuit having a connected diffusion cell architecture, comprises: providing a logic cell library having at least one cell, each cell having a logic function defined by the interconnection between active regions, non-active regions and power rails, each cell having an edge defined by a non-active region, each cell having a connection between an active region and a power rail; placing cells from the logic cell library into the integrated circuit; identifying at least two adjacent cells in the integrated circuit each having a corresponding connection between an active region to the same power rail; and joining the respective active regions associated with each corresponding connection of each cell with an additional diffusion area across the boundary between the cells forming the connected diffusion of the two adjacent cells .
  • the active regions comprise a positive diffusion area, a negative diffusion area and a gate area.
  • the connected diffusion may be the negative diffusion area or wherein each negative diffusion area of each adjacent cell are connected and each positive diffusion area of each adjacent cell are connected.
  • the corresponding connection may be positioned along the edge of the cell forming a boundary between the two cells and the two corresponding connections. Additionally, an embodiment may further comprise reorientating a cell having a corresponding connection positioned along an edge, the cell being reoriented with the edge having the corresponding connection adjacent to and forming the boundary between the two cells for joining the diffusion areas.
  • An aspect of the invention provides an integrated circuit having a connected diffusion cell architecture, comprising: at least two adjacent cells, each cell having a logic function defined by the interconnection between active regions, non- active regions and power rails, each cell having an edge defined by a non-active region, each cell having a connection between an active region and a power rail; additional diffusion area across the boundary between the cells joining the respective active diffusion region associated with the corresponding connection of each cell forming the connected diffusion of the two adjacent cells.
  • FIG. 1 shows a physical layout design of a row of cell structures within a CMOS environment
  • FIG. 2 shows a physical layout design of cell structures of FIG. 1 reconfigured in accordance with an embodiment of the invention
  • FIG. 3 Shows a physical layout design of cell structures of FIG. 2 having continuous active areas in accordance with an embodiment of the invention
  • FIG. 4A-B shows a schematic diagram of a side view of NMOS regions of two adjacent cells in accordance with an embodiment of the invention.
  • FIG. 5A-B are flow charts of methods in accordance with an embodiment of the invention.
  • a conventional cell includes non-active areas 36, for example STI regions, surrounding active areas or regions 24,26,34 within each cell.
  • non-active areas 36 for example STI regions, surrounding active areas or regions 24,26,34 within each cell.
  • the STI regions forming cell boundaries straddle the border of two adjacent cells.
  • the active areas include the diffusion 24,26 and gate areas 34.
  • the supply nets 20,18 are supply connections between positive-channel 26 and negative-channel diffusion 24 and respective power rails 14,16 (V DD ,V SS ) .
  • the supply nets may be configured along a boundary or an edge 39 of the cell.
  • a boundary or edge 39 of the cell is defined by a continuous STI region 36 that straddles across two adjacent cells, at the block level, between power and ground rails 14,16.
  • each cell may have at least one positive net and/or at least one negative net along an edge. Therefore adjacent cells may or may not have corresponding supply nets along bordering edges .
  • FIG. 2 shows a layout symbolic representation 70 of the row of logic cells of FIG. 1, however, cells with corresponding nets along an edge of bordering cells may be flipped about a y-axis (not shown) of the cell.
  • the flipped cells 71,73,75 have edges with corresponding positive nets and negative nets of adjacent cells orientated to lie adjacent across the cell boundary of the adjacent cell 78. It will be appreciated that it may not be necessary to flip any cells, for example, adjacent cells may already have corresponding nets along the boundary 78.
  • FIG. 2 shows respective positive and negative net orientation, however, advantages of embodiments of the invention may be achieved with orientating the cells such that only the same net type (i.e. positive nets or alternatively the negative nets) of each adjacent cell lie along the edge of the boundary between the two cells.
  • FIG. 3 shows the cell row arrangement of FIG. 2 in accordance with an embodiment of the invention the area bound between the corresponding supply nets of the two adjacent cells are filled at the block level above the cells with additional diffusion 102.
  • This filling of diffusion alters the overall diffusion profile of the adjacent cells.
  • the two adjacent cells having an edge with corresponding NMOS (V ss ) negative nets that lie on either side of the cell boundary form a continuous negative- channel diffusion 24. Nets 18,20 accordingly continue to interconnect diffusions 24,26 for each cell. It will be appreciated that the same process may be applied to the positive-channel 26 diffusion.
  • CMOS technology the advantages of filling the negative-channel diffusion of NMOS improves performance, however, the invention is not limited to filling only the negative-channel diffusion.
  • the additional diffusion 102 may be filled with various techniques known in the field, such as a dummy layer or abutment algorithm method, grow/shrink method, and the like.
  • a dummy layer or abutment algorithm method For example in the dummy layer approach, each cell is built, or modified such that a dummy mask layer is added in the region between the cell border, and the diffusion which connects to a V ss net. This will have a minimum width of "W", by virtue of manufacturing design rules.
  • a dummy layer width is equal to ⁇ 2W"
  • the dummy layer is replaced with diffusion fill.
  • all NMOS diffusion is grown in the horizontal direction by an amount ⁇ W" .
  • FIG. 4A-B shows schematic diagrams of a side view of NMOS regions of two adjacent cells in accordance with an embodiment of the invention.
  • FIG. 4A shows the STI and active regions and the stress resulting from STI being a harder material than the diffusion regions (NMOS or PMOS) .
  • the pushing force between the two materials creates stress which impacts the performance.
  • the stress is removed, as shown in FIG. 4B. Diffusion may be added where adjacent supply nets connected to the same power or ground.
  • the diffusion fill is added between celll and cell2 at the block level of the IC, which is the next level up in the design hierarchy, above the cell level, and consists of multiple rows of such cells.
  • FIG. 4A shows the STI and active regions and the stress resulting from STI being a harder material than the diffusion regions (NMOS or PMOS) .
  • the pushing force between the two materials creates stress which impacts the performance.
  • Diffusion may be added where adjacent supply nets connected to the same power or ground.
  • the diffusion fill
  • FIG. 5A shows a flow chart of a method 300 in accordance with an embodiment of the invention.
  • a standard cell library is provided 310.
  • the ASIC 315 is built from a cell, or more typically a collection of cells in the library.
  • cells are interconnected to effect a specific function. Those cells may be arranged in an array of rows.
  • ASIC block is built, using automated or custom place and route tools two adjacent cells are identified 320 along the row that have the same net, for example V ss , on diffusion on either side of a boundary between the two cells.
  • the diffusion areas associated with the supply nets of the two cells are joined 330 such that the two adjacent cells that are identified with corresponding nets form a single continuous diffusion area.
  • FIG. 5B shows a flow chart of a method 350 in accordance with another embodiment that shares steps 320,330 and may also have the optional flipping step 352 as set out in the method of FIG. 5A. However, the method of FIG.5B begins with having the ASIC provided 305.
  • the active areas i.e. negative and positive diffusion channels 24,26 have a longer continuous length than the arrangement of FIG. 1.
  • a longer continuous diffusion channel length reduces the number interfaces occurring between active diffusion areas and STI regions along a row of cells. For example, for cells 33,35 in FIG. 1, the number of active diffusion area and STI region interactions is halved as shown in comparing FIG. 1 and 3. The reduction in the occurrences of stress between the STI regions and the active diffusion areas correlates with an improvement in performance .
  • An embodiment of the invention may be implemented with computer aided design (CAD) systems that are well known to a skilled person.
  • Well known hardware description languages such as Very High Speed Integrated Circuit Hardware Description Language (VHDL) and VERILOG, both international standard languages of Institute of Electrical and Electronic Engineers, Inc. (IEEE), may be used to implement the invention to describe an ASIC, which is then synthesized into detailed logic functions comprising standard cells.
  • VHDL Very High Speed Integrated Circuit Hardware Description Language
  • IEEE Institute of Electrical and Electronic Engineers, Inc.
  • An example of a tool to perform the synthesis is DESIGN COMPILER (DESIGN COMPILER is a trademark in certain countries of Synopsys, Inc. of Mountain View, California, United States of America) .
  • the cell library may also be designed with modelling tools or logic schematic programs on a CAD system to create symbolic representations such as a layout of logic functions, for example, VIRTUOSO (VIRTUOSO is a trademark in certain countries of Cadence Design Systems, Inc., of San Jose, California, United States of America) .
  • VIRTUOSO is a trademark in certain countries of Cadence Design Systems, Inc., of San Jose, California, United States of America
  • the ASIC may be built in rows of standard cells as mentioned above, or by other techniques known such as custom transistor level layout or the like.
  • ASIC developers may use "place and route” (P&R) tools to flip the cells as required for increasing the applicability of the technique.
  • P&R place and route
  • the placement and routing tools generate the associated mask patterns to physically wire the standard cells in the manner required to implement the ASIC function.
  • placement tools provide initial placement of cells in a block or IC when the routing needs are estimated
  • routing tools are capable of moving cells from their initial placement once the routing needs are known.
  • "place and route” tools that may be used are PHYSICAL COMPILER and ASTRO, respectively (PHYSICAL COMPILER and ASTRO are trademarks in certain countries of Synopsys, Inc.) .
  • PHYSICAL COMPILER and ASTRO are trademarks in certain countries of Synopsys, Inc.
  • the hardware and software required to implement the invention, and indicated for explaining the preferred embodiment should not be limiting.
  • the software processes running on them may be arranged, configured or distributed in any manner suitable for performing the invention defined by the claims.
  • block level diffusion fill method as described above provides advantages such as limiting the occurrence of stress between active areas and STI regions of the logic cells and improving overall performance. Additionally, embodiments may be applied to all types of ASICs, whether the ASIC is built from a collection of logic cells of a standard cell library (as discussed above) or from other techniques such as from full custom layout and the like. It will be appreciated that specific embodiments of the invention are discussed for illustrative purposes, and various modifications may be made without departing from the scope of the invention as defined by the appended claims.

Abstract

A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12) , or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) between two adjacent cells (112) having the same net on diffusion at the adjacent edges of each cell. The diffusion area is extended to limit the occurrence of active and nonactive interface to minimise lattice strain effects and improve transistor performance.

Description

METHOD FOR OPTIMISING TRANSISTOR PERFORMANCE IN INTEGRATED CIRCUITS
FIELD OF THE INVENTION
This invention relates generally to integrated circuits, and more particularly to methods for optimising performance of logic cells within a standard cell library for large scale integration of semiconductor integrated circuits.
BACKGROUND
Conventional standard cell libraries in semiconductor integrated circuits (IC) primarily contain a logic cell layout based in a metal oxide semiconductor (MOS) environment, in particular a complimentary metal oxide semiconductor (CMOS) environment. A standard cell is a pre-designed layout of transistors or non-specific collection of logic gates that are typically designed with computer assisted design (CAD) applications. The cells are usually interconnected or wired together in a particular manner with means of a placement and routing tool to perform a specific type of logical operation in an application specific IC (ASIC) . A conventional ASIC layout is typically defined by an ■ array of logic cells arranged in adjacent rows. Such a row 10 is shown in FIG. 1. The row of cells is depicted for illustrative purposes as a layout representation of abutting logic cells 12,31,32,33,35 bound by power and ground rails 14,16. Each logic cell defines a specific logic circuit. The active areas or components of the logic cell include negative-channel diffusion 24, positive-channel diffusion 26, and gate 34 layers. The components of the logic cells are wired internally with vias 28 and metal layer 18,20,22 to form simple logic (NMOS and PMOS) gates to perform Boolean and logic functions, for example INVERTER (or NOT) 12,35, AND, OR, NAND 31, NOR 32, 33 XOR, XNOR, ADDERS, FLIP-FLOP, and the like. In the design of the interconnection layout, integrated circuit design rules must be observed, for example, minimum width of transistor width, minimum width of metal tracks, and the like.
Recent advances made in semiconductor technology have enabled cell library layout designers to work on the nanometer scale. However, as a result of this technology scaling, additional problems have surfaced concerning the physical properties of the ASIC. Such a problem includes stress occurring in materials near an interface of different materials with different crystallographic structures or thermal expansion coefficients. The stress creates strain in the active and shallow trench isolation (STI) regions 36 within the cell. The strain related with these physical interactions substantially effects the characteristics of the component transistors in the integrated circuit. For example, in the NMOS and PMOS devices, such as field effect transistors (FET) , the impact of the stress may be severe and result in 10% or more variation of output performance. Noticeably, in the NMOS devices, lattice strain is responsible for a reduction in the current between source and drain (I0) • A similar variation is reflected in the PMOS device, however, the fluctuation is a positive increase which actually is a beneficial variation improving the PMOS device performance.
Thus, there is a need for a method to avoid the reduction in drain current which is effected adversely by lattice stresses between the active regions and STI regions of the transistor devices of semiconductor integrated circuits.
STATEMENT OF THE INVENTION
An aspect of the invention provides a method for optimising transistor performance in an integrated circuit, comprises providing an integrated circuit having at least two cells, each cell having a logic function defined by the interconnection between active regions, non-active regions and power rails, each cell having an edge defined by a non-active region each cell having a connection between an active diffusion region and a power rail; identifying at least two adjacent cells each having a corresponding connection between an active region to the same power rail; and joining the respective active regions associated with each corresponding connection of each cell with an additional diffusion area across the boundary between the cells forming the connected diffusion of the two adjacent cells.
An aspect of the invention provides a method for building an integrated circuit having a connected diffusion cell architecture, comprises: providing a logic cell library having at least one cell, each cell having a logic function defined by the interconnection between active regions, non-active regions and power rails, each cell having an edge defined by a non-active region, each cell having a connection between an active region and a power rail; placing cells from the logic cell library into the integrated circuit; identifying at least two adjacent cells in the integrated circuit each having a corresponding connection between an active region to the same power rail; and joining the respective active regions associated with each corresponding connection of each cell with an additional diffusion area across the boundary between the cells forming the connected diffusion of the two adjacent cells .
In an embodiment the active regions comprise a positive diffusion area, a negative diffusion area and a gate area. The connected diffusion may be the negative diffusion area or wherein each negative diffusion area of each adjacent cell are connected and each positive diffusion area of each adjacent cell are connected. The corresponding connection may be positioned along the edge of the cell forming a boundary between the two cells and the two corresponding connections. Additionally, an embodiment may further comprise reorientating a cell having a corresponding connection positioned along an edge, the cell being reoriented with the edge having the corresponding connection adjacent to and forming the boundary between the two cells for joining the diffusion areas.
An aspect of the invention provides an integrated circuit having a connected diffusion cell architecture, comprising: at least two adjacent cells, each cell having a logic function defined by the interconnection between active regions, non- active regions and power rails, each cell having an edge defined by a non-active region, each cell having a connection between an active region and a power rail; additional diffusion area across the boundary between the cells joining the respective active diffusion region associated with the corresponding connection of each cell forming the connected diffusion of the two adjacent cells.
BRIEF DESCRIPTION OF THE DRAWINGS
A method for incorporating the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:
FIG. 1 shows a physical layout design of a row of cell structures within a CMOS environment; FIG. 2 shows a physical layout design of cell structures of FIG. 1 reconfigured in accordance with an embodiment of the invention;
FIG. 3 Shows a physical layout design of cell structures of FIG. 2 having continuous active areas in accordance with an embodiment of the invention;
FIG. 4A-B shows a schematic diagram of a side view of NMOS regions of two adjacent cells in accordance with an embodiment of the invention; and
FIG. 5A-B are flow charts of methods in accordance with an embodiment of the invention.
DETAILED DESCRIPTION
With reference to FIG. 1, a physical layout of a row of logic cells is shown arranged in a conventional manner. A conventional cell includes non-active areas 36, for example STI regions, surrounding active areas or regions 24,26,34 within each cell. There may be STI regions within a cell, especially when the cell has more than two stages, however the STI regions 36 also act to divide and isolate active areas from one another and form cell boundaries between the cells at the block level. The STI regions forming cell boundaries straddle the border of two adjacent cells. The active areas include the diffusion 24,26 and gate areas 34. The supply nets 20,18 are supply connections between positive-channel 26 and negative-channel diffusion 24 and respective power rails 14,16 (VDD,VSS) . The supply nets may be configured along a boundary or an edge 39 of the cell. A boundary or edge 39 of the cell is defined by a continuous STI region 36 that straddles across two adjacent cells, at the block level, between power and ground rails 14,16. With this arrangement each cell may have at least one positive net and/or at least one negative net along an edge. Therefore adjacent cells may or may not have corresponding supply nets along bordering edges .
FIG. 2 shows a layout symbolic representation 70 of the row of logic cells of FIG. 1, however, cells with corresponding nets along an edge of bordering cells may be flipped about a y-axis (not shown) of the cell. The flipped cells 71,73,75 have edges with corresponding positive nets and negative nets of adjacent cells orientated to lie adjacent across the cell boundary of the adjacent cell 78. It will be appreciated that it may not be necessary to flip any cells, for example, adjacent cells may already have corresponding nets along the boundary 78. Additionally, FIG. 2 shows respective positive and negative net orientation, however, advantages of embodiments of the invention may be achieved with orientating the cells such that only the same net type (i.e. positive nets or alternatively the negative nets) of each adjacent cell lie along the edge of the boundary between the two cells.
FIG. 3 shows the cell row arrangement of FIG. 2 in accordance with an embodiment of the invention the area bound between the corresponding supply nets of the two adjacent cells are filled at the block level above the cells with additional diffusion 102. This filling of diffusion alters the overall diffusion profile of the adjacent cells. The two adjacent cells having an edge with corresponding NMOS (Vss) negative nets that lie on either side of the cell boundary form a continuous negative- channel diffusion 24. Nets 18,20 accordingly continue to interconnect diffusions 24,26 for each cell. It will be appreciated that the same process may be applied to the positive-channel 26 diffusion. In CMOS technology the advantages of filling the negative-channel diffusion of NMOS improves performance, however, the invention is not limited to filling only the negative-channel diffusion.
The additional diffusion 102 may be filled with various techniques known in the field, such as a dummy layer or abutment algorithm method, grow/shrink method, and the like. For example in the dummy layer approach, each cell is built, or modified such that a dummy mask layer is added in the region between the cell border, and the diffusion which connects to a Vss net. This will have a minimum width of "W", by virtue of manufacturing design rules. At the block level, when a dummy layer width is equal to ΛΛ2W" , then the dummy layer is replaced with diffusion fill. In the grow/shrink approach, at the block level all NMOS diffusion is grown in the horizontal direction by an amount ΛΛW" . All regions where a short circuit between different nets has occurred on diffusion, the area "shrinks" back to "W". All other areas that do not shrink to λλW" are diffusion fills between the same nets (such as Vss) across a cell boundary. It will be appreciated by a skilled reader that other techniques exist, and the dummy layer and grow/shrink approaches are provided as examples .
FIG. 4A-B shows schematic diagrams of a side view of NMOS regions of two adjacent cells in accordance with an embodiment of the invention. FIG. 4A shows the STI and active regions and the stress resulting from STI being a harder material than the diffusion regions (NMOS or PMOS) . The pushing force between the two materials creates stress which impacts the performance. By filling the STI region with diffusion, the stress is removed, as shown in FIG. 4B. Diffusion may be added where adjacent supply nets connected to the same power or ground. The diffusion fill is added between celll and cell2 at the block level of the IC, which is the next level up in the design hierarchy, above the cell level, and consists of multiple rows of such cells. FIG. 5A shows a flow chart of a method 300 in accordance with an embodiment of the invention. As discussed, a standard cell library is provided 310. The ASIC 315 is built from a cell, or more typically a collection of cells in the library. In building an integrated circuit such as ASIC (or block thereof) cells are interconnected to effect a specific function. Those cells may be arranged in an array of rows. When an ASIC block is built, using automated or custom place and route tools two adjacent cells are identified 320 along the row that have the same net, for example Vss, on diffusion on either side of a boundary between the two cells. The diffusion areas associated with the supply nets of the two cells are joined 330 such that the two adjacent cells that are identified with corresponding nets form a single continuous diffusion area. An additional step of flipping 352 a cell is optional (as indicated by dashed box) if the cell needs to be flipped so that the same net is on diffusion on either side of a boundary. FIG. 5B shows a flow chart of a method 350 in accordance with another embodiment that shares steps 320,330 and may also have the optional flipping step 352 as set out in the method of FIG. 5A. However, the method of FIG.5B begins with having the ASIC provided 305.
With a shared diffusion configuration, the active areas, i.e. negative and positive diffusion channels 24,26 have a longer continuous length than the arrangement of FIG. 1. A longer continuous diffusion channel length reduces the number interfaces occurring between active diffusion areas and STI regions along a row of cells. For example, for cells 33,35 in FIG. 1, the number of active diffusion area and STI region interactions is halved as shown in comparing FIG. 1 and 3. The reduction in the occurrences of stress between the STI regions and the active diffusion areas correlates with an improvement in performance .
An embodiment of the invention may be implemented with computer aided design (CAD) systems that are well known to a skilled person. Well known hardware description languages (HDL) , such as Very High Speed Integrated Circuit Hardware Description Language (VHDL) and VERILOG, both international standard languages of Institute of Electrical and Electronic Engineers, Inc. (IEEE), may be used to implement the invention to describe an ASIC, which is then synthesized into detailed logic functions comprising standard cells. An example of a tool to perform the synthesis is DESIGN COMPILER (DESIGN COMPILER is a trademark in certain countries of Synopsys, Inc. of Mountain View, California, United States of America) . The cell library may also be designed with modelling tools or logic schematic programs on a CAD system to create symbolic representations such as a layout of logic functions, for example, VIRTUOSO (VIRTUOSO is a trademark in certain countries of Cadence Design Systems, Inc., of San Jose, California, United States of America) . Of course, the ASIC may be built in rows of standard cells as mentioned above, or by other techniques known such as custom transistor level layout or the like. ASIC developers may use "place and route" (P&R) tools to flip the cells as required for increasing the applicability of the technique. The placement and routing tools generate the associated mask patterns to physically wire the standard cells in the manner required to implement the ASIC function. While placement tools provide initial placement of cells in a block or IC when the routing needs are estimated, routing tools are capable of moving cells from their initial placement once the routing needs are known. Examples of "place and route" tools that may be used are PHYSICAL COMPILER and ASTRO, respectively (PHYSICAL COMPILER and ASTRO are trademarks in certain countries of Synopsys, Inc.) . The hardware and software required to implement the invention, and indicated for explaining the preferred embodiment should not be limiting. Similarly, the software processes running on them may be arranged, configured or distributed in any manner suitable for performing the invention defined by the claims.
It will be understood that the block level diffusion fill method as described above provides advantages such as limiting the occurrence of stress between active areas and STI regions of the logic cells and improving overall performance. Additionally, embodiments may be applied to all types of ASICs, whether the ASIC is built from a collection of logic cells of a standard cell library (as discussed above) or from other techniques such as from full custom layout and the like. It will be appreciated that specific embodiments of the invention are discussed for illustrative purposes, and various modifications may be made without departing from the scope of the invention as defined by the appended claims.

Claims

What is claimed is:
1. A method for optimising transistor performance in an integrated circuit, comprising:
providing an integrated circuit having at least two cells, each cell having a logic function defined by the interconnection between active regions, non-active regions and power rails, each cell having an edge defined by a non-active regions each cell having a connection between an active diffusion region and a power rail;
identifying at least two adjacent cells each having a corresponding connection between an active region to the same power rail; and
joining the respective active regions associated with each corresponding connection of each cell with an additional diffusion area across the boundary between the cells forming the connected diffusion of the two adjacent cells.
2. The method of claim 1 wherein the active regions comprise a positive diffusion area, a negative diffusion area and a gate area.
3. The method of claim 2 wherein the connected diffusion is the negative diffusion area.
4. The method of claim 2 wherein the connected diffusion is the positive diffusion area.
5. The method of claim 2 wherein each negative diffusion area of each adjacent cell are connected and each positive diffusion area of each adjacent cell are connected.
6. The method of claim 1 wherein the corresponding connection is positioned along the edge of the cell forming a boundary between the two cells and the two corresponding connections .
7. The method of claim 1 further comprising reorientating a cell having a corresponding connection positioned along an edge, the cell being reoriented with the edge having the corresponding connection adjacent to and forming the boundary between the two cells for joining the diffusion areas.
8. The method of claim 1 wherein the non-active area is shallow trench isolation (STI) region.
9. The method of claim 1 wherein the active areas and non- active areas are comprised of materials having different physical properties.
10. The method of claim 1 wherein the joining step comprises applying a grow/shrink procedure to join the diffusion areas of each cell .
11. The method of claim 1 wherein the integrated circuit is an application specific integrated circuits (ASIC) having the cells arranged using synthesis and place and route tools into rows interconnected to effect the ASIC's function.
12. The method of claim 1 wherein the cells are standard cells .
13. The method of claim 1 wherein the integrated circuit is an application specific integrated circuits (ASIC) having cells arranged and interconnected using custom placement tools to effect the ASIC's function.
14. The method of claim 1 wherein the cells are custom transistor-level layout cells.
15. A method for building an integrated circuit having a connected diffusion cell architecture, comprising:
providing a logic cell library having at least one cell, each cell having a logic function defined by the interconnection between active regions, non-active regions and power rails, each cell having an edge defined by a non-active region, each cell having a connection between an active region and a power rail ;
placing cells from the logic cell library into the integrated circuit;
identifying at least two adjacent cells in the integrated circuit each having a corresponding connection between an active region to the same power rail; and joining the respective active regions associated with each corresponding connection of each cell with an additional diffusion area across the boundary between the cells forming the connected diffusion of the two adjacent cells.
16. The method of claim 15 wherein the active regions comprise a positive diffusion area, a negative diffusion area and a gate area.
17. The method of claim 16 wherein the connected diffusion is the negative diffusion area.
18. The method of claim 16 wherein the connected diffusion is the positive diffusion area.
19. The method of claim 16 wherein each negative diffusion area of each adjacent cell are connected and each positive diffusion area of each adjacent cell are connected.
20. The method of claim 15 wherein the corresponding connection is positioned along the edge of the cell forming a boundary between the two cells and the two corresponding connections .
21. The method of claim 15 further comprising reorientating a cell having a corresponding connection positioned along an edge, the cell being reoriented with the edge having the corresponding connection adjacent to and forming the boundary between the two cells for joining the diffusion areas.
22. The method of claim 15 wherein the non-active area is shallow trench isolation (STI) region.
23. The method of claim 15 wherein the active areas and non- active areas are comprised of materials having different physical properties.
24. The method of claim 15 wherein the joining step comprises applying a grow/shrink procedure to join the diffusion areas of each cell.
25. The method of claim 15 wherein the integrated circuit is an application specific integrated circuits (ASIC) having the cells arranged using synthesis and place and route tools into rows interconnected to effect the ASIC's function.
26. The method of claim 15 wherein the cells are standard cells.
27. The method of claim 15 wherein the integrated circuit is an application specific integrated circuits (ASIC) having cells arranged and interconnected using custom placement tools to effect the ASIC's function.
28. The method of claim 15 wherein the cells are custom transistor-level layout cells.
29. The method of claim 15 wherein the joining step comprises applying an abutment algorithm to join the diffusion areas of each cell.
30. An integrated circuit having a connected diffusion cell architecture, comprising:
at least two adjacent cells, each cell having a logic function defined by the interconnection between active regions, non- active regions and power rails, each cell having an edge defined by a non-active region, each cell having a connection between an active region and a power rail;
additional diffusion area across the boundary between the cells joining the respective active diffusion region associated with the corresponding connection of each cell forming the connected diffusion of the two adjacent cells.
31. The integrated circuit of claim 30 wherein the active regions comprise a positive diffusion area, a negative diffusion area and a gate area.
32. The integrated circuit of claim 31 wherein the connected diffusion is the negative diffusion area.
33. The integrated circuit of claim 31 wherein the connected diffusion is the positive diffusion area.
34. The integrated circuit of claim 31 wherein each negative diffusion area of each adjacent cell are connected and each positive diffusion area of each adjacent cell are connected.
35. The integrated circuit of claim 30 wherein the non-active area is shallow trench isolation (STI) region.
36. The integrated circuit of claim 30 wherein the active areas and non-active areas are comprised of materials having different physical properties.
37. The integrated circuit of any one of claim 30 wherein the cells are standard cells.
38. The integrated circuit of any one of claim 30 wherein the cells are custom transistor-level layout cells.
EP06709805A 2005-02-24 2006-02-17 Method for optimizing transistor performance in integrated circuits by diffusion sharing across cell boundaries Withdrawn EP1859373A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/067,200 US7266787B2 (en) 2005-02-24 2005-02-24 Method for optimising transistor performance in integrated circuits
PCT/GB2006/000568 WO2006090124A2 (en) 2005-02-24 2006-02-17 Method for optimizing transistor performance in integrated circuits by diffusion sharing across cell boundaries

Publications (1)

Publication Number Publication Date
EP1859373A2 true EP1859373A2 (en) 2007-11-28

Family

ID=36586191

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06709805A Withdrawn EP1859373A2 (en) 2005-02-24 2006-02-17 Method for optimizing transistor performance in integrated circuits by diffusion sharing across cell boundaries

Country Status (5)

Country Link
US (1) US7266787B2 (en)
EP (1) EP1859373A2 (en)
JP (1) JP5080280B2 (en)
TW (1) TWI417936B (en)
WO (1) WO2006090124A2 (en)

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8407634B1 (en) 2005-12-01 2013-03-26 Synopsys Inc. Analysis of stress impact on transistor performance
US7484198B2 (en) * 2006-02-27 2009-01-27 Synopsys, Inc. Managing integrated circuit stress using dummy diffusion regions
US8035168B2 (en) * 2006-02-27 2011-10-11 Synopsys, Inc. Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance
US7600207B2 (en) * 2006-02-27 2009-10-06 Synopsys, Inc. Stress-managed revision of integrated circuit layouts
US7767515B2 (en) * 2006-02-27 2010-08-03 Synopsys, Inc. Managing integrated circuit stress using stress adjustment trenches
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US7888705B2 (en) 2007-08-02 2011-02-15 Tela Innovations, Inc. Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US7620926B1 (en) * 2007-03-20 2009-11-17 Xilinx, Inc. Methods and structures for flexible power management in integrated circuits
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
MY152456A (en) 2008-07-16 2014-09-30 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
JP5147654B2 (en) 2008-11-18 2013-02-20 パナソニック株式会社 Semiconductor device
US8362622B2 (en) * 2009-04-24 2013-01-29 Synopsys, Inc. Method and apparatus for placing transistors in proximity to through-silicon vias
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
JP2011138915A (en) * 2009-12-28 2011-07-14 Elpida Memory Inc Semiconductor device, and layout design apparatus of the semiconductor device
US8898614B2 (en) * 2010-04-19 2014-11-25 Freescale Semiconductor, Inc. Integrated circuit device with reduced leakage and method therefor
US9312260B2 (en) 2010-05-26 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits and manufacturing methods thereof
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8473888B2 (en) * 2011-03-14 2013-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. Systems and methods of designing integrated circuits
US9817928B2 (en) 2012-08-31 2017-11-14 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
US9190346B2 (en) 2012-08-31 2015-11-17 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
US8836040B2 (en) 2012-11-07 2014-09-16 Qualcomm Incorporated Shared-diffusion standard cell architecture
US9379018B2 (en) 2012-12-17 2016-06-28 Synopsys, Inc. Increasing Ion/Ioff ratio in FinFETs and nano-wires
US8847324B2 (en) 2012-12-17 2014-09-30 Synopsys, Inc. Increasing ION /IOFF ratio in FinFETs and nano-wires
US9563731B2 (en) * 2013-03-15 2017-02-07 Taiwan Semiconductor Manufacturing Co., Ltd. Cell boundaries for self aligned multiple patterning abutments
US8904322B2 (en) * 2013-03-26 2014-12-02 International Business Machines Corporation Structure for stacked CMOS circuits
KR102083388B1 (en) * 2013-09-24 2020-03-02 삼성전자주식회사 Semiconductor device and method of forming the same
KR102152772B1 (en) * 2013-11-18 2020-09-08 삼성전자 주식회사 Layout design system, layout design method, and semiconductor device fabricated by using the same
US9122823B2 (en) 2013-12-20 2015-09-01 International Business Machines Corporation Stacked multiple-input delay gates
KR102173638B1 (en) 2014-10-01 2020-11-04 삼성전자주식회사 Semiconductor device and method of forming the same
US9940424B2 (en) * 2016-05-25 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Systems and methods for minimum-implant-area aware detailed placement
US10366196B2 (en) 2016-06-22 2019-07-30 Qualcomm Incorporated Standard cell architecture for diffusion based on fin count
US9761712B1 (en) * 2016-10-31 2017-09-12 International Business Machines Corporation Vertical transistors with merged active area regions
US9978682B1 (en) * 2017-04-13 2018-05-22 Qualcomm Incorporated Complementary metal oxide semiconductor (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4700316A (en) 1985-03-01 1987-10-13 International Business Machines Corporation Automated book layout in static CMOS
JPH0442560A (en) * 1990-06-08 1992-02-13 Nec Corp Standard cell
US5701255A (en) 1994-09-14 1997-12-23 Matsushita Electric Industrial Co., Ltd. Cell generation method and cell generation system
US6163877A (en) 1996-11-05 2000-12-19 Intel Corporation Method and apparatus for optimizing transistor cell layout with integrated transistor folding
US6393601B1 (en) 1997-04-14 2002-05-21 Matsushita Electric Industrial Co., Ltd. Layout designing apparatus for integrated circuit, transistor size determining apparatus, circuit characteristic evaluating method, and transistor size determining method
JP3819186B2 (en) 1999-09-22 2006-09-06 株式会社東芝 Standard cell, semiconductor integrated circuit and layout method thereof
US6912703B2 (en) * 2001-03-19 2005-06-28 Taiwan Semiconductor Manufacturing Company Structure of integrated circuit standard cell library for reducing power supply voltage fluctuation
KR100374301B1 (en) * 2001-03-24 2003-03-03 동부전자 주식회사 Method for fabricating shallow trench isolation
WO2002099884A2 (en) * 2001-06-01 2002-12-12 Virtual Silicon Technology, Inc. Integrated circuit design with library cells
US6762092B2 (en) * 2001-08-08 2004-07-13 Sandisk Corporation Scalable self-aligned dual floating gate memory cell array and methods of forming the array
JP3976089B2 (en) * 2002-08-09 2007-09-12 株式会社リコー Semiconductor integrated circuit device and manufacturing method thereof
JP3790202B2 (en) * 2002-09-24 2006-06-28 松下電器産業株式会社 Power supply wiring method for semiconductor integrated circuit and semiconductor integrated circuit
US6938226B2 (en) * 2003-01-17 2005-08-30 Infineon Technologies Ag 7-tracks standard cell library
US7235838B2 (en) * 2004-06-30 2007-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device substrate with embedded capacitor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2006090124A3 *

Also Published As

Publication number Publication date
WO2006090124A3 (en) 2006-10-12
JP5080280B2 (en) 2012-11-21
TW200710925A (en) 2007-03-16
US7266787B2 (en) 2007-09-04
TWI417936B (en) 2013-12-01
JP2008532275A (en) 2008-08-14
US20060186478A1 (en) 2006-08-24
WO2006090124A2 (en) 2006-08-31

Similar Documents

Publication Publication Date Title
US7266787B2 (en) Method for optimising transistor performance in integrated circuits
US20060190893A1 (en) Logic cell layout architecture with shared boundary
US7287237B2 (en) Aligned logic cell grid and interconnect routing architecture
US8314635B2 (en) Methods for forming programmable transistor array comprising basic transistor units
US6308309B1 (en) Place-holding library elements for defining routing paths
US8276109B2 (en) Mixed-height high speed reduced area cell library
US6006024A (en) Method of routing an integrated circuit
US5987086A (en) Automatic layout standard cell routing
US6209123B1 (en) Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors
Chiluvuri et al. Layout-synthesis techniques for yield enhancement
US8230380B2 (en) High speed reduced area cell library with cells having integer multiple track heights
JPH0527981B2 (en)
CN103594422A (en) Layout circuit optimization for deep submicron technologies
Kim et al. Design quality trade-off studies for 3-D ICs built with sub-micron TSVs and future devices
US20220327275A1 (en) Multiplexer
US7062739B2 (en) Gate reuse methodology for diffused cell-based IP blocks in platform-based silicon products
US7725870B2 (en) Method for radiation tolerance by implant well notching
TWI771698B (en) Multiplexer circuit, multiplexer and method for manufacturing multiplexer
Sherlekar Design considerations for regular fabrics
CN103178016A (en) Methods of forming gate structures for reduced leakage
Ku et al. Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity
Moraes et al. A virtual CMOS library approach for fast layout synthesis
Kaur et al. Power estimation analysis for CMOS cell structures
Moraes et al. An Efficient Layout Style for Three-Metal CMOS Macro-Cells
US20090045840A1 (en) Method for Radiation Tolerance by Logic Book Folding

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20071008

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

R17P Request for examination filed (corrected)

Effective date: 20071008

DAX Request for extension of the european patent (deleted)
17Q First examination report despatched

Effective date: 20071008

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: NVIDIA TECHNOLOGY UK LIMITED

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20150901