EP1853016A1 - High-throughput scheduler with guaranteed fairness for wireless networks and other applications - Google Patents

High-throughput scheduler with guaranteed fairness for wireless networks and other applications Download PDF

Info

Publication number
EP1853016A1
EP1853016A1 EP07250442A EP07250442A EP1853016A1 EP 1853016 A1 EP1853016 A1 EP 1853016A1 EP 07250442 A EP07250442 A EP 07250442A EP 07250442 A EP07250442 A EP 07250442A EP 1853016 A1 EP1853016 A1 EP 1853016A1
Authority
EP
European Patent Office
Prior art keywords
eligible
scheduling
scheduler
transmission elements
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07250442A
Other languages
German (de)
English (en)
French (fr)
Inventor
Christopher W. Hamilton
Noy C. Kucuk
Jinhui Li
Christine E. Severns-Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Agere Systems LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems LLC filed Critical Agere Systems LLC
Publication of EP1853016A1 publication Critical patent/EP1853016A1/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/622—Queue service order
    • H04L47/623—Weighted service order
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/622—Queue service order
    • H04L47/6225—Fixed service order, e.g. Round Robin
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L65/00—Network arrangements, protocols or services for supporting real-time applications in data packet communication
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/50—Allocation or scheduling criteria for wireless resources
    • H04W72/52—Allocation or scheduling criteria for wireless resources based on load

Definitions

  • the present invention relates generally to the field of telecommunications, and more particularly to schedulers used to control access to limited resources.
  • a scheduler is used to resolve contention among multiple tasks competing for a limited resource.
  • a scheduler is commonly used in a network processor to schedule multiple traffic flows for transmission over a specific transmission bandwidth.
  • a network processor generally controls the flow of data between a physical transmission medium, such as a physical layer portion of a network, and a switch fabric in a router or other type of switch.
  • An important function of a network processor involves the scheduling of cells, packets or other data blocks, associated with the multiple traffic flows, for transmission to the switch fabric from the physical transmission medium of the network and vice versa.
  • the network processor scheduler performs this function.
  • a good scheduler should also be fair. For example, it may allocate the bandwidth according to the weights of the users, with the higher-priority users getting more bandwidth than lower-priority users.
  • WRR Weighted Round-Robin
  • F be the sum of the weights W i for the N users.
  • F timeslots as one frame, such that F is the frame size in timeslots.
  • WRR serves U i for exactly W i timeslots in each frame. Therefore, each user gets their fair share of the frame. For example, assume there are four users U 1 , U 2 , U 3 and U 4 that have the weights of 4, 3, 2, and 1, respectively. Then the scheduler can serve these four users by repeating the following sequence per frame: U 1 , U 2 , U 3 , U 4 , U 1 , U 2 , U 3 , U 1 , U 2 , U 1 . There are ten timeslots in one frame, and U 1 can get four timeslots in each frame.
  • WRR WRR would serve the users as follows: U 1 , U 2 , U 3 , U 4 , U 5 , U 6 , U 7 , U 8 , U 9 , U 10 , U 11 , U 1 , U 1 , U 1 , U 1 , U 1 , U 1 , U 1 , U 1 , U 1 , U 1 , U 1 , U 1 , U 1 , U 1 , U 1 , U 1 .
  • the service received by U 1 is very bursty. This is clearly not desirable in telecommunication systems, because long burstiness could overflow the buffers of user communication devices. Such burstiness becomes increasingly problematic in those practical applications in which the total number of users may be several hundreds or more.
  • a frame mapping scheduler that provides simplicity and fairness comparable to that of WRR, but without the burstiness problem commonly associated with WRR. More specifically, a frame mapping scheduler in the illustrative embodiment described therein comprises scheduling circuitry which utilizes a weight table and a mapping table.
  • the weight table comprises a plurality of entries, with each of the entries identifying a particular one of the transmission elements.
  • the mapping table comprises at least one entry specifying a mapping between a particular timeslot of a frame and an entry of the weight table.
  • the scheduling circuitry determines a particular transmission element to be scheduled in a given timeslot by accessing a corresponding mapping table entry and utilizing a resultant value to access the weight table.
  • the mapping table entries may be predetermined in accordance with a golden ratio policy, or other type of policy.
  • mapping table memory be arranged "on-chip," that is, on the same integrated circuit as the scheduler, so as to reduce access times. For example, such an arrangement is beneficial in network processing applications in which data blocks may need to be processed substantially in real time.
  • Examples of scheduling algorithms utilized in the wireless network context include the above-described WRR scheduling algorithm and its unweighted counterpart round robin (RR), maximum carrier-to-interference ratio (Max C/I), Proportional Fairness (PF) and Modified Largest Weighted Delay First (M-LWDF).
  • RR round robin
  • Max C/I maximum carrier-to-interference ratio
  • PF Proportional Fairness
  • M-LWDF Modified Largest Weighted Delay First
  • a drawback of the RR scheduling algorithm is that it does not consider the channel conditions. Instead, the RR scheduling algorithm simply schedules backlogged users one by one, with the first user being assigned to the first timeslot, the second user being assigned to the second timeslot, and so on, regardless of their respective channel capacities. Such an approach is fair, because in a given set ofN timeslots, each ofN users has exactly one chance to be served. However, the throughput of the RR algorithm is poor, because it does not check the channel capacities before it makes the scheduling decisions. The WRR scheduling algorithm similarly fails to take channel capacities into account in its scheduling decisions.
  • the Max C/I scheduling algorithm selects for a given timeslot the user that has the best channel capacity. Although this approach can achieve the maximum overall throughput, its fairness performance is very poor. For example, if the wireless link of a given mobile user is constantly weak, that user is not likely to be scheduled.
  • the PF scheduling algorithm selects the user that has the maximum r i / R i , where r i is the channel capacity of user i and R i is the average rate received by user i .
  • the algorithm updates R i adaptively.
  • R i is the average rate received by user i .
  • Additional details regarding the PF scheduling algorithm can be found in, for example, A. Jalali et al., "Data throughput of CDMA-HDR a high efficiency high data rate personal communication wireless system," in Proc. of IEEE VTC 2000, pp. 1854-1858, May 2000 .
  • the fairness of the PF scheduling algorithm is better than that of the Max C/I scheduling algorithm, but not as good as that of the RR or WRR scheduling algorithms. Also, the PF scheduling algorithm cannot provide guaranteed fairness.
  • the M-LWDF scheduling algorithm gives higher priorities to the users that have longer waiting times. However, like the above-described PF scheduling algorithm, it fails to provide guaranteed fairness.
  • Max C/I, PF and M-LWDF scheduling algorithms provide better throughput than the RR and WRR scheduling algorithms in the wireless context by sacrificing fairness.
  • What is needed is an improved scheduling algorithm which is able to provide a better balance between throughput and fairness, particularly in wireless network applications.
  • the present invention in one or more illustrative embodiments provides wireless scheduling algorithms that improve the throughput of conventional RR and WRR scheduling algorithms without sacrificing the fairness.
  • a scheduler is adapted to schedule packets or other data blocks for transmission from a plurality of transmission elements in timeslots of a frame in a communication system.
  • the scheduler In scheduling for a given frame, the scheduler initially designates each of the transmission elements as eligible to transmit one or more data blocks in the given frame, and selects from among those of the transmission elements designated as eligible at least one of the transmission elements for scheduling in a next available timeslot of the given frame. The scheduler then adjusts the eligibility status of the selected transmission element(s), and repeats the selecting and adjusting operations for one or more remaining timeslots of the given frame.
  • the eligibility status for a given selected transmission element may be adjusted, for example, by designating the given selected transmission element as ineligible to transmit any additional data blocks in the given frame.
  • a first illustrative embodiment provides a modified RR scheduling algorithm also referred to herein as a Wireless RR (WiRR) scheduling algorithm.
  • the eligibility status for a given selected transmission element comprises a binary eligibility indicator having an eligible state and an ineligible state, and the eligibility status is adjusted by changing the binary eligibility indicator for that element from the eligible state to the ineligible state.
  • the given selected transmission element is served in a timeslot of the given frame, it is considered ineligible for service in any subsequent timeslots of that frame.
  • the process is repeated for additional frames, and for each new frame the transmission elements are all initially designated as eligible to transmit one or more data blocks in that frame.
  • a second illustrative embodiment provides a weighted version of the WiRR scheduling algorithm.
  • the eligibility status for a given selected transmission element comprises an eligible number, and the eligibility status of the given selected transmission element is adjusted by decreasing its eligible number. When the eligible number of any of the transmission elements reaches zero, that transmission element is considered ineligible for service in any subsequent timeslots of the frame.
  • the initially designated eligible numbers for the respective transmission elements may comprise, for example, weights assigned to the respective transmission elements.
  • a new transmission element may be added to the plurality of transmission elements previously designated as eligible to transmit one or more data blocks in the given frame.
  • the scheduler in an illustrative embodiment may be implemented in a network processor integrated circuit or other processing device of the communication system, using a wide variety of different arrangements of scheduling circuitry.
  • the invention will be illustrated herein in conjunction with exemplary wireless networks and other types of communication systems.
  • the exemplary systems include respective schedulers configured in a particular manner in order to illustrate the techniques of the invention. It should be understood, however, that the invention is more generally applicable to any communication system scheduler in which it is desirable to provide improved throughput without adversely impacting fairness. For example, guaranteed fairness levels comparable to those associated with conventional RR or WRR scheduling algorithms may be provided.
  • FIG. 1 shows a simplified diagram of a communication system 100 in accordance with an illustrative embodiment of the invention.
  • the system 100 comprises a scheduler 102 coupled to a transmitter 104 and a channel status element 106.
  • the scheduler is coupled to transmission elements which in this embodiment comprise respective queues 110-1,110-2, ... 110-N for respective ones of N users.
  • the N users are mobile users of a wireless network of the system 100, and are associated with respective mobile user devices 112-1, 112-2, ... 112-N which communicate with transmitter 104 in a conventional manner.
  • the transmitter 104 may comprise, for example, at least a portion of a base station or access point of the wireless network.
  • the wireless network is configured for communication of packets or other arrangements of data between transmitter 104 and the mobile user devices 112. All such arrangements of data are intended to be encompassed by the general term "data block" as used herein. It is to be appreciated that the invention does not require any particular size or configuration of data blocks. For simplicity and clarity of illustration, the diagram shows only the downlink communication between transmitter 104 and the mobile user devices 112, although it is to be appreciated that similar techniques may be used for other types of transmission.
  • the system 100 in this embodiment maintains one queue 110 for each mobile user 112, although other types of queuing arrangements may be used.
  • Downlink transmissions are assumed to occur in timeslots of a frame.
  • the scheduler 102 serves one or more of the users.
  • the scheduler in this embodiment is assumed to have knowledge of the wireless channel capacities associated with the respective mobile users. This knowledge may be provided to the scheduler by the channel status element 106, or using other techniques. As indicated previously, the channel capacities associated with the mobile users are typically time varying and difficult to predict.
  • the scheduler bases its scheduling decisions on the actual measured channel conditions and other parameters, as will be described in greater detail below in conjunction with FIGS. 3 through 5. For a given timeslot, the scheduler selects one or more of the user queues 110 which will each be scheduled to transmit a packet during that timeslot. A given packet is transmitted via transmitter 104 to the corresponding one of the mobile user devices 112.
  • the system 100 of FIG. 1 may be implemented, for example, as an otherwise conventional Universal Mobile Telecommunications System (UMTS) or Wideband Code Division Multiple Access (WCDMA) wireless cellular communication system.
  • system 100' as shown in FIG. 2 comprises a radio network controller (RNC) 120 coupled to base stations 122, 124 and 126 as shown.
  • RNC radio network controller
  • the base stations 122, 124 and 126 are referred to as Node B elements in accordance with well-known UMTS and WCDMA nomenclature.
  • These elements communicate with the mobile user devices 112, which are referred to as user equipment (UE) elements in the UMTS and WCDMA context.
  • UE user equipment
  • UMTS or WCDMA system 100' may be incorporated in the RNC 120, or may be replicated in each of the Node B elements 122, 124 and 126.
  • a scheduler is typically arranged in each Node B element so as to permit fast scheduling.
  • the above-noted HSDPA capability uses timeslots referred to as transmission time intervals (TTIs), and one or more users can be served within each TTI.
  • TTIs transmission time intervals
  • the HSDPA feature can be provided in a frequency division duplex (FDD) mode or a time division duplex (TDD) mode.
  • FDD frequency division duplex
  • TDD time division duplex
  • a given TTI has a duration of 2 milliseconds (ms)
  • ms milliseconds
  • a given TTI could be 5 ms or 10 ms.
  • the communication system channel typically used in HSDPA to send data to the UEs from a given Node B is referred to as the high speed downlink shared channel (HS-DSCH).
  • HS-DSCH high speed downlink shared channel
  • scheduler 102 as described below will be assumed to serve a single user per timeslot, but it should be understood that the described techniques can be extended in a straightforward manner to accommodate HSDPA and other arrangements in which multiple users can be scheduled in a single timeslot.
  • FIGS. 1 and 2 are by way of illustrative example only. More specifically, as previously noted, the invention can be implemented in any type of wireless network or other communication system, and is not limited to any particular communication application.
  • the scheduler 102 is configured to schedule packets or other data blocks for transmission from the user queues 110 in timeslots of one or more frames.
  • the scheduler initially designates each of the queues 110 as eligible to transmit a packet in a given frame, and then selects from the queues designated as eligible a particular one of the queues for scheduling in a next available timeslot. After that queue has been scheduled, its eligibility status is adjusted, and the selection and adjustment operations are repeated for the remaining timeslots of the given frame.
  • a scheduling algorithm referred to herein as a modified RR or Wireless RR (WiRR) scheduling algorithm
  • WiRR Wireless RR
  • the scheduler 102 may be implemented at least in part in the form of an integrated circuit, as will be described in greater detail below.
  • Such an integrated circuit may comprise a network processor or other type of processor or processing device that is implemented in a given communication system element, such as a base station or access point associated with transmitter 104 in the FIG. 1 system, or an RNC or Node B element in the FIG. 2 system.
  • the scheduler 102 may be, for example, a frame mapping scheduler, of the type described in the above-cited U.S. Patent Application Serial Nos. 10/903,954 and 10/998,686 .
  • the use of these techniques can substantially reduce the amount of memory required to store a mapping table for a golden ratio policy or any other policy that requires a stored mapping table.
  • scheduling techniques of the present invention may also or alternatively be used in conjunction with a flexible scheduler architecture capable of supporting multiple scheduling algorithms, such as that disclosed in the above-cited U.S. Patent Application Serial No. 10/722,933 .
  • This scheduling algorithm has the same fairness as the conventional RR scheduling algorithm described previously, but substantially better throughput.
  • step 300 the scheduling process begins for a new frame.
  • all N users are initially designated as being eligible to transmit a packet in that frame.
  • the users thus have respective eligibility statuses, each of which may comprise, for example, a binary eligibility indicator having an eligible state and an ineligible state. With such a binary eligibility indicator, a given user is either eligible or not eligible.
  • step 302 for the next available timeslot of the frame, the scheduler 102 selects from among all the users that are backlogged and eligible, the user that has the best channel capacity. Users are assumed to be backlogged if they have at least one packet to transmit. With reference to the diagram of FIG. 1, it can be seen that each of the users illustrated, namely, users 1, 2, 3 and N, is backlogged in that each has at least one packet in its associated queue. Users that are not backlogged in the current timeslot may be removed from consideration in the scheduling process for that timeslot, as will be appreciated by those skilled in the art. However, users that are not backlogged in the current timeslot may become backlogged in the next timeslot, and so removing such users from consideration in scheduling the current timeslot should not be construed as removing them from consideration for the remainder of the frame.
  • the "best" channel capacity referred to in step 302 is generally assumed to be the highest channel capacity of the backlogged and eligible users, although a wide variety of measures may be used to select from among the backlogged and eligible users, as will be described in greater detail below.
  • step 304 the selected user is served in the available timeslot and the eligibility status of that user is then adjusted.
  • the selected user is "served" in this example by scheduling a packet from the corresponding user queue 110 for transmission in the available timeslot.
  • the eligibility status of the selected user is adjusted by setting its status to ineligible. Thus, the selected user will not be served again in the current frame.
  • FIG. 5 As will be described in conjunction with FIG. 5 below, other types of eligibility status adjustment may be used in other embodiments.
  • step 306 a determination is made as to whether any further backlogged and eligible users are available for scheduling. If not, the process returns to step 300, at which point all users are again set to eligible status without regard to their previous selection, and the process begins again for a new frame. However, if there are additional backlogged eligible users, the process returns to step 302 to schedule one or more of those users in additional timeslots of the current frame.
  • one frame will be equal to N timeslots. As indicated above, a user is considered backlogged when its corresponding one of the queues 110 is not empty. If some of the N users are not backlogged, the frame length will be less than N.
  • the best channel capacity may be the best absolute capacity or the best relative capacity, where again “best” generally denotes “highest.”
  • Absolute capacity, r i is the channel capacity to user i , measured in bits per second.
  • Relative capacity can be defined as r i l r i , where r i is the average channel capacity of user i .
  • the relative capacity may be defined as r ; / R i , where R i is the average rate received by user i , similar to the definition used in the PF scheduling algorithm described previously.
  • the averages r i and R i can be updated adaptively. When two or more users have the same channel capacity, the tie can be broken randomly, or the user with the smaller index i can be selected.
  • Another technique for dealing with such ties is to serve the users simultaneously in the given timeslot.
  • Techniques for scheduling multiple users in a given timeslot via assignment of different HSDPA codes to those users are described in the above-cited U.S. Patent Application Attorney Docket No. Hamilton 5-1-3-2.
  • the WiRR scheduling algorithm illustrated in FIG. 3 advantageously provides guaranteed fairness by ensuring that all backlogged users will be served once in each frame.
  • its fairness is as good as that provided by the conventional RR scheduling algorithm.
  • it provides much better throughput than the conventional RR scheduling algorithm.
  • the number in the table are the channel capacities for each of the users for each of four timeslots, denoted Slot 1, Slot 2, Slot 3 and Slot 4, in each of two frames, denoted Frame 1 and Frame 2. It is assumed for this example that all four of the users are backlogged.
  • the user channel capacity entries for the various frames and slots are presented in cells that are unshaded, lightly shaded or darkly shaded. For a given frame and slot, unshaded cells indicate the users, if any, that are eligible but not selected, while the selected eligible user is indicated by a lightly shaded cell, and the ineligible users, if any, are indicated by darkly shaded cells.
  • the WiRR scheduling algorithm as implemented by scheduler 102 proceeds in this example such that in Slot 1 of Frame 1, all four users are eligible, and User 2 with a channel capacity of 9 is selected for service.
  • Slot 2 of Frame 1 the previously-selected User 2 is no longer eligible, and User 3 with a channel capacity of 7 is selected from the eligible set of three users.
  • Slot 3 of Frame 1 the previously-selected User 2 and User 3 are no longer eligible, and User 1 with a channel capacity of 6 is selected from the eligible set of two users.
  • Slot 4 of Frame 1 the only eligible user is User 4, with a channel capacity of 5, and that user is selected.
  • the process then starts the scheduling for the next frame, Frame 2, and all four users are again designated as eligible for scheduling in that frame.
  • the order of user selection for Slots 1 through 4 of Frame 2 is User 3, User 2, User 1 and User 4, as shown.
  • a simulation performed on the above-described WiRR scheduling algorithm indicates that its throughput performance is comparable to that of the conventional Max C/I scheduling algorithm.
  • N 50.
  • the channel capacities of the users were assumed to be uncorrelated random processes with uniform distributions. It was also assumed that all of the users were always backlogged.
  • the simulation results in terms of throughput performance for WiRR and conventional RR and Max C/I scheduling algorithms are shown in TABLE 1 below. It can be seen that the Max C/I scheduling algorithm has a throughput of nearly 100%, while the RR scheduling algorithm has a throughput of only 50%.
  • the WiRR scheduling algorithm has a throughput performance of 95.6%.
  • the weight assigned to user i is denoted w i .
  • an eligibility status referred to herein as an "eligible number.”
  • the eligible number for user i is denoted e i .
  • step 500 the scheduling process begins for a new frame.
  • all N users are initially designated as being eligible to transmit a packet in that frame.
  • their eligibility statuses comprise respective eligible numbers e i that are initially set to respective weights w i , for all i .
  • step 502 for the next available timeslot of the frame, the scheduler 102 selects from among all the users that are backlogged and have positive eligible numbers, the user that has the best channel capacity.
  • step 504 the selected user is served in the available timeslot and the eligibility status of that user is then adjusted.
  • the selected user is "served" in this example by scheduling a packet from the corresponding user queue 110 for transmission in the available timeslot.
  • step 506 a determination is made as to whether any further backlogged and eligible users are available for scheduling. If not, the process returns to step 500, at which point all users again have their eligible numbers set to their respective assigned weights without regard to their previous selection, and the process begins again for a new frame. However, if there are additional backlogged eligible users, the process returns to step 502 to schedule one or more of those users in additional timeslots of the current frame.
  • the selection step can use any of a number of different measures, including by way of example, highest absolute capacity or relative capacity.
  • the relative capacity can be defined as r i l r i or w i r i / R i , where as noted above r i is the average channel capacity of user i , and R i is the average rate received by user i .
  • the weighted version of WiRR as described above provides guaranteed fairness that is comparable to that of the conventional WRR scheduling algorithm. Its throughput performance is expected to be better than that of conventional WRR.
  • the scheduler 102 may be configured to handle users removed or added during a given frame. For users that are removed, the scheduler can simply designate those users as ineligible or otherwise eliminate the users from consideration in the scheduling process. For new users that are added, the scheduler can, by way of example, wait until a new frame starts, or set the eligible number or other eligibility status of the new user proportionally, randomly or using other techniques.
  • the scheduling algorithms described in conjunction with the illustrative embodiments above provide improved throughput performance without sacrificing fairness. Simulations show that the throughput of the WiRR scheduling algorithm is very high.
  • the weighted version of the WiRR scheduling algorithm provides improved throughput relative to a conventional WRR scheduling algorithm.
  • its fairness performance which is as good as that of WRR, is guaranteed.
  • Other advantages include lower burstiness relative to conventional WRR.
  • a scheduling algorithm is implemented in a scheduler of a network processor.
  • a network processor may be used in systems comprising wireless networks as shown in FIGS. 1 and 2, but can also be used in other types of systems, such as the communication system 600 shown in FIG. 6.
  • the system 600 includes a network processor 602 having an internal memory 604.
  • the network processor 602 is coupled to an external memory 606 as shown, and is configured to provide an interface for communicating packets or other arrangements of data between a network 608 and a switch fabric 610. As noted previously, all such arrangements of data are intended to be encompassed by the general term "data block" as used herein.
  • the network 608 may be a wireless network, corresponding to a portion of one of the wireless networks in the systems of FIGS. 1 and 2, while the network processor 602 and switch fabric 610 may be implemented in base stations, network controllers or other elements such systems.
  • the network processor 602 and its associated external memory 606 may be implemented, e.g., as one or more integrated circuits installed on a line card or port card of a router, switch or other system element.
  • FIG. 7 illustrates an example line card embodiment of a portion of the system 600 of FIG. 6.
  • the system comprises a line card 700 having at least one integrated circuit 702 installed thereon.
  • the integrated circuit 702 comprises network processor 602 which has internal memory 604.
  • the network processor 602 interacts with external memory 606 on the line card 700.
  • the external memory 606 may serve, e.g., as an external static random access memory (SRAM) or dynamic random access memory (DRAM) for the network processor integrated circuit 702.
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • Such memories may be configured in a conventional manner.
  • a suitable host processor may also be installed on the line card 700, and used for programming and otherwise controlling the operation of one or more network processor integrated circuits on the line card 700.
  • FIGS. 6 and 7 The portion of the communication system as shown in FIGS. 6 and 7 is considerably simplified for clarity of illustration. It is to be appreciated, however, that the system may comprise a router, switch or other element which includes multiple line cards such as that shown in FIG. 7, and that each of the line cards may include multiple integrated circuits. A similar embodiment may be implemented in the form of a port card. However, the invention does not require such card-based implementation in a router, switch or other element.
  • FIGS. 6 and 7 are by way of illustrative example only. More specifically, as previously noted, the invention can be implemented in any type of processor or other communication system processing device, and is not limited to any particular network-based processing application.
  • processor as the term is used herein may be implemented, by way of example and without limitation, utilizing elements such as those commonly associated with a microprocessor, central processing unit (CPU), digital signal processor (DSP), application-specific integrated circuit (ASIC), or other type of data processing device, as well as portions and combinations of such elements.
  • CPU central processing unit
  • DSP digital signal processor
  • ASIC application-specific integrated circuit
  • system 600 and network processor 602 as illustrated in FIGS. 6 and 7 may include other elements in addition to or in place of those specifically shown, including one or more elements of a type commonly found in a conventional implementation of such a system and network processor.
  • the network processor may include a classifier, queuing and dispatch logic, one or more memory controllers, interface circuitry for interfacing the network processor with the network 608, the switch fabric 610, a host processor or other external device(s), as well as other conventional elements not explicitly shown in the figure.
  • the network processor may include a classifier, queuing and dispatch logic, one or more memory controllers, interface circuitry for interfacing the network processor with the network 608, the switch fabric 610, a host processor or other external device(s), as well as other conventional elements not explicitly shown in the figure.
  • the functionality of the network processor 602 as described herein may be implemented at least in part in the form of software program code.
  • elements associated with the performance of scheduling operations in the network processor may be implemented at least in part utilizing elements that are programmable via instructions or other software that may be supplied to the network processor via an external host processor or other suitable mechanism.
  • information characterizing particular scheduling algorithms, or associated traffic shaping information may be supplied to the network processor from the associated host processor or other suitable mechanism.
  • FIG. 8 shows a more detailed view of the network processor 602 in an illustrative embodiment of the invention.
  • the network processor 602 in this embodiment includes a scheduler 800, transmit queues 802, a traffic shaper 804, a weight table 810, and a mapping table 812.
  • the scheduler 800 schedules data blocks associated with the transmit queues 802 for transmission over one or more transmission media which are not explicitly shown.
  • the scheduling utilizes the weight table 810 and mapping table 812, in conjunction with traffic shaping information from the traffic shaper 804 or without such information, in scheduling the data blocks associated with the transmit queues 802 for transmission.
  • the network processor 602 may include additional elements, for example, of a type described in the above-cited U.S. patent applications, or of a conventional type known to those skilled in the art, and such elements, being described elsewhere, are not further described herein.
  • the weight table 810 and mapping table 812 may be stored at least in part in the internal memory 604 of the network processor 602, and may also or alternatively be stored at least in part in the external memory 606 of the network processor 602. When stored using internal memory, at least a portion of such memory may be internal to the scheduler 800 or other scheduling circuitry.
  • scheduler 800 may include or otherwise have associated therewith a number of additional timeslot tables or other types of table elements suitable for use in static or dynamic table-based scheduling of a type described in the above-cited U.S. patent applications, or of a type known in conventional practice.
  • the transmit queues 802 may be viewed as comprising a plurality of transmission elements.
  • the transmit queues may comprise a plurality of transmission queues and associated control logic, with each of the transmission queues corresponding to a transmission element.
  • transmission element as used herein is intended to be construed more generally so as to encompass any source of one or more data blocks, or other elements that are schedulable for transmission in the network processor 602.
  • Packets or other data blocks can be enqueued in transmission elements of the transmit queues 802 from an associated network processor data path, not explicitly shown in the figure. This may occur in conjunction with packet enqueue messages and associated data blocks received from such a data path. Similarly, packets or other data blocks can be dequeued from the transmission elements to the data path upon transmission, for example, in conjunction with packet dequeue messages and associated data blocks being sent to the data path.
  • the traffic shaper 804 may be implemented, by way of example, as an otherwise conventional traffic shaping engine which establishes one or more traffic shaping requirements, in a known manner, for the transmission of the data blocks from the transmission elements of the transmit queues 802.
  • the traffic shaper 804 may receive information regarding queue and scheduler status from the transmit queues 802 via the scheduler 800.
  • the traffic shaper may generate traffic shaping information such as queue transmission interval and prioritization for establishing a class of service (CoS) or other desired service level for one or more of the transmission elements or their corresponding network connections.
  • CoS class of service
  • the transmission elements may comprise queues.
  • the present invention can be used to schedule any type of elements for which data blocks are to be transmitted, and more generally any type of schedulable elements in a communication system processing device.
  • Such elements are intended to be encompassed by the general term "transmission elements" as used herein, and may also be referred to herein as "users.”
  • the scheduler 800 in the FIG. 8 embodiment is configured to implement a scheduling algorithm such as the above-noted WiRR scheduling algorithm or its weighted version.
  • scheduling circuitry may include one or more tables or other arrangements of one or more of hardware, software and firmware capable of implementing the scheduling techniques described herein.
  • the weight table 810 and the mapping table 812 or suitable portions thereof may be at least partially incorporated into scheduling circuitry or an associated memory in accordance with the invention.
  • the schedulers 102 and 800 may utilize any arrangement of logic gates, processing elements or other circuitry capable of providing scheduling functionality of the type described herein.
  • Scheduling circuitry in accordance with the invention may thus comprise otherwise conventional general-purpose network processor circuitry which is adaptable under software control to provide at least a portion of a scheduling function in accordance with the invention. Numerous such circuitry arrangements will be readily apparent to those skilled in the art, and are therefore not described in detail herein.
  • a given embodiment of the present invention can be implemented as one or more integrated circuits.
  • a plurality of identical die is typically formed in a repeated pattern on a surface of a wafer.
  • Each die may include a device as described herein, and may include other structures or circuits.
  • the individual die are cut or diced from the wafer, then packaged as an integrated circuit.
  • One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Integrated circuits so manufactured are considered part of this invention.
  • FIG. 8 utilizes a scheduler which is separate from its associated table or tables, these elements or portions thereof may be incorporated into scheduling circuitry in accordance with the invention.
  • transmit queues 802 and traffic shaper 804 are described as being separate from scheduler 800 in conjunction with the FIG. 8 embodiment, the associated functionality may be implemented at least in part within scheduling circuitry in accordance with the invention.
  • Other embodiments can use different types and arrangements of processing elements for implementing the described functionality.
  • the tables may be implemented in internal memory, external memory or combinations of internal and external memory.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
EP07250442A 2006-05-01 2007-02-02 High-throughput scheduler with guaranteed fairness for wireless networks and other applications Withdrawn EP1853016A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/415,546 US8228920B2 (en) 2006-05-01 2006-05-01 High-throughput scheduler with guaranteed fairness for wireless networks and other applications

Publications (1)

Publication Number Publication Date
EP1853016A1 true EP1853016A1 (en) 2007-11-07

Family

ID=38473892

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07250442A Withdrawn EP1853016A1 (en) 2006-05-01 2007-02-02 High-throughput scheduler with guaranteed fairness for wireless networks and other applications

Country Status (4)

Country Link
US (1) US8228920B2 (ja)
EP (1) EP1853016A1 (ja)
JP (1) JP5164425B2 (ja)
KR (1) KR101303390B1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018040648A1 (zh) * 2016-08-29 2018-03-08 中兴通讯股份有限公司 流量分配方法及无线接入点

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101098500B (zh) * 2006-06-30 2010-05-12 联想(北京)有限公司 融合移动通信网络与视频广播网络的通信系统及通信方法
US8027346B1 (en) * 2008-05-29 2011-09-27 Avaya Inc. Method and system for scheduler dominated merge of state changes
EP2244516B1 (en) * 2009-04-23 2016-05-18 Alcatel Lucent Relaying data between a base station and user equipment
US10083410B2 (en) * 2013-09-19 2018-09-25 Oracle International Corporation Method and system for implementing a cloud based email distribution fairness algorithm
US9525535B1 (en) 2014-08-08 2016-12-20 Sprint Spectrum L.P. Systems and methods for scheduling transmissions from an access node
CN109156022B (zh) 2016-06-22 2022-08-09 英特尔公司 用于全双工调度的通信设备和方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020061007A1 (en) 1999-01-13 2002-05-23 Pankaj Rajesh K. System for allocating resources in a communication system
WO2002085061A1 (en) 2001-04-12 2002-10-24 Qualcomm Incorporated Method and apparatus for scheduling transmissions in a wireless communication system
US20060117054A1 (en) 2004-11-29 2006-06-01 Jinhui Li Frame mapping scheduler with compressed mapping table

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995011204A1 (fr) 1993-10-21 1995-04-27 Chichibu Onoda Cement Corporation Composition a base aqueuse et auto-nivelante
US6289221B1 (en) * 1998-01-20 2001-09-11 Siemens Aktiengesellschaft Mobile radio telephone system
US7406098B2 (en) * 1999-01-13 2008-07-29 Qualcomm Incorporated Resource allocation in a communication system supporting application flows having quality of service requirements
US6470016B1 (en) * 1999-02-09 2002-10-22 Nortel Networks Limited Servicing output queues dynamically according to bandwidth allocation in a frame environment
US6763009B1 (en) * 1999-12-03 2004-07-13 Lucent Technologies Inc. Down-link transmission scheduling in CDMA data networks
US6985462B2 (en) * 2001-10-05 2006-01-10 Telefonaktiebolaget Lm Ericsson (Publ) System and method for user scheduling in a communication network
US6687651B2 (en) * 2002-01-10 2004-02-03 Fujitsu Network Communications, Inc. Real time estimation of equivalent bandwidth utilization
US7042858B1 (en) * 2002-03-22 2006-05-09 Jianglei Ma Soft handoff for OFDM
US7298719B2 (en) * 2002-04-15 2007-11-20 Lucent Technologies Inc. Method for scheduling wireless downlink transmissions subject to rate constraints
WO2004017584A1 (en) * 2002-08-16 2004-02-26 Nuasis Corporation Contact center architecture
CA2398755A1 (en) * 2002-08-19 2004-02-19 Faisal Shad Scheduler for a shared channel
JP2004147275A (ja) * 2002-08-30 2004-05-20 Matsushita Electric Ind Co Ltd パケット送信スケジューリング方法および基地局装置
US7602722B2 (en) * 2002-12-04 2009-10-13 Nortel Networks Limited Mobile assisted fast scheduling for the reverse link
JP2004187237A (ja) * 2002-12-06 2004-07-02 Matsushita Electric Ind Co Ltd 基地局装置およびパケット送信スケジューリング方法
US7734805B2 (en) * 2003-04-15 2010-06-08 Alcatel-Lucent Usa Inc. Method for scheduling transmissions in communication systems
US8099098B2 (en) * 2003-04-24 2012-01-17 Alcatel Lucent Methods and apparatus for planning wireless data networks using analytical modeling of user level performance
US7283814B2 (en) * 2003-07-31 2007-10-16 Lucent Technologies Inc. Method and apparatus for scheduling transmissions in wireless data networks
JP4335619B2 (ja) * 2003-09-04 2009-09-30 株式会社エヌ・ティ・ティ・ドコモ パケット優先制御装置及びその方法
US8493998B2 (en) * 2003-11-19 2013-07-23 Alcatel Lucent Method and apparatus for scheduling forward data bursts in wireless network
US7477636B2 (en) 2003-11-26 2009-01-13 Agere Systems Inc. Processor with scheduler architecture supporting multiple distinct scheduling algorithms
US8059589B2 (en) * 2004-06-09 2011-11-15 Qualcomm Incorporated Dynamic restrictive reuse scheduler
FR2873259A1 (fr) * 2004-07-13 2006-01-20 France Telecom Procede de selection de stations receptrices dans un systeme de transmission radio de donnees
US7680124B2 (en) 2004-07-30 2010-03-16 Agere Systems Inc. Frame mapping scheduler for scheduling data blocks using a mapping table and a weight table
GB0420164D0 (en) * 2004-09-10 2004-10-13 Nokia Corp A scheduler
US7477622B2 (en) * 2005-01-28 2009-01-13 Qualcomm, Incorporated Superposition coding in a wireless communication system
KR100922959B1 (ko) * 2005-03-29 2009-10-22 삼성전자주식회사 다중 안테나 시스템에서의 자원 스케줄링 장치 및 방법
US7660244B2 (en) * 2005-06-20 2010-02-09 Alcatel-Lucent Usa Inc. Method and apparatus for quality-of-service based admission control using a virtual scheduler
US7768973B2 (en) * 2006-04-21 2010-08-03 Fujitsu Limited Proportional fair scheduler for OFDMA wireless systems with QOS constraints
US8085819B2 (en) * 2006-04-24 2011-12-27 Qualcomm Incorporated Superposition coding in a wireless communication system
US7769038B2 (en) * 2006-05-01 2010-08-03 Agere Systems Inc. Wireless network scheduling methods and apparatus based on both waiting time and occupancy

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020061007A1 (en) 1999-01-13 2002-05-23 Pankaj Rajesh K. System for allocating resources in a communication system
WO2002085061A1 (en) 2001-04-12 2002-10-24 Qualcomm Incorporated Method and apparatus for scheduling transmissions in a wireless communication system
US20060117054A1 (en) 2004-11-29 2006-06-01 Jinhui Li Frame mapping scheduler with compressed mapping table

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
A. JALALI ET AL.: "Data throughput of CDMA-HDR a high efficiency high data rate personal communication wireless system", PROC. OF IEEE VTC 2000, May 2000 (2000-05-01), pages 1854 - 1858

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018040648A1 (zh) * 2016-08-29 2018-03-08 中兴通讯股份有限公司 流量分配方法及无线接入点
CN107801204A (zh) * 2016-08-29 2018-03-13 中兴通讯股份有限公司 流量分配方法及无线接入点

Also Published As

Publication number Publication date
KR20070106939A (ko) 2007-11-06
US8228920B2 (en) 2012-07-24
JP2007300642A (ja) 2007-11-15
JP5164425B2 (ja) 2013-03-21
US20070253375A1 (en) 2007-11-01
KR101303390B1 (ko) 2013-09-03

Similar Documents

Publication Publication Date Title
JP4397928B2 (ja) ワイヤレス通信ネットワークの資源を、ネットワークのチャネルを介してユーザ機器に送信すべきトラヒックに割り当てる方法
EP1853017B1 (en) Wireless network scheduling method and apparatus based on waiting time and queue occupancy
US8228920B2 (en) High-throughput scheduler with guaranteed fairness for wireless networks and other applications
EP2681886B1 (en) Lte scheduling
EP2027681A1 (en) Mapping services to radio bearers and allocating bandwidth to the radio bearers according to weight values
KR20120081204A (ko) 무선 통신 시스템에서 서비스 품질 (ＱｏＳ) 송신의 스케줄링을 위한 방법 및 장치
EP2057797B1 (en) Scheduling methods and apparatus based on adjusted channel capacity
EP1653683B1 (en) Dynamic setting of transmission scheduler algorithms
US7724723B2 (en) High-throughput scheduler with integer-based eligible number initialization
US7830857B2 (en) Credit-based wireless network scheduling
US7352752B2 (en) Frame mapping scheduler with compressed mapping table
US7680124B2 (en) Frame mapping scheduler for scheduling data blocks using a mapping table and a weight table
US20070060148A1 (en) Packet scheduler
Shao et al. Dynamic resource control for high-speed downlink packet access wireless channel
AJIB et al. SERVICE DISCIPLINES PERFORMANCE FOR BEST-EFFORT POLICIES IN WWW TRAFFIC OVER PACKET-SWITCHED WIRELESS CELLULAR NETWORKS

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA HR MK YU

17P Request for examination filed

Effective date: 20080123

17Q First examination report despatched

Effective date: 20080220

AKX Designation fees paid

Designated state(s): DE GB

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: LSI CORPORATION

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INTEL CORPORATION

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20180626