Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F15/00—Digital computers in general; Data processing equipment in general
  • G06F15/76—Architectures of general purpose stored program computers
  • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30181—Instruction operation extension or modification
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F15/00—Digital computers in general; Data processing equipment in general
  • G06F15/76—Architectures of general purpose stored program computers
  • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
  • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
  • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components

Definitions

• a programmable logic circuit such as a field programmable gate array (FPGA) or a programmable logic device (PLD), which can freely change the configurations of the logic circuits in a processor, has been widely used.
• FPGA field programmable gate array
• PLD programmable logic device
• HDL hardware description language
• a high-level language or a modeling tool having high abstraction, such as C language, is mainly used for examining an algorithm applied to the LSI.
• the logic circuit is prepared using the algorithm created in a high-level language, the examined algorithm should be rewritten in the HDL, and thus the preparing time increases.
• a potential problem is that once the logic circuit configuration is created in the HDL, it is difficult to change the algorithm.
• Another a problem is that the software developer usually must consider a specific limit of the hardware in the operation synthesizing step. Disclosure of Invention
• ISA' instruction set architecture
• a series of logic circuit configuration information of a processor for executing an application program from an application program described in a high-level language.
• the present invention also relates to a custom LSI development platform technology which can design, develop, and manufacture the application specific custom LSI in a short time by applying the generated ISA and logic circuit configuration information to a dynamic logic circuit reconfigurable processor.
• a dynamically reconfigurable processor which is reconfigurable using the generated logic circuit configuration information.
• ISA instruction set architecture
• a custom LSI development platform including a processor and a software module.
• the processor is a dynamic logic circuit reconfigurable processor.
• the software module includes an ISA generator for generating an ISA of the processor; and a logic circuit configuration generator for generating logic circuit configuration information of the processor from layout arrangement information of a programmable element (PE) constituting logic circuits of the processor and the ISA.
• PE programmable element
• the ISA generator includes a means for extracting the pattern of an instruction of a program described in a high-level language, and a means for comparing the pattern of the extracted instruction with the pattern of a custom instruction stored in a library.
• the ISA generator comprises a means for substituting the extracted instruction with the custom instruction and/or combination of the custom instructions.
• the ISA generator further includes a function call that is a means for calling the extracted custom instruction, and a means for generating a middle code including a control instruction of the processor.
• the software module includes a means for converting the middle code and the custom instruction into an object code.
• the software module further includes a means for generating a logic circuit configuration object code from the logic circuit configuration information, and a simulator for simulating the performance of the ISA.
• the software module further includes a creator for generating as a new custom instruction an instruction that is not substituted with the custom instruction during the process for substituting the extracted instruction with the custom instruction.
• the processor includes a dynamic reconfigurable logic circuit, a configuration memory for storing the logic circuit configuration information of the custom instruction, and a memory for storing the extracted custom instruction.
• the processor could include a register file for temporarily holding the result of executing the extracted custom instruction, and a controller for reading the logic circuit configuration information corresponding to the custom instruction from the configuration memory and reconfiguring the dynamic reconfigurable logic circuit when executing the custom instruction.
• the controller can further include an index register for storing an index when accessing the memory, while the processor could further include a stack for storing a value of the index register.
• a method for generating an ISA of a processor including extracting the pattern of an instruction of a program described in a high-level language, comparing the pattern of the extracted instruction with the pattern of a custom instruction stored in a library, and substituting the extracted instruction with the custom instruction and/or combination of the custom instructions to generate the ISA.
• the logic element connection information substituted with the custom instruction is extracted, and the ISA is generated to include the logic element connection information.
• the logic element connection information may be stored in the library so as to be associated with the custom instruction.
• the instruction that is not substituted with the custom instruction among the program instructions in the process for substituting the program instruction with the custom instruction and/or combination of the custom instructions is created as a new custom instruction and is added to the library to extract the custom instruction again.
• a method for generating logic circuit configuration information of a processor that includes extracting the pattern of an instruction of a program described in a high-level language, comparing the pattern of the extracted instruction with the pattern of a custom instruction, and substituting the extracted instruction with the custom instruction and/or combination of the custom instructions.
• the method also includes generating the logic circuit configuration information from logic element connection information associated with the custom instruction and layout arrangement information of a programmable element of the processor.
• the logic element connection information may be stored in a library, and the processor may be a dynamic logic circuit reconfigurable processor.
• a dynamically reconfigurable microprocessor comprising a program stack operable to receive a plurality of program instructions, where the program instructions comprises at least first and second instruction sets.
• the processor includes a reconfigurable logic circuit in electrical communication with the program stack, where the reconfigurable logic circuit has alternative first and second data paths whereby data to be operated on according to the first instruction set passes through the first data path and data to be operated on according to the second instruction set passes through the second data path.
• the reconfigurable logic circuit is reconfigurable according to whether instructions corresponding to the first or second instruction set are being executed by the microprocessor.
• a fifth aspect disclosed in a method of dynamically reconfiguring processing circuitry.
• the method comprises receiving a plurality of program instructions to be executed by the processing circuitry, where the program instructions comprise at least first and second instruction sets.
• the method further comprises configuring a reconfigurable logic circuit in a first data path when operating on data according to the first instruction set, and configuring the reconfigurable logic circuit in a second data path when operating on data according to the second instruction set;
• a dynamic logic circuit reconfigurable processor According to a sixth aspect of the present invention, there is provided a dynamic logic circuit reconfigurable processor.
• the processor may include a dynamic reconfigurable logic circuit, a configuration memory for storing layout arrangement information for each instruction of a programmable element (PE) constituting the dynamic reconfigurable logic circuit, a register file for temporarily holding a middle result of executing an instruction; a memory for storing the instruction, and a controller for managing the processor including executing order of the instruction.
• the controller further includes an index register for storing an index when accessing the memory, while the processor further includes a stack for storing a value of the index register.
• the set of instructions provides the steps of extracting an instruction pattern from an instruction in an application program of the processor described in a high-level language, comparing the extracted instruction pattern with patterns of one or more custom instructions stored in a library, and substituting the instruction in the program with the one or more custom instructions to generate the instruction set architecture.
• the instructions further include the step of generating the logic circuit configuration information from logic element connection information associated with the one or more custom instructions included in the instruction set and from layout arrangement information of at least one programmable element of the processor.
• FIG. 1 is a block diagram illustrating the entire structure of one embodiment of a custom LSI development platform according to the present invention
• FIG. 2 is a detailed block diagram of one embodiment of a software module
• FIG. 3 is a detailed block diagram of one embodiment of an ISA generator
• FIG. 4 is a block diagram of one embodiment of a dynamic logic circuit reconfigurable processor according to the present invention
• FIG. 5 is a functional block diagram of one embodiment of a dynamic logic circuit processor according to the present invention
• FIG. 6 is a diagram illustrating the structure of an instruction format
• FIG. 7 is a diagram illustrating the structure of a reconfigurable data path according to an embodiment of the present invention
• FIG. 8 is a diagram illustrating a flow of an AES encryption process conducted in accordance with the disclosed principles
• FIG. 9 is an exemplary description of a middle code of the AES encryption process
• FIG. 10 is another exemplary description of the middle code of the AES encryption process
• FIG. 11 is a flowchart of a DES encryption process conducted in accordance with the disclosed principles.
• ISA' instruction set architecture
• the present invention relates to a custom LSI development platform technology which can design, develop, and manufacture the application specific custom LSI in a short time by applying the generated ISA and logic circuit configuration information to a dynamic logic circuit reconfigurable processor.
• a software developer can employ the disclosed technology to develop an application without considering hardware characteristics. As a result, the entire execution cycle number required for the development can be reduced and thus an application specific custom LSI can be developed in a short time.
• commonness (platform) of property for developing the custom LSI is possible, and the design and development property can be standardized.
• a "dynamic logic circuit reconfigurable processor” is a processor having a function that dynamically reconfigures and processes a logic circuit in a processor according to an instruction.
• a "custom LSI” is an LSI including an application specific integrated circuit (ASIC) that is designed and manufactured according to needs.
• a "custom instruction” is an instruction that is executed by a process and defined by a user.
• An “instruction set” is a series of instruction codes included in a processor.
• An “instruction set architecture” (ISA) is composed of logic element connection information required for generating logic circuit configuration information of a processor and an instruction set.
• the "logic element connection information” is information defining, for example, an AND circuit, an OR circuit, and an XOR circuit in this order. Accordingly, on the logic circuit of the dynamic logic circuit reconfigurable processor, the information on where the AND circuit, the OR circuit, or the XOR circuit is located, or which wiring lines connects the AND circuit, the OR circuit, and the XOR circuit to one another, is not included.
• a "custom logic circuit” is a logic circuit for realizing a custom instruction, and is a circuit or a function that cannot be realized in a general-purpose processor due to the performance.
• a “platform” is a system composed of common hardware and software that can be used for realizing a different custom logic circuit.
• a “data path” is a logic circuit of a processor for executing a custom instruction.
• a “programmable element” is an element for constructing a logic circuit, such as the AND circuit, the OR circuit, the XOR circuit, or an ALU circuit.
• the software module 10 is composed of a series of software for generating logic circuit configuration information for dynamically changing an ISA in the dynamic logic circuit reconfigurable processor 20 and a reconfigurable logic circuit 24 (reconfigurable data path) in the dynamic logic circuit reconfigurable processor 20 for each custom instruction.
• an ISA generator 110 If a software developer describes a source program 100 in a C language, an ISA generator 110 generates and compiles a middle code 111 and an ISA 112 to generate a program object code 141 and a logic circuit configuration object code 142.
• the dynamic logic circuit reconfigurable processor 20 processes operation of input data 27, while changing a reconfigurable logic circuit 24 for each custom instruction based on the program object code 141 and the logic circuit configuration object code 142, and outputs data 28 as a final result.
• FIG. 2 is a detailed block diagram of the software module 10 illustrated in FIG. 1.
• an ISA generator 110 starts up and analyzes the instruction structure of the C source program 100. Also, in a custom instruction library 160, a plurality of custom instructions which are previously defined are stored. The ISA generator 110 extracts the pattern of the instruction that is in use or is repeatedly used in the C source program 100, compares it with the pattern of the custom instruction in the library 160, substitutes the instruction in the C source program 100 with the custom instruction, and generates the middle code 111 and the ISA 112.
• the middle code 111 is composed of a function call of the custom instruction and a control instruction
• the ISA 112 is composed of a custom instruction and logic element connection information.
• the middle code 111 is compiled to an assembler code 121 by a compiler 120 and then becomes a program object code 141. Further, the compiler 120 compiles the middle code 111 and the custom instruction of the ISA 112, for example, the custom instruction that multiplication is defined as V to the assembler code 121.
• the custom instruction of the ISA 112 is converted into the assembler code 121 together with the middle code 111 by the compiler 120, and then becomes the program object code 141 by the assembler 140.
• a logic circuit configuration generator 130 generates logic circuit configuration information 1311 from the logic element connection information of the IS A 112 and layout arrangement information 1310 of a programmable element (PE) of a reconfigurable logic circuit 24. It then converts it into the logic circuit configuration object code 142 by the assembler 140.
• the software module further includes a simulator 170 for simulating the performance of the ISA 112, specifically, program object code 141 and the logic circuit configuration object code 142.
• FIG. 3 is a detailed block diagram of the ISA generator 110. As shown in FIG.
• a patterning module 1110 extracts an instruction that is in use or is repeatedly used in the C source program 100 with reference to the library 160, compares the pattern of the extracted instruction with the pattern of the custom instruction stored in the library 160, and substitutes an identical instruction with the custom instruction (1140).
• Various instructions that were not extracted as the custom instructions (were not previously created as the custom instructions) by the patterning module 1110 are newly defined and created by a creator 150, or are synthesized to the existing custom instruction and defined as new custom instructions (1160) if the various instructions can be synthesized to the existing custom instruction.
• the custom instructions of the library 160 are always updated by the addition and synthesis of the custom instruction (1160).
• the patterning module 1110 substitutes the instruction of the C source program 100 with the custom instruction until the entire C source program 100 can be executed. This includes covered instructions 1120 and non-covered instructions 1130.
• the patterning module 1110 generates the logic circuit configuration information of the reconfigurable logic circuit 24 for each custom instruction, with reference to the logic element connection information (associated with the custom instruction and stored in the library 160) and the layout arrangement information 1150 of the PE.
• the ISA generator 110 thus produces (1170) the ISA 112 and Middle Code 111.
• FIG. 4 is a block diagram showing a dynamic logic circuit reconfigurable processor
• the dynamic logic circuit reconfigurable processor 20 includes the reconfigurable data path (reconfigurable logic circuit) 24 and executes programs by sequential control.
• the dynamic logic circuit reconfigurable processor 20 executes the process content of the C source program 100 while resetting the logic circuit configuration for each step. Further, the step is a period that is required for executing one instruction, including the setting of the logic circuit configuration and the execution of the operation.
• the logic circuit configuration information is configuration information of the reconfigurable logic circuit for executing the custom instruction.
• the dynamic logic circuit reconfigurable processor 20 includes a controller 21, a stack 22, a configuration memory 23, a reconfigurable data path 24, a register file 25, and a memory 26.
• the controller 21 performs the entire management of the dynamic logic circuit reconfigurable processor 20, such as a load of the configuration data and a load of data in the memory 26.
• the controller 21 includes seven 22-bit index registers 211 formed therein and can access the memory 26 using the value of the index register 211. Also, the controller
• the memory 26 is a storage device for storing the instruction of the dynamic logic circuit reconfigurable processor 20.
• FIG. 5 illustrates a functional block diagram of the dynamic logic circuit processor 20 illustrated in FIG. 4.
• the functional diagram illustrates dynamically reconfiguring a logic circuit from a high-level language source program, in accordance with the disclosed principles.
• an ISA generator analyzes the instruction structure of the high-level source program 100. The ISA generator extracts the pattern of the instruction that is in use or is repeatedly used in the C source program 100, and compares it with the pattern of the custom instruction in the library. The ISA generator then substitutes the instruction in the source program 100 with the custom instruction, and generates the middle code (see above) and the ISA 112.
• the ISA 112 is composed of a custom instruction(s) and logic element connection information.
• Logic circuit configuration information is generated from the logic element connection information of the ISA 112 and layout arrangement information of a PEs of the reconfigurable logic circuit 24.
• the logic circuit configuration information is then converted into the logic circuit configuration object code 142. This is typically done by an assembler, such as the assembler 140 described above. According to one embodiment, multiple sets of logic circuit configuration information object code 142 can be created. In FIG. 5, examples of such object codes are labeled 142a, 142b, 142c, however, there is no limit to the number of various object codes that may be generated, and in exemplary embodiments, the most suitable instruction set is used.
• Each set of object code 142a, 142b, 142c provides for a corresponding configuration in the dynamic reconfigurable logic circuit 24. These are labeled as 24a, 24b, 24c, respectively, and represent distinct configurations in the programmable logic elements comprising the logic circuit 24. Once the desired logic circuit 24 configuration is created, 64-bit registers are used in this embodiment to execute the desired code with the selected configuration.
• the dynamic reconfigurable logic circuit processor 20 disclosed herein is reconfigurable to provide processing operations typically provided by multiple dedicated processing units.
• the processor 20 may be configured to function as a central processing unit of a computer, while at a second point in time it is configured to operate as an application specific processor, and then at a third point in time it is configured to operate as a digital signal processor.
• the disclosed principles result in a reduced overall device size and space.
• flexibility in processing capabilities is increased without increasing manufacturing costs.
• the logic elements within the processor 20 axe mapped to the particular application to be executed. As a result, each application is executed more efficiently with the disclosed technique, since each distinct application is executed by hardware reconfigured for each application. Moreover, such reconfiguration of the processor 20 is accomplished automatically from the application codes to be processed.
• FIG. 6 illustrates the structure of the instruction format stored by the memory 26.
• the instruction is executed by the operation with the reconfigurable data path 24, or is executed only by the manipulation of the value of the index register 211 without using the reconfigurable data path 24. If the instruction is executed by the operation with the reconfigurable data path 24, the address of the configuration memory 23 in which adequate configuration data are stored and the register file 25 used for the operation are designated. If the instruction is executed by the manipulation of the value of the index register 211, the operation content and the index register 211 used for the operation are designated. If the memory address is designated in the section 'ImData', the exchange of the data between the memory 26 and the index register 211 can be executed.
• the executing order control of the program can be designated, and, if the branch condition can be designated, the process can be branched using the operation result at the reconfigurable data path 24.
• the sections 'Dt_Adr' and 'Rel_Adr' are used for designating a relative address.
• the section 'Work_Rate' can be used for designating the clock cycle number when executing the process by the reconfigurable data path 24 by 1, 2, 4 or 8 clock cycles according to the process content.
• the configuration memory 23 is a memory for storing the configuration data.
• the configuration memory 23 can store 128 configuration data of the custom instruction.
• the register file 25 is a register for storing the operation result at each PE of the reconfigurable data path 24 and transferring it to a different function. One word has a 256-bit width.
• the register file 25 is connected to the PE of the reconfigurable data path 24 and the bit location of the stored register file 25 is determined depending on the location of the PE for outputting data.
• FIG. 7 illustrates the structure of the reconfigurable data path 24 according to an embodiment of the present invention.
• the PEs are arranged in 16 rows x 8 columns.
• the PEs have six inputs and two outputs and can allocate any logic function to the input.
• the PEs are connected to each other by a vertical line (VL) and a horizontal line (HL).
• the VL is connected to the respective PEs of one column and each VL is connected to the HL.
• a switching unit (SW) controls the exchange of the signal from the VL to the HL or from the HL to the VL.
• the VL has a 64-bit width and the number thereof is 8, and the HL has a 64-bit width and the number thereof is 7. Also, 64-bit data can be loaded from the memory to the reconfigurable data path 24 at a time.
• the controller 21 reads the program from the memory 26 and determines whether the instruction uses the reconfigurable data path 24 or operates only the value of the index register 211. In a case of using the reconfigurable data path 24, the controller 21 reads adequate configuration data from the address of the configuration memory 23 designated in the program and loads this data to the reconfigurable data path 24.
• the reconfigurable data path 24 performs the process of the input data if the configuration (logic circuit configuration) is fixed.
• the operation result executed in each PE can be output to the VL and written in the register file 25. As a middle result, the data can be transferred to a separate function and can be used.
• the register file 25 By using the register file 25, a large process can be divided into a plurality of functions and can be then executed.
• the value of the index register 211 since an operation circuit is prepared in the index register 211, the operation designated in the program is performed in the operation circuit and is transitioned to a next instruction.
• an encryption custom LSI of an advanced encryption standard was developed.
• the AES is selected as a standard encryption method for substituting a date encryption standard (DES).
• DES date encryption standard
• the ISA is generated from the program of the AES created in the C language, and the AES encryption process was performed in the dynamic logic circuit reconfigurable processor 20 to perform the performance evaluation.
• the bit number of the plain text or the bit number of the key can be selected. However, in this embodiment, both of them were set as 128 bits.
• FIG. 8 illustrates a flow of the AES encryption process.
• a data-format plain text of two-dimensional arrangement called 'State' is arranged.
• a round key is generated (Sl), and an exclusive OR of State and the round key is performed (S2).
• the round function is executed a predetermined number of times. In this embodiment, the round function was executed 9 times in the following condition.
• the round function is executed by next 4 conversions.
• an s-box converting process having 8-bit input and 8-bit output (byte- sub) is executed (S3).
• Shift-Row for executing periodic shift of a byte unit with respect to a row is executed (S4).
• Mix-Column to be a matrix operation for each column is executed (S5).
• FIG. 9 and FIG. 10 are examples of the middle code 111 of the AES encryption process that is described in the C language, including Byte-sub, Shift-Row, Mix-Column, and Add-Round-Key.
• the main routine of the AES encryption process is an 'encrypt' function.
• the head of the custom instruction is attached with 'vul-'.
• 309 cycles are obtained in the entire process and 79 cycles are obtained in the encryption process.
• Embodiment 2 The DES is an encryption standard standardized in the National Institute of
• 64-bit encryption text is output.
• DES encryption process a 64-bit string is first input and is subjected to initial transpose based on a transposed table.
• the transposed bit string is divided by 32 bits.
• the divided bit strings are encrypted by the key and the encryption function F, respectively.
• the key uses 48-bit round key generated from the input 56-bit key. This process is performed 16 times, and the created left and right bit strings are combined to perform final transpose. Thus, the result is output as the encryption text.
• FIG. 11 is a flowchart of the DES encryption process.
• Table 1 represents the custom instructions used in the DES encryption process and the contents thereof. Table 1
• a 56-bit key is input from the memory to the reconfigurable data path 24 by the instruction 0, and the transpose thereof is simultaneously executed.
• 64-bit plain text is input by instruction 1, and the initial transpose thereof is simultaneously executed.
• the cyclic shift of the key is executed by instruction 2 or 3 according to the round number.
• instruction 4 the reduction transpose of the key and the encryption F function are executed by one instruction.
• the exchange of the data between the instructions is performed through the register file 25. This round is repeated 16 times. In FIG. 11, the repetition is performed by the conditional branch process, but in the present embodiment, the repetition is developed and is sequentially performed. This is to reduce the designed circuit scale and because a redundant circuit for determining the round number must be made in order to execute the conditional branch process. Finally, the inverse of the initial transpose is performed, and a 64-bit cipher text is output in the memory.
• Table 2 represents an operation frequency and throughput when performing the DES encryption process by the dynamic logic circuit reconfigurable processor 20.
• the operation frequency of the DES encryption process was 6.25 MHz.
• the result of performing the DES encryption process by an Intel Pentium® 4 is shown in Table 2. Table 2
• the DES encryption process of the Pentium® 4 was executed by compiling the description of the specification of the DES encryption process by the C language. In the compile option, -02 was used.
• the DES encryption process of the dynamic logic circuit reconfigurable processor 20 from Table 2 represents performance higher than the DES encryption process of Intel Pentium (registered trademark) 4 by 3.8 times. This is because the characteristic that the PE serving as the component of the dynamic logic circuit reconfigurable processor 20 can allocate any logic function to the input by one bit unit can be used in the DES encryption process.
• the transpose or the substitution of one bit unit is repeated.
• a 32-bit microprocessor such as the Intel Pentium® 4
• the PE of the dynamic logic circuit reconfigurable processor 20 inputs the data from the register file 25 to the reconfigurable data path 24, moves it to a designated bit location, and stores it in the register file 25 again.
• the PE can allocate any logic function to the input, a plurality of the processes depending on the data are synthesized and are executed by one instruction, thereby reducing the executed clock cycle number.
• the present invention provides a custom LSI development platform in which when a software developer prepares an application program in a high-level language, for example, C language, an ISA and logic circuit configuration information are automatically generated based on the created application program. The generated ISA and logic circuit configuration information are then automatically applied to a dynamically reconfigurable logic circuit processor.
• the disclosed principles may be used as a platform in designing and developing the custom LSI, as well as in manufacturing an application specific custom LSI.

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• 2005
  • 2005-11-30 KR KR1020077014815A patent/KR20070097051A/ko not_active Application Discontinuation
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