EP1820092A2

EP1820092A2 - Electronic device having multi operand arithmetic circuitry

Info

Publication number: EP1820092A2
Application number: EP05825414A
Authority: EP
Inventors: Sergei Sawitzki
Original assignee: Koninklijke Philips Electronics NV
Current assignee: NXP BV
Priority date: 2004-12-01
Filing date: 2005-11-28
Publication date: 2007-08-22
Also published as: CN101069152A; WO2006059267A2; JP2008522304A; WO2006059267A3

Abstract

An electronic device comprising an arithmetic circuitry (AC) for performing at least one of an addition or a subtraction of more than two binary input numbers (BINl - BIN4) is provided, wherein at least two of the binary input numbers differ in their bit-widths. The arithmetic circuitry (AC) comprises an extension means (EUl - EU3) for performing a sign and/or a zero extension of at least one of the binary input numbers (BINl - BIN4). Further, the arithmetic circuitry (AC) comprises at least two two-operand arithmetic units (AUl - AU3), each for calculating an addition and/or a subtraction of two operands being a first and a second binary number, and overflow and saturation means (OSUl - OSU3) for detecting a calculation overflow of at least one two-operand arithmetic unit (AUl - AU3) and for saturating the calculation result of the arithmetic unit (AUl - AU3) in accordance with the detected overflow result.

Description

Electronic device having multi operand arithmetic circuitry

The invention relates to an electronic device with an arithmetic circuitry for performing at least one of an addition or a subtraction of more than two binary input numbers. At least two of the binary input numbers differ in their bit-width. The invention is also related to a method for addition or subtraction of more than two binary input numbers. Further, the invention relates to a method for designing an arithmetic circuitry. The invention relates also to a data processing system with an electronic device with an arithmetic circuitry for performing at least one of an addition or a subtraction of more than two binary input numbers with different bit-widths.

Arithmetic units, used in digital signal processors (DSPs), other kinds of processors or microcontrollers, as well as in application specific integrated circuits (ASICs), comprise binary input numbers with a predefined number of bits. The number of bits representing a binary input number is the bit-width. A finite bit-width entails a finite range of representable numbers. Due to the finite range of representable numbers, the binary input numbers in a logic unit are confined to a maximum representable value, a minimum representable value and a finite quantization. In order to avoid excess of the minimum and maximum values during calculation the calculation result has an enlarged bit-width to cover all possible results. The result is monitored and an overflow (or underflow) indicator is generated to signal a violation of the predetermined bit-width. Typically, overflow or underflow flags are used to indicate whether a calculation result extends the allowable value range or not. Furthermore, if overflow or underflow occurs, the binary input number representing the calculation result is set to a predefined value, that is the maximum or minimum representable value. This step is called saturation.

Overflow detection and saturation arithmetic are widely used features of arithmetic processing units employed in DSP, microcontrollers, and microprocessors. Saturation is necessary to reduce errors occurring due to quantization and due to the finite range of representable numbers in computer arithmetic. Binary input numbers are used in signed and unsigned formats. A common format for signed binary input numbers is the 2's complement. According to the 2's complement, a negative value has leading 1. Most processor architectures are based on a two-operand model. Accordingly, always two binary input numbers having the same binary representation and the same bit- width are computed. If the same arithmetic operation has to be applied to more than two numbers, the operation can be performed serially, i.e. the operation is performed on two numbers and subsequently on a third number. In particular, today's application-specific processors often require more than a two-operand based arithmetic. Additionally, the bit- width of the binary input numbers to be computed may vary, even for the same arithmetic unit. Regarding processors, two scenarios might be considered: processors or controllers having an algorithmic logic unit for usually multiplying and adding two digital numbers retrieved from a memory as well as ASICs including dedicated logic to perform calculation steps in a more efficient way.

The design of arithmetic circuitry for ASICs is usually supported by design software tools, often conceived to design in an hierarchical manner. Hierarchical circuit design strategies start at a rather behavioral description of a circuitry. In a later step, either the designer or the design software synthesizes logic gates and transistors to meet the behavioral definition. At the end of the synthesizing step a schematic and a layout of the circuitry exist, on the basis of which the circuitry is finally manufactured. Today, various steps of the design process are carried out automatically. However, the resulting arithmetic circuitry is often not completely optimized after the automatic synthesizing steps. Therefore, a lot of effort is put in the finding of effective concepts and rules to design optimized algorithmic circuitry.

The following explanations of multi-operand arithmetic are illustrated with respect to the standard 2's complement representation of integers. For the case of a simple 2- input arithmetic unit, wherein both inputs have the same bit-width, the overflow detection for addition or subtraction is widely known. Usually, the bit-width of the calculation result is one bit greater than the bit-widths of the binary input number. Additionally, a carry flag (or bit) is provided. The overflow flag is the carry flag for unsigned integers or the logical AND of the negated carry flag and the highest bit position of the result for the signed case. An underflow flag can be obtained by use of the same logic. As soon as an overflow or an underflow is detected, a saturation is to be applied. When saturated, the obtained result is replaced by the maximum (in case of overflow) or minimum (in case of underflow) representable value.

In case of more than two operands the known and straight forward overflow detection methods cannot be applied. Adding for example three times 111 I₂ would result in (0)110I₂. Accordingly, the carry flag is 0. The carry flag 0 indicates that an overflow is not detected, though an overflow occurred. The same problem arises for signed operands. If more than two operands with different bit-widths are added, additional problems occur. For example 111 I₂ + 111 h + 1111111 h would result in 10001 HOl₂. Even though the result is correct for the unsigned case, it is not correct for signed binary numbers. For signed numbers, the correct result is 1111110I₂ (-3₁₀). To conclude, overflow or underflow detection and saturation arithmetic for a unit with more than two input operands cannot be implemented in a straight forward manner.

In US 5,917,739 an algorithmic unit is disclosed, where the n-bit average of four signed or unsigned n-bit integer operands is calculated in one instruction cycle. A method and a circuit is described, which should be used to obtain the average of four numbers, wherein the numbers have the same bit- widths. Subtraction is not covered by the method and the circuit. The intermediate result is extended, but saturation is not mentioned.

US 2003/0140072 relates to two-input addition. Both inputs have the same bit- widths. US 6,321,248 discloses an overflow detection for a two-input operation. A particular case for two operands having different bit-widths is mentioned for the two-operand operation.

In "Overflow detection in multi-operand addition", International Journal of Electronics, Vol. 73, No. 3, pp. 461-469, 1992, Pai and Tran disclose an algorithm to detect overflow in multi-operand addition. The algorithm is extended to support generic commercial arithmetic adder chips. This is used in conjunction with a multi-operand carry-save adder and a multi-operand bit-serial adder to detect overflow. Provision is also made in these circuits to incorporate subtraction of operands. CAD tools are used to simulate the logic in hardware for the verification of the algorithm. According to Pai and Tran, all inputs have the same bit- width. They propose to count the required number of carry-out bits depending on the number of inputs.

For the sake of brevity of the present description, the term "overflow" includes "underflow". Accordingly, any reference made to "overflow detection" and a corresponding saturation (maximum) should be understood as comprising the case of "underflow detection" and a corresponding saturation (minimum).

It is an object of the invention to provide an improved and effective electronic device with algorithmic circuitry for performing a calculation operation on more than two binary input numbers, at least two of which differ in their bit-widths. It is also an object of the present invention to provide a design method to generate the improved algorithmic circuitry for performing a calculation operation on more than two binary input numbers, at least two of which differ in their bit-widths.

The object is solved by a an electronic device according to claim 1, a data processing system according to claim 6, a method for calculating a sum or difference of N binary input numbers according to claim 7, and a method for designing an arithmetic circuitry according to claim 8.

Therefore, an electronic device comprising an arithmetic circuitry for performing at least one of an addition or a subtraction of more than two binary input numbers is provided, wherein at least two of the binary input numbers differ in their bit- widths. The arithmetic circuitry comprises an extension means for performing a sign and/or a zero extension of at least one of the binary input numbers. Further, the arithmetic circuitry comprises at least two two-operand arithmetic units, each for calculating an addition and/or a subtraction of two operands being a first and a second binary number, and overflow and saturation means for detecting a calculation overflow of at least one two-operand arithmetic unit and for saturating the calculation result of the arithmetic unit in accordance with the detected overflow result.

Accordingly, always two binary input numbers are combined to an intermediate or the final result. Overflow detection and saturation is applied independently to each two-operand calculation result. Even the final result is computed on two inputs. This way, the common rules of two-operand overflow detection and saturation can be reused for every two-operand arithmetic unit. According to the invention, an extension means is disposed, where necessary, to extend the binary input numbers to have the same bit-widths during calculation. An extension means might be arranged at the input to the arithmetic circuitry in order to extend all the binary input numbers to the same bit-width. Further, an extension means can be located between two two-operand arithmetic units for extending the output of a presiding two-operand arithmetic unit before it is input to the next two-operand arithmetic unit. The overflow and saturation means controls the calculation results of the two- operand arithmetic units, detect calculation overflows and set the calculation results to a maximum or minimum value according to the detected overflow result. The overflow and saturation means may control the outputs of all the two-operand arithmetic units or just some of them, if it is predetermined that overflow will not occur in a particular stage of the circuitry. Sign extension is used in case of signed operation and zero extension is used in case of unsigned operation. The proposed arithmetic unit can have more than two inputs with different bit-widths and still detect overflow or underflow and saturate the result correctly. The extension means detect whether an input operand needs sign or zero extension and extend the operand accordingly.

According to an aspect of the invention, the arithmetic circuitry comprises an input means for inputting at least one binary input number to the extension means. If an input means is provided for more than one binary input number, the numbers can be input in a parallel manner. For numerous applications, a rather parallel approach of inputting numbers is advantageous over a serial manner, allowing only to input numbers one after the other or bit by bit.

According to a further aspect of the invention, a plurality of extension units is provided in the arithmetic circuitry for performing a sign and/or zero extension of at least one of the binary input numbers for each binary input number having a smaller bit- width than the binary input number having the greatest bit-width. A very effective approach is the use of a plurality of extension units instead of a more or less centralized extension means. It is preferred to dispose each extension unit close to an input unit to the arithmetic circuitry. This way, each extension unit might be dedicated to extend one binary input number with a smaller bit-width than the one with the largest bit-width. Accordingly, the bit-width of the binary input number with the greatest bit-width is determined and the other binary input numbers having smaller bit-widths are extended to have the greatest bit-width. The extension units are not necessarily disposed at the input of the arithmetic circuitry, but might also be located somewhere within the arithmetic circuitry.

According to a further aspect of the invention, all the extension units provide an input for inputting a control signal that indicates whether the binary input number that is passed to the extension unit is of a signed or unsigned format. Accordingly, the extension unit is controlled by the input, which is typically a single bit control input, to sign or zero extend the binary number in response to the indicated binary input number format.

According to another aspect of the invention, the electronic device comprises a plurality of overflow and saturation units, each for detecting a calculation overflow of a single two-operand arithmetic unit and for saturating the calculation result of the two-operand arithmetic unit in accordance with the detected overflow result. The use of a plurality of overflow and saturation units gives rise to a rather independent operation that can attribute to calculation speed and effectiveness of the whole arithmetic circuitry. If, for example, each of the two-operand arithmetic units is followed by a dedicated overflow and saturation unit, the respective logic circuitry, to realize the overflow and saturation procedure, can be less sophisticated than in the case of one overflow and saturation means used for a plurality of two-operand arithmetic units.

The invention is also related to a method for calculating a sum and/or a difference of N binary input numbers, if N is greater than two and at least two of the binary input numbers differ in their bit-widths. The method includes the step of extending at least one binary input number having a shorter bit-width to have the same bit-width as a second binary input number. In another step a sum and/or a difference of two binary input numbers is calculated. The calculation step is performed by using N-I two-operand arithmetic units, each for calculating an addition and/or a subtraction of two operands being a first and a second binary number. Additionally, overflow of the calculation result of at least one of the two-operand arithmetic units is detected and saturation of the calculation result in accordance with the detected overflow result is performed. Since the calculation step is confined to a two-operand arithmetic unit, calculation, overflow detection and saturation is faster and less complex than in other solutions. The invention is further related to a method for designing arithmetic circuitry for performing an addition and/or a subtraction of N binary input numbers, wherein N is greater than two and at least two of the binary input numbers differ in their bit-width. In a synthesizing process for the arithmetic circuitry according to the present invention, the following entities have to be provided: Input means to input the N binary input numbers to the arithmetic circuitry, extension means for performing a sign and/or zero extension of at least one of the binary input numbers, N-I two-operand arithmetic units, each for calculating an addition and/or subtraction of two operands being a first and a second binary number, overflow and saturation means for detecting a calculation overflow of at least one two- operand arithmetic unit and for saturating the calculation result of the arithmetic unit in accordance with the detected overflow result, and connections between the input means, extension means, the arithmetic units and the overflow and saturation means. An arithmetic circuitry, designed with respect to the above design steps, is less complex and more effective than conventional circuitry.

According to a further aspect of the invention, the method for designing the arithmetic circuitry comprises a step of connecting the arithmetic circuitry such that each output of the N-I two-operand arithmetic units is connected to the overflow and saturation means. These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter and with respect to the following figures, wherein

Fig.1 shows a block diagram of a three-operand arithmetic circuitry according to a first embodiment of the invention;

Fig. 2 shows a block diagram of a multi-operand arrangement according to a second embodiment of the invention; and Fig. 3 shows a block diagram of a multi-operand arithmetic circuitry according to a third embodiment of the invention.

Fig. 1 shows a block diagram of a three-operand arithmetic circuitry according to the first embodiment of the invention. Three binary input numbers BINl, BIN2 and BIN3 are input to the arithmetic circuitry AC. The first and second binary input numbers BESf 1, BIN2 have smaller bit-widths bwl, bw2 than the third binary number BIN3. The first and second binary input numbers BINl, BIN2 are input to a first and a second extension unit EUl, EU2. In the extension units EUl, EU2, the binary input numbers BINl, BIN2 are sign or zero extended respectively, to have the same bit -width as the bit-width bw3 of the third binary input number BIN3. The two sign extension units EUl, EU2 are connected to the inputs of a first two-operand arithmetic unit AUl. The arithmetic unit AUl performs a calculation step on its two inputs. This calculation step can be a subtraction or an addition or any similar operation on the two input operands. The output of the first two-operand arithmetic unit AUl is controlled by a first overflow and saturation unit OSUl . The overflow and saturation unit OSUl checks the output of the first two-operand arithmetic unit AUl, detects a possible overflow and saturates the calculation result according to the detected overflow. If for example the bit-width bw3 of the third binary input number BIN3 is 8 bit, the bit-widths bw4, bw5 of the extended binary input numbers BINl and BIN2 have also a bit- width of 8 bit. The output of AUl is then 9 bit or 10 bit wide. The overflow and saturation unit OSUl restricts the result to 8 bit. The output of OSUl has the bit-width bw7, which is equal to the bit-width bw3 of the binary input number BIN3. After being saturated in OSUl, the output of the first overflow and saturation unit OSUl is input to a second two-operand arithmetic unit AU2. The second input to the second two-operand arithmetic unit AU2 is the third binary input number BESf 3, on which an arithmetic operation is to be performed. Both inputs have the same bit-widths, since bw7 equals bw3. This is due to the first and second extension units EUl, EU2, which extend the first and second binary input numbers BINl, BIN2 to the same bit-width as the third binary input number BIN3 and due to OSUl. The output of the second two-operand arithmetic unit AU2 is overflow controlled and saturated according to a detected overflow by a second overflow and saturation unit OSU2. The bit- width bw8 of the output of AU2 is 9 bit or 10 bit. After being overflow and saturation controlled in OSU2, the result is again restricted to a bit-width of 8 bit. If subsequent calculation or processing stages can handle more than 8 bit, OSU2 can be omitted. In case that both two-operand arithmetic units AUl and AU2 perform an addition, the output of the second overflow and saturation unit OSU2 is the correct sum of the three binary input numbers BINl, BIN2 and BIN3. In case that both two-operand arithmetic units AUl and AU2 perform a subtraction, the output of the second overflow and saturation unit OSU2 is the correct difference of the three binary input numbers BINl, BIN2 and BIN3.

Fig. 2 shows a block diagram of a second embodiment of the invention. Four binary input numbers BINl - BIN4 are input to the arithmetic circuitry AC. Four input units IUl - IU4 are provided for inputting the four binary input numbers BINl - BIN4, respectively. The input units IUl - IU4 are input pins or equivalent connections or even latches or the like, to input the binary input numbers BIN1-BIN4 to the arithmetic circuitry AC. The four input units IUl - IU4 may be arranged separately on the same or on different sides of the arithmetic circuitry AC. Furthermore, the four input units IUl - IU4 can be realized as one block, wherein input pins or connections or latches are reused for inputting two or more binary input numbers BINl - BIN4. The binary input numbers BINl - BIN3 have smaller bit-widths bwl, bw2, bw3 than the bit-width bw4 of the fourth binary input number BIN4. The outputs of the input units IUl, IU2, IU3 have bit-widths bw5, bw6, bw7, respectively which are typically equal to bwl, bw2, bw3. This does not exclude that the binary input signals are made symmetric in the input units. Extension units EUl to EU3 are provided for the binary input numbers BINl - BIN3 having bit-widths bw5, bw6 and bw7, respectively. The extended binary input numbers BINl and BIN2 have the same bit- width bw8, bw9, and are added or subtracted in a first two-operand arithmetic unit AUl. The output of the first arithmetic unit AUl has a bit-width bwl2 and is overflow and saturation controlled by a first overflow and saturation unit OSUl . After being extended to the bit-width bwl 6 in the third extension unit EU3, the third binary input number BIN3 is combined with the output of the first overflow and saturation unit OSUl. The output of the second arithmetic unit AU2 is overflow and saturation controlled by a second overflow and saturation unit OSU2. The overflow and saturation controlled output is passed to a third two-operand arithmetic unit AU3. This unit performs an operation on the output of the second overflow and saturation unit OSU2 and the fourth binary input number BIN4. The output of the third two-operand arithmetic unit AU3 is overflow and saturation controlled by a third overflow and saturation unit OSU3.

In case that all the three two-operand arithmetic units AUl - AU3 perform an addition, the output of the third overflow and saturation unit OSU3 is the correct sum of the three binary input numbers BINl - BIN4. However, several different configurations and corresponding results may be achieved, when the three algorithmic units AUl - AU3 perform different calculation operations or if signed binary input numbers BIN1-BIN4 are processed. The outputs of the first algorithmic unit AUl has a bit width bwl2, that is one or two bit wider than the bit-width bw8, bw9 of the two input operands to the algorithmic unit AUl. The bit-width bwl2 is restricted in OSUl to the bit-width bwl3, that is equal to bwlO. The output of the second algorithmic unit AU2 has a bit- width bwl4 that is restricted in OSU2 to the bit-width bwl5. bwl5 is equal to bwl 1. bwl 1 is equal to bw4. The two binary numbers having the bit- width bwl 5 and bwl 1 are fed to the algorithmic unit AU3. The output has a bit- width bwl 6, being one or two bit greater than the bit- width bwl 5 and bwl 1 of the inputs to AU3. The output of AU3 is fed to OSU3, where it is restricted to the bit- width bwl7. bwl7 is equal to bw4. It is also possible that bwl7 is one or two bits greater than bw4.

Fig. 3 shows a block diagram of a third embodiment of the invention which constitutes an alternative embodiment to the second embodiment. Four binary input numbers BINl - BIN4 are input to the arithmetic circuitry AC. Four input units IUl - IU4 are provided for inputting the four binary input numbers BINl - BIN4, respectively. The input units IUl - IU4 are input pins or equivalent connections or even latches, buffers or the like, to input the binary input numbers BINl - BIN4 to the arithmetic circuitry AC. The four input units IUl - IU4 may be arranged separately on the same or on different sides of the arithmetic circuitry AC. Further, the four input units IUl - IU4 can be realized as one block, wherein input pins or connections or latches are reused for inputting two or more binary input numbers BINl - BIN4. The binary input numbers BINl to BIN3 have a smaller bit- width bwl, bw2, bw3 than the bid- width bw4 of the fourth binary input number BIN4. Accordingly, extension units EUl to EU3 are provided for the binary input numbers BINl - BIN3. The extension units EUl - EU3 are optionally provided with a single-bit control input. If the single-bit control input is "HIGH", the sign extension unit EUl, EU2, or EU3 performs a sign-extension. If the single-bit control input is "LOW", the sign-extension unit EUl, EU2, or EU3 performs a zero extension. If such a sign-extension control is used, all extension units EU1-EU3 must be controlled by the same sign signal, indicating if signed or unsigned operation has to be performed. The extended binary input numbers BINl and BIN2 are added or subtracted in a first two-operand arithmetic unit AUl. The output of AUl has a bit-width bwl2. The third and fourth binary input numbers BIN3 and BIN4 are added or subtracted in a second two-operand arithmetic unit AU2. The outputs of the first and second arithmetic units AUl, AU2 having the bit-widths bwl2, bwl3 are overflow and saturation controlled by a first and a second overflow and saturation unit OSUl and OSU2 and restricted to bit-widths bwl4, bwl5, respectively. The overflow and saturation controlled outputs have equal bit- widths bwl5, bwlό, and they are passed to a third two-operand arithmetic unit AU3. This unit calculates the sum or difference of the two overflow and saturation controlled outputs of the first and second two-operand arithmetic units AUl and AU2. The output of the third two- operand arithmetic unit AU3 has the bit- width bwlό and is overflow and saturation controlled by a third overflow and saturation unit OSU3. The bit-width of the output of OSU3 is bwl7. bwl7 is equal to bw4 or 1 or 2 bits greater, in case subsequent calculation or processing units can handle greater bit-widths. In case that all the three two-operand arithmetic units AUl - AU3 perform an addition, the output of the third overflow and saturation unit OSU3 is the correct sum of the three binary input numbers BINl - BIN4. However, several different configurations and corresponding results may be achieved, when the three algorithmic units AUl - AU3 perform different calculation operations or if signed binary input numbers are processed. According to a further embodiment of the present invention a designing method for designing an arithmetic circuitry AC is provided. Particularly, the respective algorithmic circuitry AC of the first, second and third embodiments shown in Figs. 1, 2 and 3 can be the result of an automatic or semi-automatic design synthesis process. The rules for the design procedure for 4 binary input numbers with varying bit-widths can be defined as follows. First, input units IUl, IU2, IU3, IU4 for inputting the 4 binary input numbers BINl- BIN4 to the arithmetic circuitry are provided. Furthermore, three extension units EUl, EU2, EU3 for performing a sign or zero extension of the binary input numbers BINl, BIN2, BIN3 is provided. Three two-operand arithmetic units AUl, AU2, AU3 are provided in a further design step. With respect to the arithmetic units AUl - AU3 three overflow and saturation units OSUl, OSU2, OSU3 for detecting a calculation overflow the three two-operand arithmetic units AUl, AU2, AU3 are provided, wherein the overflow and saturation units OSUl, OSU2, OSU3 saturate the calculation result of the arithmetic units AUl, AU2, AU3 in accordance with the detected overflow result. Finally, connections between the input units IUl, IU2, IU3, the extension units EUl, EU2, EU3, the arithmetic units AUl, AU2, AU3 and the overflow and saturation units OSUl, OSU2, OSU3 are provided. All the mentioned steps are performed such that based on the resulting schematic or layout a circuitry as exemplarily shown in Figures 2 or 3 can be manufactured.

According to still a further embodiment of the present invention the use of two-operand arithmetic units AUl - AU3 for calculating a sum or a difference of four binary input numbers BINl, BIN2, BIN3, BIN4 is provided. The binary input numbers BINl, BIN2, BIN3 differ in their bit-widths. In a first step the binary numbers BINl - BIN3 are extended to have the same bit-width as the fourth binary input number BIN4. Three two- operand arithmetic units AUl, AU2, AU3 are used, each for calculating an addition or a subtraction of two operands. In another step an overflow of the calculation result of the algorithmic units AUl- AU3 is detected and the calculation result is saturated in accordance with the detected overflow result.

All mentioned embodiments of the present invention may comprise input units for inputting binary input numbers. However, input units are not necessarily part of the embodiments. Each input unit may provide a single-bit control input to switch between sign and zero extension in response to the control input's value.

The scope of the present invention is not limited to any particular format or representation of binary input numbers, be it an integer or an floating point format, be it a signed or unsigned representation. Although the above embodiments have been described with respect to the standard 2's complement representation of integers, the present invention should not be considered as being restricted to this representation of binary numbers.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parenthesis shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. In the device claim in numerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are resided in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Furthermore, any reference signs in the claims shall not be constitute as limiting the scope of the claims.

Claims

CLAIMS:

1. Electronic device, comprising arithmetic circuitry (AC) for performing at least one of an addition or a subtraction of more than two binary input numbers (BINl, BIN2, BIN3, BIN4), wherein at least two of the binary input numbers (BINl, BIN2, BIN3, BIN4) differ in their bit-widths, the arithmetic circuitry (AC) comprising: an extension means (EUl, EU2, EU3) for performing at least one of a sign and zero extension of at least one of the binary input numbers (BINl, BIN2, BIN3, BIN4), at least two two-operand arithmetic units (AUl, AU2, AU3), each for calculating at least one of an addition and a subtraction of two operands being a first and a second binary number, an overflow and saturation means (OSUl, OSU2, OSU3) for detecting a calculation overflow of at least one two-operand arithmetic unit (AUl, AU2, AU3) and for saturating the calculation result of the two-operand arithmetic unit (AUl, AU2, AU3) in accordance with the detected overflow result.

2. Electronic device according to claim 1, wherein the arithmetic circuitry (AC) further comprises an input means (IUl, IU2, IU3, IU4) for inputting at least one binary input number (BINl, BIN2, BIN3, BIN4) to the extension means (EUl - EU3).

3. Electronic device according to claim 1 or 2, wherein said arithmetic circuitry (AC) comprises a plurality of extension units (EUl, EU2, EU3) for performing at least one of a sign or zero extension of at least one of the binary input numbers (BINl, BIN2, BIN3, BIN4) for each binary input number having a smaller bit- width than the binary input number having the greatest bit-width.

4. Electronic device according to claim 3, wherein at least one of the extension units (EUl, EU2, EU3) provides an input, in particular a single bit input, for receiving a control signal indicating whether the binary input number (BINl, BIN2, BIN3) is a signed binary number or an unsigned binary number.

5. Electronic device according to one of claims 1 to 4, wherein the arithmetic circuitry (AC) comprises a plurality of overflow and saturation units (OSUl, OSU2, OSU3) each for detecting a calculation overflow of one two-operand arithmetic unit (AUl, AU2, AU3) and for saturating the calculation result of the two-operand arithmetic unit (AUl, AU2, AU3) in accordance with the detected overflow result.

6. Data processing system, comprising at least one electronic device according to anyone of the claims 1 to 5.

7. Method for calculating at least one of a sum and a difference of N binary input numbers (BINl, BIN2, BIN3, BIN4), wherein N is greater than two and at least two of the binary input numbers (BINl, BIN2, BIN3, BIN4) differ in their bit-widths, comprising the steps of: extending at least one first binary input number (BINl, BIN2, BIN3, BIN4) with a shorter bit- width to have the same bit- width as a second binary input number (BINl, BIN2, BIN3, BIN4); using N-I two-operand arithmetic unit (AUl, AU2, AU3) each for calculating at least one of an addition and a subtraction of two operands, and performing the calculation, detecting an overflow of the calculation result; and saturating the calculation result in accordance with the detected overflow result,

8. Method for designing arithmetic circuitry (AC) for performing at least one of an addition and a subtraction of N binary input numbers (BINl, BIN2, BIN3, BIN4), wherein N is greater than two and at least two of the binary input numbers differ in their bit-widths, the method comprising: providing input means (IUl, IU2, IU3, IU4) for inputting the N binary input numbers to the arithmetic circuitry (AC), providing an extension means (EUl, EU2, EU3) for performing at least one of a sign and a zero extension of at least one of the binary input numbers (BINl, BIN2, BIN3, BIN4), providing N-I two-operand arithmetic units (AUl, AU2, AU3), each for calculating at least one of an addition and a subtraction of two operands being a first and a second binary number, - providing overflow and saturation means (OSUl, OSU2, OSU3) for detecting a calculation overflow of at least one two-operand arithmetic unit (AUl, AU2, AU3) and for saturating the calculation result of the arithmetic unit (AUl, AU2, AU3) in accordance with the detected overflow result, providing connections between the input means (IUl, IU2, IU3), extension means (EUl , EU2, EU3), the arithmetic units (AUl , AU2, AU3) and the overflow and saturation means (OSUl, OSU2, OSU3).

9. Method according to claim 8, comprising the step of providing connections in the arithmetic circuitry (AC) such that each output of the N-I two-operand arithmetic units (AUl , AU2, AU3) is connected to the overflow and saturation means (OSUl , OSU2, OSU3).

10. Computer program comprising program code means for causing a computer to carry out the steps of the method as claimed in claim 7 or 8 when said computer program is run on a computer.