EP1812928A4 - Video processing - Google Patents

Video processing

Info

Publication number
EP1812928A4
EP1812928A4 EP05851664A EP05851664A EP1812928A4 EP 1812928 A4 EP1812928 A4 EP 1812928A4 EP 05851664 A EP05851664 A EP 05851664A EP 05851664 A EP05851664 A EP 05851664A EP 1812928 A4 EP1812928 A4 EP 1812928A4
Authority
EP
European Patent Office
Prior art keywords
video processing
video processor
processing
video
multidimensional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05851664A
Other languages
German (de)
French (fr)
Other versions
EP1812928A2 (en
Inventor
Shirish Gadre
Ashish Karandikar
Stephen Lew
Christopher T Cheng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nvidia Corp
Original Assignee
Nvidia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/267,638 external-priority patent/US8493396B2/en
Application filed by Nvidia Corp filed Critical Nvidia Corp
Publication of EP1812928A2 publication Critical patent/EP1812928A2/en
Publication of EP1812928A4 publication Critical patent/EP1812928A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/85—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • General Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
  • Image Analysis (AREA)

Abstract

A latency tolerant system for executing video processing operations is described. So too is a stream processing in a video processor, a video processor having scalar and vector components and multidimensional datapath processing in a video processor.
EP05851664A 2004-11-15 2005-11-14 Video processing Withdrawn EP1812928A4 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US62841404P 2004-11-15 2004-11-15
US11/267,638 US8493396B2 (en) 2004-11-15 2005-11-04 Multidimensional datapath processing in a video processor
US11/267,700 US8698817B2 (en) 2004-11-15 2005-11-04 Video processor having scalar and vector components
US11/267,599 US8416251B2 (en) 2004-11-15 2005-11-04 Stream processing in a video processor
US11/267,875 US8687008B2 (en) 2004-11-15 2005-11-04 Latency tolerant system for executing video processing operations
PCT/US2005/041329 WO2006055546A2 (en) 2004-11-15 2005-11-14 A video processor having a scalar component controlling a vector component to implement video processing

Publications (2)

Publication Number Publication Date
EP1812928A2 EP1812928A2 (en) 2007-08-01
EP1812928A4 true EP1812928A4 (en) 2010-03-31

Family

ID=36407688

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05851664A Withdrawn EP1812928A4 (en) 2004-11-15 2005-11-14 Video processing

Country Status (5)

Country Link
EP (1) EP1812928A4 (en)
JP (1) JP4906734B2 (en)
KR (5) KR100917067B1 (en)
CA (1) CA2585157A1 (en)
WO (1) WO2006055546A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0519597D0 (en) * 2005-09-26 2005-11-02 Imagination Tech Ltd Scalable multi-threaded media processing architecture
US9606801B2 (en) 2013-09-06 2017-03-28 Huawei Technologies Co., Ltd. Method and apparatus for asynchronous processor based on clock delay adjustment
US10275370B2 (en) * 2015-01-05 2019-04-30 Google Llc Operating system dongle
KR102067714B1 (en) * 2016-11-17 2020-01-17 주식회사 엘지화학 Battery module and battery pack including the same
WO2019173075A1 (en) * 2018-03-06 2019-09-12 DinoplusAI Holdings Limited Mission-critical ai processor with multi-layer fault tolerance support
KR102067128B1 (en) * 2018-06-07 2020-01-16 코츠테크놀로지주식회사 Health monitoring device and large area display including the same
WO2022220835A1 (en) * 2021-04-15 2022-10-20 Zeku, Inc. Shared register for vector register file and scalar register file

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US6239810B1 (en) * 1995-11-22 2001-05-29 Nintendo Co., Ltd. High performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing

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US4985848A (en) * 1987-09-14 1991-01-15 Visual Information Technologies, Inc. High speed image processing system using separate data processor and address generator
US4965716A (en) * 1988-03-11 1990-10-23 International Business Machines Corporation Fast access priority queue for managing multiple messages at a communications node or managing multiple programs in a multiprogrammed data processor
US4958303A (en) * 1988-05-12 1990-09-18 Digital Equipment Corporation Apparatus for exchanging pixel data among pixel processors
US5210834A (en) * 1988-06-01 1993-05-11 Digital Equipment Corporation High speed transfer of instructions from a master to a slave processor
US5040109A (en) * 1988-07-20 1991-08-13 Digital Equipment Corporation Efficient protocol for communicating between asychronous devices
JPH0795766B2 (en) * 1989-06-30 1995-10-11 株式会社日立製作所 Digital data communication device and data communication adapter used therefor
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US5418973A (en) * 1992-06-22 1995-05-23 Digital Equipment Corporation Digital computer system with cache controller coordinating both vector and scalar operations
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US5574944A (en) * 1993-12-15 1996-11-12 Convex Computer Corporation System for accessing distributed memory by breaking each accepted access request into series of instructions by using sets of parameters defined as logical channel context
JPH0877347A (en) * 1994-03-08 1996-03-22 Texas Instr Inc <Ti> Data processor for image/graphics processing and its operating method
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US5893066A (en) * 1996-10-15 1999-04-06 Samsung Electronics Co. Ltd. Fast requantization apparatus and method for MPEG audio decoding
US5949410A (en) * 1996-10-18 1999-09-07 Samsung Electronics Company, Ltd. Apparatus and method for synchronizing audio and video frames in an MPEG presentation system
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US7305540B1 (en) * 2001-12-31 2007-12-04 Apple Inc. Method and apparatus for data processing
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US6239810B1 (en) * 1995-11-22 2001-05-29 Nintendo Co., Ltd. High performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing
US5978838A (en) * 1996-08-19 1999-11-02 Samsung Electronics Co., Ltd. Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor

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ESPASA R ET AL: "Decoupled vector architectures", HIGH-PERFORMANCE COMPUTER ARCHITECTURE, 1996. PROCEEDINGS., SECOND INT ERNATIONAL SYMPOSIUM ON SAN JOSE, CA, USA 3-7 FEB. 1996, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 3 February 1996 (1996-02-03), pages 281 - 290, XP010162067, ISBN: 978-0-8186-7237-8, DOI: 10.1109/HPCA.1996.501193 *

Also Published As

Publication number Publication date
WO2006055546A2 (en) 2006-05-26
KR101002485B1 (en) 2010-12-17
KR100917067B1 (en) 2009-09-15
KR101084806B1 (en) 2011-11-21
EP1812928A2 (en) 2007-08-01
KR20090020715A (en) 2009-02-26
KR20110011758A (en) 2011-02-08
KR100880982B1 (en) 2009-02-03
WO2006055546A9 (en) 2007-09-27
WO2006055546A3 (en) 2008-06-19
KR20070063580A (en) 2007-06-19
JP4906734B2 (en) 2012-03-28
KR20100093141A (en) 2010-08-24
KR101030174B1 (en) 2011-04-18
KR20080080419A (en) 2008-09-03
CA2585157A1 (en) 2006-05-26
JP2008521097A (en) 2008-06-19

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