EP1805793A1 - Electromigration control - Google Patents

Electromigration control

Info

Publication number
EP1805793A1
EP1805793A1 EP05791928A EP05791928A EP1805793A1 EP 1805793 A1 EP1805793 A1 EP 1805793A1 EP 05791928 A EP05791928 A EP 05791928A EP 05791928 A EP05791928 A EP 05791928A EP 1805793 A1 EP1805793 A1 EP 1805793A1
Authority
EP
European Patent Office
Prior art keywords
electrically conductive
vacancy
conductive line
dams
electromigration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05791928A
Other languages
German (de)
French (fr)
Inventor
Jean-Philippe Société Civile SPID JACQUEMIN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to EP05791928A priority Critical patent/EP1805793A1/en
Publication of EP1805793A1 publication Critical patent/EP1805793A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances

Abstract

A method of controlling electromigration, and the adverse effects thereof, in a patterned, electrically conductive layer (9) of a semiconductor device. A plurality of vacancy dams (10) are created at respective locations along the length of a metal interconnect (9) by implantation of selected atoms. Each vacancy dam (10) causes vacancies created by electromigration (8) to accumulate thereat, thereby distributing the total effect of such electromigration along the length of the line (9) and significantly increasing the life span of the semiconductor device.

Description

ELECTROMIGRATION CONTROL
FIELD OF THE INVENTION
This invention relates generally to the control of electromigration in a patterned electrically conductive layer of a semiconductor device.
BACKGROUND OF THE INVENTION
Aluminium has, in the past, been the principal conductive material employed for electrical interconnection in semiconductor devices due to its low resistivity, good adherence to silicon dioxide, low cost, ease in bonding and good etchability. The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor geometries. As device geometry continues to scale down for Ultra Large Scale Integrated circuits, there is a growing demand for an interconnect wiring with minimum pitch and high conductivity, while requiring greater levels of reliability. Currently, an integrated circuit die is considered to be good if a test indicates an equivalent life span of 10 years. However, in some specific applications such as space (e.g. satellite, probe, etc), medical (e.g. pacemakers, and the like) and military, a longer life span may be required, so as to avoid or minimize the requirement for device replacement.
The use of copper and copper-based materials is now widely established and has been found to result in a higher performance with respect to semiconductor devices. In fact, in many cases, copper has replaced aluminium because of its lower resistivity and higher reliability, which is thought to be because of its higher activation energy for diffusion. One of the main phenomena that cause an interconnect layer to degrade is electromigration, in which atoms of the interconnect physically change location as current passes through the interconnect.
Electromigration generally is defined as atoms constituting a line that move when current flows into the line due to electrons, and it will be appreciated that copper still suffers from electromigration reliability issues as geometries continue to shrink and current densities increase. Under high current densities, copper atoms move in the direction of the electron flow, and vacancies accumulate in the opposite direction into voids that have the effect of increasing circuit resistance and eventually causing an open circuit, which causes the device to fail. In the known copper damascene process, and referring to Figure 1 of the drawings, the copper interconnect line 9, provided in respect of a substrate 5, is generally encapsulated on the sides and bottom by barrier metal 6, and on top by barrier/etch stop dielectric 10. Referring to Figures 2a and 2b of the drawings, and as mentioned above, before device failure, under high current densities, copper atoms move in the direction of the electron flow 7 and vacancies "flow" in the opposite direction 8. The vacancies accumulate at an interface of the device, in this case, the metal/barrier interface 4, into a void 3 that eventually creates an open circuit (i.e. a "killer void") and causes the device to fail, after x years, say. In other words, a void becomes a "killer" void when a sufficient number of vacancies have accumulated to create an open circuit.
In order to suppress or reduce the effects of electromigration, many studies have been performed in respect of the interconnect material, i.e. the crystalline structure, reduction of grain boundaries, etc, whereas other studies have concentrated on the interface between the barrier and the metal. All such studies have concentrated on reducing the impact of vacancy flow caused by electromigration, rather than actually suppressing the occurrence of electromigration.
US Patent Application Publication No. US 2004/0041274 Al describes a semiconductor device structure comprising first and second interconnects with a primary structure (e.g. a via or the like) therebetween. The primary structure defines an interface with the interconnects so, in order to diffuse the effects of electromigration at the interface, a buffer structure (e.g. a dummy via) is provided on the first interconnect which defines another interface in respect of which vacancies can accumulate, thereby diffusing (or "diluting" the effects of electromigration). However, this proposal involves modification of the device design, not to mention the increased overhead of depositing structures which are unnecessary to the actual function of the device.
SUMMARY OF THE INVENTION
We have now devised an improved arrangement, and it is an object of the present invention to provide a semiconductor device including one or more electrically conductive lines, in which the effects of electromigration are significantly reduced, without the need to modify the device design, structure or layout. It is also an object of the invention to provide a method of manufacturing such a semiconductor device, and an integrated circuit die comprising a plurality of such semiconductor devices. In accordance with the present invention, there is provided a method of forming an electrically conductive line on a substrate of an integrated circuit, the method comprising depositing a line of electrically conductive material on said substrate, and altering, by implantation of selected atoms, the crystalline structure of said electrically conductive line at one or more locations along the length thereof, so as to create respective one or more vacancy dams for causing vacancies created by electromigration within said electrically conductive line during operation to accumulate thereat.
Also in accordance with the present invention, there is provided a method of manufacturing an integrated circuit comprising one or more semiconductor devices, the method comprising depositing one or more electrically conductive lines on a substrate, the method further comprising altering the crystalline structure of the or each conductive line at one or more locations along the length thereof by implantation of one or more selected atoms so as to create one or more respective vacancy dams for causing vacancies created by electromigration within a respective electrically conductive line during operation to accumulate thereat.
The present invention also extends to an integrated circuit comprising one or more semiconductor devices and one or more electrically conductive lines provided on a substrate, wherein the or each conductive line comprises one or more vacancy dams along the length thereof, at which vacancy dams vacancies created by electromigration within the respective conductive line are caused to accumulate, in use, wherein said one or more vacancy dams are formed by altering the crystalline structure of a respective portion of the respective conductive line by implantation of one or more selected atoms.
The or each electrically conductive line is preferably a metal, such as aluminium or, more preferably, copper due to its lower resistivity and higher reliability. The atoms selected for implantation are intended to alter the crystalline structure of the electrically conductive line at the location of implantation to the extent that vacancy flow is substantially halted, without significantly decreasing the electrical conductivity of the line. The atoms may be of the same type as the material of the electrically conductive line, but not necessarily — other atoms, either of a single type or a combination of two or more types, may be selected. A plurality of vacancy dams created by implantation of atoms are preferably provided along the length of the electrically conductive line, possibly at substantially equidistant intervals, so as to substantially equally distribute the diffusive effect thereof along the length of the line. These and other aspects of the present invention will be apparent from, and elucidated with reference to, the embodiment described herein.
BRIEF DESCRIPTION OF THE DRAWINGS An embodiment of the present invention will now be described by way of example only and with reference to the accompanying drawings, in which:
Figure 1 is a schematic cross-sectional view of an electrically conductive interconnect;
Figure 2a is a schematic side view of a portion of electrically conductive interconnect, indicating the respective directions of flow of electrons and vacancies;
Figure 2b is a schematic side view of a portion of the electrically conductive interconnect of Figure 2a, indicating a killer void formed at the barrier after x years of operation of a respective integrated circuit;
Figure 3a is a schematic side view of a portion of an electrically conductive interconnect according to an exemplary embodiment of the present invention; and
Figure 3b is a schematic side view of a portion of the electrically conductive interconnect of Figure 3a, indicating non-killer voids formed at the "vacancy dams after x years of operation of a respective integrated circuit.
DETAILED DESCRIPTION OF THE INVENTION
Thus, the present invention proposes a method of diffusing or distributing the total effects over a period of x years of electromigration within an electrically conductive interconnect of an integrated circuit by creating one or, more preferably, several vacancy dams distributed (preferably at substantially equidistant intervals) along the length of the conductive line so as to effectively divide its volume.
An exemplary embodiment of the invention is illustrated schematically in Figure 3a, which shows a portion of an electrically conductive (e.g. aluminiuiri or, more preferably, copper) line 9 having a barrier 6. A plurality of vacancy dams 10 are created at respective equidistant intervals along the length of the line 9 to divide the vohume of the line 9 into sections. These vacancy dams may be created by the implantation o f copper (Cu) or other specific atoms so as to disturb the crystallographic structure of the electrically conductive line at the location of implantation.
For example, carbon atoms implanted into copper do not modify the structure of the copper, and the resultant structure is stable (i.e. the carbon atoms do not react with the copper) up to around 7000C in a vacuum (10-6mbar). Tungsten atoms could also be implanted in a copper line to create the desired vacancy atoms, as tungsten also does not alter the structure of the copper, and the resultant structure is stable up to around 45O0C. Other suitable atoms for implantation in the conductive line to create the desired vacancy atoms will be apparent to a person skilled in the art, and the present invention is not necessarily intended to be limited in this regard.
As a result, vacancies flowing in the direction 8 in each section of the conductive line 9 accumulate at the next vacancy dam 10. Thus, instead of all vacancies accumulating at the barrier 6 to eventually create a killer void (3, Figure 2b) after x years (i.e. the failure time of the conventional structure, as illustrated in Figures 2a and 2b), the accumulation of vacancies is distributed between the barrier 3 and the three vacancy dams 10, such that after x years of operation, the effect of the accumulation of vacancies at each dam and the barrier is significantly less than it would have been if all of the vacancies created over that period of time had been allowed to accumulate at the barrier 3, as in the prior art. The net result is that instead of one killer void being created at the barrier 6, a non-killer void 11 may be created at each dam 10 and the barrier 6 after x years, and the device can continue to operate effectively for longer. In fact, it may be several further years of operation before a killer void is created at any of the vacancy dams 10 or the barrier 6. This is because less vacancies accumulate at the barrier and each dam over the same period of time (because vacancy accumulation is distributed along the length of the line 9), so it takes much longer for sufficient vacancies to accumulate to create a "killer" void at any one of these locations.
The main consideration here is to select the atoms for implantation (in respect or the conductive line in question) so as to substantially halt vacancy flow, without significantly adversely affecting the conductivity of the electrically conductive line.
It should be noted that the above-mentioned embodiment illustrates rather than limits the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as- limiting the claims. The word "comprising" and "comprises", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification, as a whole. The singular reference of an element does not exclude the plural reference of suclα elements and vice- versa. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A method of forming an electrically conductive line (9) on a substrate of an integrated circuit, the method comprising: depositing a line (19) of electrically conductive material on said substrate (5), and - altering, by implantation of selected atoms, the crystalline structure of said electrically conductive line (9) at one or more locations along the length thereof, so as to create respective one or more vacancy dams (10) for causing vacancies created by electromigration (8) within said electrically conductive line (9) during operation to accumulate thereat.
2. A method according to claim 1, wherein the or each electrically conductive line (9) is formed of copper.
3. A method according to claim 1, wherein the atoms selected for implantation are intended to alter the crystalline structure of the electrically conductive line (9) at the location of implantation to the extent that vacancy flow is substantially halted, without significantly decreasing the electrical conductivity of the line (9).
4. A method according to claim 1, wherein a plurality of vacancy dams (10) created by implantation of atoms are provided along the length of the electrically conductive line (9).
5. A method according to claim 4, wherein said plurality of vacancy dams (10) are provided at substantially equidistant intervals along the length of the conductive line (9).
6. A method of manufacturing an integrated circuit comprising one or more semiconductor devices, the method comprising: depositing one or more electrically conductive lines (9) on a substrate (5), and altering the crystalline structure of the or each conductive line (9) at one or more locations (10) along the length thereof by implantation of one or more selected atoms so as to create one or more respective vacancy dams (10) for causing vacancies created by electromigration (8) within a respective electrically conductive line (9) during operation to accumulate thereat.
7. An integrated circuit comprising one or more semiconductor devices and one or more electrically conductive lines (9) provided on a substrate (5), wherein the or each conductive line (9) comprises one or more vacancy dams (10) along the length thereof, at which vacancy dams (10) vacancies created by electromigration (8) within the respective conductive line (9) are caused to accumulate, in use, wherein said one or more vacancy dams (10) are formed by altering the crystalline structure of a respective portion of the respective conductive line (9) by implantation of one or more selected atoms.
EP05791928A 2004-10-22 2005-10-17 Electromigration control Withdrawn EP1805793A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP05791928A EP1805793A1 (en) 2004-10-22 2005-10-17 Electromigration control

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP04300709 2004-10-22
EP05791928A EP1805793A1 (en) 2004-10-22 2005-10-17 Electromigration control
PCT/IB2005/053392 WO2006043224A1 (en) 2004-10-22 2005-10-17 Electromigration control

Publications (1)

Publication Number Publication Date
EP1805793A1 true EP1805793A1 (en) 2007-07-11

Family

ID=35429284

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05791928A Withdrawn EP1805793A1 (en) 2004-10-22 2005-10-17 Electromigration control

Country Status (4)

Country Link
EP (1) EP1805793A1 (en)
JP (1) JP2008518433A (en)
CN (1) CN101044612A (en)
WO (1) WO2006043224A1 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3369660B2 (en) * 1992-08-31 2003-01-20 株式会社東芝 Semiconductor device
JP3415387B2 (en) * 1997-02-18 2003-06-09 株式会社東芝 Semiconductor device and manufacturing method thereof
JP4083921B2 (en) * 1998-05-29 2008-04-30 株式会社東芝 Manufacturing method of semiconductor device
KR100382544B1 (en) * 2000-11-22 2003-05-09 주식회사 하이닉스반도체 Method for Fabricating Line of Semiconductor Device
US6579795B1 (en) * 2002-04-02 2003-06-17 Intel Corporation Method of making a semiconductor device that has copper damascene interconnects with enhanced electromigration reliability

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2006043224A1 *

Also Published As

Publication number Publication date
JP2008518433A (en) 2008-05-29
WO2006043224A1 (en) 2006-04-27
CN101044612A (en) 2007-09-26

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