EP1800406A2 - Procede de codage et de decodage au moyen du code ldpc et appareil associe - Google Patents

Procede de codage et de decodage au moyen du code ldpc et appareil associe

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Publication number
EP1800406A2
EP1800406A2 EP05787114A EP05787114A EP1800406A2 EP 1800406 A2 EP1800406 A2 EP 1800406A2 EP 05787114 A EP05787114 A EP 05787114A EP 05787114 A EP05787114 A EP 05787114A EP 1800406 A2 EP1800406 A2 EP 1800406A2
Authority
EP
European Patent Office
Prior art keywords
matrix
permutation
base
parity check
permutation matrix
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05787114A
Other languages
German (de)
English (en)
Inventor
Kyu Hyuk Chung
Min Seok Oh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Electronics Inc
Original Assignee
LG Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020040077013A external-priority patent/KR101065693B1/ko
Application filed by LG Electronics Inc filed Critical LG Electronics Inc
Publication of EP1800406A2 publication Critical patent/EP1800406A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal

Definitions

  • the present invention relates to an encoding/decoding method, and more particularly, to a method of encoding/decoding using an LDPC code, method of generating an LDPC code for encoding or decoding and apparatus for encoding and decoding.
  • the present invention is suitable for a wide scope of applications, it is particularly suitable for saving a memory for storing a parity check matrix required for the method of encoding and decoding using the LDPC (low density parity check) code and for enhancing encoding or decoding performance.
  • encoding is a process that a transmitting side performs a data processing for a receiving side to restore original data despite errors caused by signal distortion, loss and the like while the transmitting side transmits data via a communication channel.
  • decoding is a process that the receiving side restores the encoded transmitted data into the original data.
  • the LDPC code is a linear block code having low density since most of elements of a parity check matrix H are zeros, which was proposed by Gallager in 1962. It was difficult to implement the LDPC code that is very complicated due to the technological difficulty in those days. Yet, the LDPC code was taken into re ⁇ consideration in 19 * 95 so that its superior performance has been verified. So, many efforts are made to research and develop the LPDC code. (Reference: [1] Robert G. Gallager, "Low-Density Parity-Check Codes", The MIT Press, September 15, 1963. [2] D.J.C.
  • Equation 1 The LDPC code can be explained by a (n-k) Xn parity check matrix H. And, a generator matrix G corresponding to the parity check matrix H can be found by Equation 1. [Equation 1]
  • a transmitting side encodes input data by Equation 2 using the generator matrix G having a relation of Equation 1 with the parity check matrix H.
  • the parity check matrix H having a size approximately exceeding 1,000X2,000 needs lots of operations in the encoding and decoding processes, has difficulty in its implementation, and requires a considerably large storage space.
  • the present invention is directed to a method of encoding/decoding using an LDPC code and apparatus thereof that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
  • An object of the present invention is to provide a method of encoding/decoding using an LDPC code and apparatus thereof, by which a memory for storing a parity check matrix can be saved for the encoding or decoding using the LDPC code and by which encoding or decoding performance can be enhanced.
  • Another object of the present invention is to provide a method of generating an LDPC code, by which a memory for storing a parity check matrix in an encoding/decoding method using the LDPC code can be saved.
  • a method of encoding/decoding input data using an LDPC (low density parity check) code includes the steps of generating a parity check matrix by expanding a base matrix including a permutation type defining a permutation matrix as at least one element, wherein the permutation matrix is generated from permutating a seguence of at least one of rows and columns of at least one base permutation matrix or rotating the at least one base permutation matrix, and encoding or decoding the input data using the parity check matrix.
  • a method of generating an LDPC code which is defined by an (n-k) Xn matrix H, includes the steps of determining at least one zXz base permutation matrix or a zXz a zXz zero matrix (where z is an integer equal to or greater than 1), determining a (n-k) /zXn/z base matrix H b including information enabling the base permutation matrix to be permutated with each element according to a predetermined rule or information indicating the zero matrix (where n is a length of a codeword and k is a length of an information block) , and generating the matrix H from expanding the base matrix by replacing the base permutation matrix or the zero matrix according to the information.
  • an apparatus for encoding in encoding input data using an LDPC code, includes a parity check matrix generating module generating a parity check matrix by expanding a base matrix including a permutation type defining a permutation matrix as at least one element wherein the permutation matrix is generated from permutating a sequence of at least one of rows and columns of at least one base permutation matrix or rotating the at least one base permutation matrix, and an encoding module encoding the input data using the parity check matrix generated from the parity check matrix generating module.
  • an apparatus for decoding in decoding input data using an LDPC code, includes a parity check matrix generating module generating a parity check matrix by expanding a base matrix including a permutation type defining a permutation matrix as at least one element wherein the permutation matrix is generated from permutating a sequence of at least one of rows and columns of at least one base permutation matrix or rotating the at least one base permutation matrix and a decoding module decoding the input data using the parity check matrix generated from the parity check matrix generating module.
  • the permutation matrix defined by the permutation type is at least one base permutation matrix, a plurality of permutation matrices generated from permutating the sequence of one of the rows and columns of the at least one base permutation matrix or rotating the at least one base permutation matrix, or the zero matrix.
  • each of the permutation types of the base matrix is expanded by being replaced by the permutation matrix defined by the corresponding permutation type, whereby the parity check matrix is generated.
  • the permutation matrix is generated by a first class of shifting each of the rows or columns of the at least one base permutation matrix by a prescribed interval in a predetermined direction, a second class of exchanging a specific one of the rows for a random one of the rows, a third class of exchanging a specific one of the columns for a random one of the columns or a fourth class of rotating the at least one base permutation matrix by 90°, 180° or 270°.
  • FIG. IA is a block diagram of a communication system for explaining one preferred embodiment of the present invention.
  • FIG. IB is a detailed block diagram of an LDPC encoder shown in FIG. IA;
  • FIG. 1C is a detailed block diagram of an LDPC decoder shown in FIG. IA;
  • FIG. 2 is a diagram of a parity check matrix H including a plurality of zxz permutation matrices or a zero matrix;
  • FIG. 3 is a diagram for explaining a method of configuring a plurality of permutation matrices by shifting all rows of a base permutation matrix with a predetermined interval in one preferred embodiment of the present invention
  • FIG. 4 is a diagram for explaining a method of configuring a plurality of permutation matrices by exchanging a specific row of a base permutation matrix for another random row;
  • FIG. 5 is a diagram for explaining a method of configuring a plurality of permutation matrices by exchanging a specific column of a base permutation matrix for another random column;
  • FIG. 6 is a diagram for explaining a method of configuring a plurality of permutation matrices by rotating a base permutation matrix at a specific angle;
  • FIGs. 7A to 7C are diagrams for explaining a method of generating a parity check matrix H using a base permutation matrix and a base matrix H b having information about types of permutation matrices generated from permutating the base permutation matrix according to a combination of four classes in the process of encoding or decoding data in a transmitting or receiving side; and
  • FIGs. 8A to 8C are diagrams for explaining a method of generating a parity check matrix H using two base permutation matrix and a base matrix H b having information about types of permutation matrices generated from permutating the two base permutation matrices according to a combination of four classes in the process of encoding or decoding data in a transmitting or receiving side.
  • FIG. IA is a block diagram of a communication system to explain one preferred embodiment of the present invention, in which a technical feature of the present invention is applied to a wireless communication system for example.
  • a transmitter 10 and a receiver 30 communicate with each other using a radio channel as a medium.
  • a k-bit source data u outputted from a data source 11 is converted to an n-bit codeword c by LDPC encoding of an LDPC encoder 13.
  • the codeword c is radio-modulated by a modulator 15, is transmitted by an antenna 17 via the radio channel 20, and is then received by another antenna 31 of the receiver 30.
  • the receiver 30 goes through a process reverse to that of the transmitter 10. Namely, the source data u can be finally obtained in a manner of demodulation by a demodulator 33 and decoding by an LDPC decoder 35.
  • the above explained data transmitting/receiving process is described within a minimum range required for explaining the features of the present invention. So, it is apparent to those skilled in the art that the corresponding process needs more procedures for the data transmission/reception.
  • FIG. IB is a detailed block diagram of the LDPC encoder 13 shown in FIG. IA and FIG. 1C is a detailed block diagram of the LDPC decoder 35 shown in FIG. IA.
  • the parity check matrix H used for encoding the input source data in the LDPC encoder 13 is (n-k)Xn dimensional.
  • the ⁇ k' means a length (bit unit) of the source data inputted to the LDPC encoder 13.
  • the ⁇ n' means a length (bit unit) of the encoded codeword c.
  • the parity check matrix H as shown in FIG. 2, comprises a plurality of zXz permutation matrices or a zero matrix. Namely, Pij in FIG. 2 means the zXz permutation matrix or zero matrix.
  • a plurality of the permutation matrices can be formed by permutating at least one base permutation matrix with a regularity.
  • a row and column weight is ⁇ l' .
  • one of elements of the entire rows and columns of the plurality of permutation matrices is ⁇ l' and the rest of the elements are ⁇ 0' .
  • the following four methods (classes) can be taken into consideration as the regularity in permutating the at least one base permutation matrix to configure the plurality of permutation matrices.
  • the first class corresponds to a method of shifting the entire rows (or, columns) of the base permutation matrix in a specific direction with a predetermined interval.
  • the first class it is able to generate (z-1) permutation matrices according to an interval of the row or column shifted for a zXz base permutation matrix. Hence, z permutation matrices are generated if the base permutation matrix is included.
  • each of the z permutation matrices including the base permutation matrix can be expressed by one integer.
  • the second class corresponds to a method of exchanging a specific row of the base permutation matrix for another random row.
  • FIG. 4 shows the corresponding example.
  • the permutation matrix of (a) shown in FIG. 4 is generated.
  • the permutation matrix of (a) shown in FIG. 4 is generated.
  • it is able to generate (z-1) permutation matrices according to which row is exchanged for a first row of a zXz base permutation matrix.
  • z permutation matrices are generated if the base permutation matrix is included.
  • the base permutation matrix is able to express each of the permutation matrices as one integer.
  • the permutation matrix is generated by taking the first row as a reference to exchange for another random row. Yet, it is also able to obtain the same result if another random row is taken as a reference.
  • the third class corresponds to a method of exchanging a specific column of the base permutation matrix for another random column.
  • FIG. 5 shows an example of the third class. Referring to FIG. 5, by exchanging a first column of the base permutation matrix for a sixth column of the base permutation matrix, the permutation matrix of (a) shown in FIG. 5 is generated. In the third class, it is able to generate (z-1) permutation matrices according to which column is exchanged for a first column of a zXz base permutation matrix. Hence, z permutation matrices are generated if the base permutation matrix is included.
  • each of the z permutation matrices including the base permutation matrix can be expressed by one integer. For instance, by expressing the base permutation matrix as ⁇ 0' , by expressing a permutation matrix generated from exchanging the first column of the base permutation matrix for a second column of the base permutation matrix as ⁇ l r , and by expressing a permutation matrix generated from exchanging the first column of the base permutation matrix for a third column of the base permutation matrix as ⁇ 2' and the like, it is able to express each of the permutation matrices as one integer. In FIG. 5, the permutation matrix is generated by taking the first column as a reference to exchange for another random column. Yet, it is also able to obtain the same result if another random column is taken as a reference.
  • the fourth class corresponds to a method of generating a permutation matrix by rotating the base permutation matrix by 90°, 180° or 270°.
  • FIG. 6 shows the corresponding example. Referring to FIG. 6, by rotating the base permutation matrix by 90°, the permutation matrix of
  • each of the four permutation matrices including the base permutation matrix can be expressed by one integer.
  • each of the permutation matrices is able to express each of the permutation matrices as one integer.
  • each type of the plurality of permutation matrices generated from the base permutation matrix according to the four classes can be simply expressed as one integer.
  • Such an integer as defining a zXz permutation matrix will be called a permutation type in the following description.
  • ''Expressing the permutation type as an integer' is just exemplary.
  • the permutation type can be expressed in various ways.
  • the present invention it is unnecessary to store the parity check matrix H itself for performing the encoding or decoding.
  • the base matrix H b having the permutation type as each element is stored and expanded into the parity check matrix H by replacing each element with a corresponding permutation matrix during performing the encoding or decoding.
  • the present invention enhances performance of the encoding or decoding.
  • the present invention can save the memory since the parity check matrix itself needs not to be stored.
  • FIG. IB and FIG. 1C are the detailed diagrams of the LDPC encoder 13 and the LDPC decoder 35 in FIG. IA, respectively.
  • the LDPC encoder 13 includes a memory module 131 storing at least one base permutation matrix and a base matrix H b , a parity check matrix generating module 133 expanding the base matrix to generate a parity check matrix H, and an encoding module 135 encoding input data using the parity check matrix generated from the parity check matrix generating module 133.
  • the LDPC decoder 35 includes a memory module 351 storing at least one base permutation matrix and a base matrix H b , a parity check matrix generating module 353 expanding the base matrix to generate a parity check matrix, and an decoding module 355 decoding input data using the parity check matrix generated from the parity check matrix generating module 353.
  • the memory module 131 of the LDPC encoder 13 or the memory module 351 of the LDPC decoder 35 is capable of storing the base matrix H b only.
  • the parity check matrix generating module 133 or 353 generates the parity check matrix H in a manner of expanding the base matrix H b by replacing each permutation type of the base matrix H b with a permutation matrix defined by the permutation type.
  • the permutation matrix may correspond to the at least one base permutation matrix, a plurality of permutation matrices generated from permutating the at least one base permutation matrix according to the aforesaid first to fourth classes or a combination of the four classes, or a zero matrix. It is apparent to those having ordinary skill in the art the parity check matrix generating module 133 or 353 can be implemented by software or hardware.
  • the encoding module 135 encodes the input data using the parity check matrix generated from the parity check matrix generating module 133. And, there are various methods for encoding the input data using the parity check matrix. And, those methods are exemplarily explained as follows .
  • Equation 2 can be replaced by Equation 3.
  • a k-bit input source data si X k is encoded into an n-bit codeword x ⁇ t by Equation 2.
  • the decoding module 355 of the LDPC decoder 35 uses Equation 4 in receiving to decode the data encoded in the above-explained manner.
  • the part H p can employ a block dual diagonal matrix in general.
  • a main diagonal and a diagonal beneath or directly above the main diagonal include identity matrices and the rest include zero matrices.
  • the generation of a short cycle such as a 4-cycle or 6-cycle is minimized in the entire parity check matrix H.
  • the parity check matrix H does not have the 4-cycle.
  • the parity check matrix H has the ⁇ -cycle equal to or smaller than a preset critical value C ma ⁇ -
  • the 4-cycle means a case that two random rows of the parity check matrix H simultaneously have l's at two points, respectively.
  • the 6- cycle means a case that two combinable rows selected from three random rows of the parity check matrix H have l's at the same points, respectively.
  • FIGs. 7A to 7C are diagrams for explaining a method of generating a parity check matrix H using a base permutation matrix and a base matrix H b having information about types of permutation matrices generated from permutating the base permutation matrix according to a combination of four classes in the process of encoding or decoding data in a transmitting or receiving side
  • FIG. 7B shows a base matrix H b including information about permutation types of permutation matrices generated from permutating the base permutation matrix according to a combination of the aforesaid four classes.
  • the permutation type included in the base matrix H b is represented by such a format as (n s , n r , n c , n t ) .
  • the format of (n s , n r , n c , n t ) means the corresponding permutation matrix is generated in a manner of shifting all rows or columns of the base permutation matrix by n s , exchanging a specific row (e.g., 1 st row) for an n r th row, and rotating the base permutation matrix by an angle corresponding to nt.
  • the permutation type (2, 0, 1, 0) means a new permutation matrix generated from shifting all rows or columns in the base permutation matrix shown in FIG. 7A by two rows or columns and exchanging the first and second rows with each other.
  • ⁇ (-1) ' in FIG. 7B means a 5X5 zero matrix.
  • FIG. 7C shows the parity check matrix H generated from the base permutation matrix shown in FIG. 7A and the base matrix H b including the permutation types of the permutation matrices shown in FIG. 7B.
  • the plurality of permutation matrices are generated from the base permutation matrix by a combination of the aforesaid four classes. Instead, the plurality of permutation matrices can be generated by one of the four classes or by a combination of the two or three classes. In case that the plurality of permutation matrices are generated from one of the four classes, the type of the permutation matrix can be expresses as one integer. In case that the plurality of permutation matrices are generated from two of the four classes, the type of the permutation matrix can be expressed as two integers. In case that the plurality of permutation matrices are generated from the combination of the three classes, the type of the permutation matrix can be expressed as three integers.
  • the method of shifting the entire rows or columns of the base permutation matrix of the first class by a predetermined interval with the method of rotating the base permutation matrix by a predetermined angle, it is able to simplify the permutation type included in the base matrix H b to (n s , n r ) from (n s , n r , n c , n t ) .
  • the predetermined angle is set to 90°
  • the type of the permutation matrix can be expressed as one integer s.
  • ⁇ s ⁇ is an integer corresponding to one of 0, 1, ... , (z-1) , z, (z+1), ... , (2Xz-I) .
  • z matrices generated from shifting the zXz base permutation matrix by the predetermined interval and another z matrices generated from rotating the former matrices in a predetermined direction by 90° can be expressed as one integer s.
  • a zXz identity matrix can preferably be used as the base permutation matrix.
  • the permutation matrix type included in the base matrix Hj 3 can be simplified and the LDPC code is represented using the simple information to save the memory for the LDPC code storage and to provide the optimal performance.
  • FIGs. 8A to 8C are diagrams for explaining a method of generating a parity check matrix H using two base permutation matrix and a base matrix H b having information about types of permutation matrices generated from permutating the two base permutation matrices according to a combination of four classes in the process of encoding or decoding data in a transmitting or receiving side.
  • FIGs. 8A to 8C differs from the aforesaid embodiment with reference to FIGs. 7A to 7C in that a plurality of different permutation matrices are generated from two base permutation matrices and in that a permutation type included in a base matrix H b is expressed as a format of (no, n s , n r , n c , nt) as shown in FIG. 8B.
  • the meanings of ⁇ n s , n r , n c and n t ' are identical to the above-explained meanings.
  • ⁇ n ⁇ / is the information indicating that the plurality of different permutation matrices are generated based on which one of the two base permutation matrices.
  • FIG. 8B shows the parity check matrix H generated from the base matrix H b including the information of the types of the two base permutation matrices shown in FIG. 8A and the permutation matrix shown in FIG. 8B.
  • the present invention needs not to store the parity check matrix occupying a memory having a considerably big capacity in encoding or decoding input data, thereby saving the memory and thereby enhancing the encoding/decoding performance.
  • the present invention is applicable to such a wireless communication system as a mobile communication system, a broadband wireless access system and the like and is further applicable to all kinds of fields needing the encoding or decoding.

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

L'invention porte sur un procédé de codage/décodage au moyen du code LDPC et sur l'appareil associé, permettant de sauvegarder une mémoire de stockage de matrice de contrôle de parité. Le procédé de l'invention consiste à générer une matrice de contrôle de parité par expansion d'une matrice de base comprenant un type de permutation définissant une matrice de permutation en tant qu'au moins un élément, cette matrice de permutation étant générée à partir de la permutation d'une séquence d'au moins une des rangées et colonnes d'au moins une matrice de permutation de base ou à partir de la rotation d'au moins une matrice de permutation de base et par codage et décodage des données d'entrée au moyen de la matrice de contrôle de parité.
EP05787114A 2004-09-17 2005-09-14 Procede de codage et de decodage au moyen du code ldpc et appareil associe Withdrawn EP1800406A2 (fr)

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KR20040074732 2004-09-17
KR1020040077013A KR101065693B1 (ko) 2004-09-17 2004-09-24 Ｌｄｐｃ 코드를 이용한 부호화, 복호화 방법 및 부호화또는 복호화를 위한 ｌｄｐｃ 코드 생성 방법
PCT/KR2005/003041 WO2006031062A2 (fr) 2004-09-17 2005-09-14 Procede de codage et de decodage au moyen du code ldpc et appareil associe

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CN100596029C (zh) * 2006-10-20 2010-03-24 北京泰美世纪科技有限公司 Ldpc码校验矩阵构造方法及利用该方法的编码解码装置

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US7178080B2 (en) * 2002-08-15 2007-02-13 Texas Instruments Incorporated Hardware-efficient low density parity check code for digital communications
WO2004019268A1 (fr) 2002-08-20 2004-03-04 Flarion Technologies, Inc. Procédés et appareil permettant de coder des codes ldpc
KR100996029B1 (ko) * 2003-04-29 2010-11-22 삼성전자주식회사 저밀도 패리티 검사 코드의 부호화 장치 및 방법

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