EP1779440A4 - Metal-insulator varactor devices - Google Patents
Metal-insulator varactor devicesInfo
- Publication number
- EP1779440A4 EP1779440A4 EP05769417A EP05769417A EP1779440A4 EP 1779440 A4 EP1779440 A4 EP 1779440A4 EP 05769417 A EP05769417 A EP 05769417A EP 05769417 A EP05769417 A EP 05769417A EP 1779440 A4 EP1779440 A4 EP 1779440A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- insulator
- layer
- conducting
- given voltage
- varactor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000012212 insulator Substances 0.000 title claims abstract description 79
- 239000000463 material Substances 0.000 claims abstract description 17
- 230000004888 barrier function Effects 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 19
- 230000005641 tunneling Effects 0.000 claims description 19
- 238000013459 approach Methods 0.000 claims description 6
- 239000012774 insulation material Substances 0.000 claims 6
- 238000004519 manufacturing process Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 32
- 239000002184 metal Substances 0.000 description 29
- 229910052751 metal Inorganic materials 0.000 description 29
- 238000010586 diagram Methods 0.000 description 12
- 238000013461 design Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 230000004044 response Effects 0.000 description 6
- 238000004458 analytical method Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 230000001419 dependent effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000003574 free electron Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005516 deep trap Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000011176 pooling Methods 0.000 description 1
- 238000005381 potential energy Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/88—Tunnel-effect diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
- H01L27/0808—Varactor diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/93—Variable capacitance diodes, e.g. varactors
Definitions
- FIGURES Ia and Ib are energy band diagrams for a MIIM device of the present invention, showing an unbiased and a biased state, respectively.
- FIGURE 2a is an energy band diagram for the MUM device of Figures Ia and Ib, shown here to illustrate further details with respect to the biased state.
- FIGURE 2b is a plot of charge against lateral distance for the biased device of Figure 2a.
- FIGURE 2c is a plot of electric field strength against lateral distance for the biased device of Figure 2a.
- FIGURE 3 includes a plot of capacitance against bias voltage for an exemplary MUM varactor device that is produced in accordance with the present invention, including an inset plot of an energy band diagram of this exemplary MUM.
- FIGURES 4a and 4b are energy band diagrams for a MUM device of the present invention, showing an unbiased and a biased state, respectively, wherein the device is configured for use without ' a need for a zero bias voltage.
- FIGURES 5a and 5b are energy band diagrams for a first alternative MlM device of the present invention, showing an unbiased and a biased state, respectively.
- FIGURES 6a and 6b are energy band diagrams for a second alternative M]HM device of the present invention, showing an unbiased and a biased state, respectively.
- FIGURE 7 is a schematic diagram of a small signal model derived from the MIIM device structure.
- the varactor is configured with first and second conducting layers, spaced apart from one another such that a given voltage can be applied across the first and second conducting layers.
- an insulator arrangement includes at least one insulator layer disposed between the first and second conducting layers, configured to cooperate with the first and second conducting layers to produce a charge pool therein which changes responsive to changes in the given voltage such that a device capacitance value between the first and second conducting layers changes responsive to the given voltage.
- the insulator arrangement includes at least two distinct layers. [0017] In another feature, the insulator arrangement includes a single layer of material. [0018] In a related feature, at least one of the layers of the insulator is an amorphous material.
- a MUM device can be configured to set a threshold bias voltage, at least approximately, to zero volts so as to provide for use of the varactor without a need for a bias voltage.
- varactor a variable capacitor in which the capacitance of the 2-terminal device varies as a function of voltage across the device.
- the disclosed varactor has several advantages over competing semiconductor- based varactors, including:
- the basic varactor of this disclosure has a structure of metal-insulator- insulator-metal (MUM) of the type originally disclosed by Eliasson and Moddel in U.S. Patent No. 6,534,784 (hereinafter, the 784 patent) which is incorporated herein by reference in its entirety and commonly owned with the present application.
- MUM metal-insulator- insulator-metal
- a first metal layer M 1 and a second metal layer M 2 are positioned in a spaced-apart relationship.
- An insulator arrangement 20 is disposed between first and second metal layers Mi and M 2 .
- insulator arrangement 20 includes a first insulator layer Ij and a second insulator layer I 2 .
- first insulator I 1 is configured to have a very high barrier height (»1 eV) and second insulator I 2 to have a low barrier height (nominally ⁇ 0.3 eV),
- second metal (M 2 ) may readily tunnel across I 2 but not across I 1 .
- potential well 30 is formed in I 2 proximate to a boundary 32 between I 1 and I 2 . It is further recognized that this charge pooling causes a change in capacitance that is dependent on an applied voltage, forming a varactor device.
- FIGS. 2a-c to understand the operation of the MIIM varactor and to estimate the capacitance as a function of applied voltage, one may start by solving the electrostatics problem of charge and field distribution that is illustrated.
- Figures 2a-c are plots against distance x, of potential E, charge p, and electric field intensity ⁇ , respectively.
- a MUM structure including aforedescribed Mi, Ii, I 2 , and M 2 , having a first (higher) Ii barrier of thickness d,, electron affinity ⁇ h and dielectric constant S 1 , and a second (lower) I 2 barrier of thickness d 2 , electron affinity ⁇ 2 , and dielectric constant ⁇ 2 .
- These barriers are bounded by metal Mi on the left side with work function ⁇ Mh and metal M 2 on the right side with work function ⁇ m-
- the barrier heights shown in Figure 2, which are all taken as positive numbers, are given by
- flE is the Fermi distribution of electrons. Note that we have used the energy convention shown in Figure 2a, where the Fermi level of the first metal is taken as zero, and potential energy E increases positively as we move down the vertical axis. Knowing the charge density in barrier I 2 as a function of potential, we can use the Poisson equation, with appropriate boundary conditions, to solve for a potential distribution, V ⁇ x), a charge density in the barrier I 2 , Q c , and the charge densities at the two metal interfaces, Q 1 and Q 2 . It is noted that Figure 2b plots charge density as a function of x, in order to illustrate these various charge density values. From the bias voltage dependence of the anode Mi charge, Qj(Vb), we may then calculate capacitance as dQildV b .
- V V + hV' +—V"
- h is the finite element width (dx) and the ⁇ is determined by the slope of V(x). If V ⁇ x)>Q, the sign is negative, otherwise the sign is positive.
- Figure 3 includes a coordinate system, generally indicated by the reference number 40, showing capacitance plotted against voltage for a given MUM device.
- Plots are provided for four different temperatures: 150° K, 200° K, 250° K and 300° K, indicated by the reference numbers 45, 46, 47 and 48, respectively.
- Va x is approximately 0.25 V. In some practical applications, it may be advantageous to have Va 1 -O so that the maximum change in capacitance occurs at zero bias and no bias supply is required, as will be described in further detail immediately hereinafter.
- Figures 4a and 4b are energy band diagrams that are generally indicated by the reference numbers 50 and 60, respectively, for a highly advantageous "zero- bias" MUM device wherein V th is moved to zero volts such that no bias supply voltage is needed in order to operate the varactor.
- Ih order to accomplish this, ⁇ 2 is set to equal zero by choosing ⁇ MT ⁇ X I - That is, the work function OfM 2 is equal to the electron affinity ⁇ 2 of I 2 .
- First and second metal layers are indicated as M 1 and M 2 , respectively, while an insulator is indicated as I.
- a negative barrier height is formed by selecting electron affinity ⁇ of insulator I and metal M 2 , having work function ⁇ such that ⁇ > ⁇ M2 (18)
- a negative barrier height is produced at a boundary 64 between insulator I and metal M 2 .
- the negative barrier between insulator I and metal M 2 forms a charge well 66 whose width is modulated by the applied voltage, as can be seen by comparing Figures 5a and 5b, resulting in a change in capacitance responsive to the applied voltage.
- First and second metal layers are indicated as M 1 and M 2 , respectively, while an insulator layer arrangement is indicated as 74, including a first insulator layer I 1 . a second insulator layer I 2 and a third insulator layer I 3 .
- the device is configured to produce a charge well 76, in I 2 , proximate to a boundary 78 between I 1 and I 2 .
- a varactor is configured with first and second conducting layers, spaced apart from one another such that a given voltage can be applied across the first and second conducting layers.
- an insulator arrangement includes at least one insulator layer disposed between the first and second conducting layers, configured to cooperate with the first and second conducting layers to produce a charge pool which changes responsive to changes in the given voltage such that a device capacitance value between the first and second conducting layers changes responsive to the given voltage.
- the insulator arrangement can include one layer, two distinct layers or more than two distinct layers. One or more of the layers can be an amorphous material.
- a zero- bias voltage version of the varactor is also described.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US58649304P | 2004-07-08 | 2004-07-08 | |
US11/113,587 US7173275B2 (en) | 2001-05-21 | 2005-04-25 | Thin-film transistors based on tunneling structures and applications |
PCT/US2005/024207 WO2006014574A2 (en) | 2004-07-08 | 2005-07-07 | Metal-insulator varactor devices |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1779440A2 EP1779440A2 (en) | 2007-05-02 |
EP1779440A4 true EP1779440A4 (en) | 2009-04-15 |
Family
ID=35787663
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP05769417A Withdrawn EP1779440A4 (en) | 2004-07-08 | 2005-07-07 | Metal-insulator varactor devices |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1779440A4 (en) |
JP (1) | JP2008506265A (en) |
KR (1) | KR20070083457A (en) |
WO (1) | WO2006014574A2 (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3613011A (en) * | 1969-01-08 | 1971-10-12 | Gen Motors Corp | Varactor tone control apparatus |
US5019530A (en) * | 1990-04-20 | 1991-05-28 | International Business Machines Corporation | Method of making metal-insulator-metal junction structures with adjustable barrier heights |
US5895934A (en) * | 1997-08-13 | 1999-04-20 | The United States Of America As Represented By The Secretary Of The Army | Negative differential resistance device based on tunneling through microclusters, and method therefor |
US20020171078A1 (en) * | 2001-05-21 | 2002-11-21 | Eliasson Blake J. | Metal-oxide electron tunneling device for solar energy conversion |
US20040100817A1 (en) * | 2002-11-26 | 2004-05-27 | Subramanian Chitra K. | Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4510516A (en) * | 1982-02-01 | 1985-04-09 | Bartelink Dirk J | Three-electrode MOS electron device |
-
2005
- 2005-07-07 EP EP05769417A patent/EP1779440A4/en not_active Withdrawn
- 2005-07-07 WO PCT/US2005/024207 patent/WO2006014574A2/en active Search and Examination
- 2005-07-07 KR KR1020077000863A patent/KR20070083457A/en not_active Application Discontinuation
- 2005-07-08 JP JP2007520523A patent/JP2008506265A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3613011A (en) * | 1969-01-08 | 1971-10-12 | Gen Motors Corp | Varactor tone control apparatus |
US5019530A (en) * | 1990-04-20 | 1991-05-28 | International Business Machines Corporation | Method of making metal-insulator-metal junction structures with adjustable barrier heights |
US5895934A (en) * | 1997-08-13 | 1999-04-20 | The United States Of America As Represented By The Secretary Of The Army | Negative differential resistance device based on tunneling through microclusters, and method therefor |
US20020171078A1 (en) * | 2001-05-21 | 2002-11-21 | Eliasson Blake J. | Metal-oxide electron tunneling device for solar energy conversion |
US20040100817A1 (en) * | 2002-11-26 | 2004-05-27 | Subramanian Chitra K. | Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics |
Also Published As
Publication number | Publication date |
---|---|
EP1779440A2 (en) | 2007-05-02 |
KR20070083457A (en) | 2007-08-24 |
WO2006014574A9 (en) | 2006-03-30 |
WO2006014574A2 (en) | 2006-02-09 |
WO2006014574A8 (en) | 2007-04-05 |
JP2008506265A (en) | 2008-02-28 |
WO2006014574A3 (en) | 2007-01-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7388276B2 (en) | Metal-insulator varactor devices | |
Despotuli et al. | Nanoionics of advanced superionic conductors | |
Golubev et al. | Understanding the impact of C60 at the interface of perovskite solar cells via drift-diffusion modeling | |
Xu | Diode and transistor behaviors of three-terminal ballistic junctions | |
TW201721856A (en) | Multiple impedance correlated electron switch fabric | |
Khusayfan et al. | Design and electrical performance of CdS/Sb2Te3 tunneling heterojunction devices | |
US20120061637A1 (en) | 3-d structured nonvolatile memory array and method for fabricating the same | |
CN108493255B (en) | Two-dimensional material schottky diode with controllable electric field | |
CN104798152A (en) | Energy storage devices formed with porous silicon | |
CN103219944A (en) | Frequency multiplier based on lower dimension semiconductor structure | |
Liu et al. | Ultrafast flash memory with large self-rectifying ratio based on atomically thin MoS2-channel transistor | |
Fink et al. | Ion track-based nanoelectronics | |
CN105932049B (en) | Nanometer diode device and preparation method thereof | |
EP1779440A2 (en) | Metal-insulator varactor devices | |
Jung et al. | The effect of the trap density and depth on the current bistability in organic bistable devices | |
Zhao et al. | Equivalent circuit parameters of resonant tunneling diodes extracted from self-consistent Wigner-Poisson simulation | |
Tripathi et al. | Effect of CuPc layer insertion on the memory performance of CdS nanocomposite diodes | |
CN114613841A (en) | High-current three-dimensional nano air channel electron tube and electronic device | |
Zakaria et al. | Improved rectification performance and terahertz detection in hybrid structure of self-switching device (SSD) and planar barrier diode (PBD) using two-dimensional device simulation | |
Pernas et al. | Self-consistent calculation of the intrinsic bistability in double-barrier heterostructures | |
Su et al. | Investigation of surface pin diodes for a novel reconfigurable antenna | |
Heo | Metal-Insulator-Metal tunnel diode with various materials and structural designs for rectifying effect | |
CN202905724U (en) | Fast recovery diode | |
Yoshida et al. | Potential application of p–i–n semiconductor capacitor with non-linear voltage–charge characteristic for secondary battery | |
Chang et al. | Physical Modeling of Resonant Tunneling in Ferroelectric Tunnel Junctions With Multiple Quantum Well Superlattice Heterostructures |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20070205 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR |
|
AX | Request for extension of the european patent |
Extension state: AL BA HR MK YU |
|
R17D | Deferred search report published (corrected) |
Effective date: 20070405 |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: THE REGENTS OF THE UNIVERSITY OF COLORADO |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: ESTES, MICHAEL, J. |
|
DAX | Request for extension of the european patent (deleted) | ||
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01L 29/88 20060101ALI20090204BHEP Ipc: H01L 29/93 20060101ALI20090204BHEP Ipc: H01L 21/02 20060101ALI20090204BHEP Ipc: H01L 27/08 20060101AFI20090204BHEP |
|
A4 | Supplementary search report drawn up and despatched |
Effective date: 20090313 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20090203 |