EP1776637A2 - Procedes pour retarder les acces a des donnees et/ou a des commandes d'un systeme a deux ordinateurs et unite de temporisation correspondante - Google Patents

Procedes pour retarder les acces a des donnees et/ou a des commandes d'un systeme a deux ordinateurs et unite de temporisation correspondante

Info

Publication number
EP1776637A2
EP1776637A2 EP05764000A EP05764000A EP1776637A2 EP 1776637 A2 EP1776637 A2 EP 1776637A2 EP 05764000 A EP05764000 A EP 05764000A EP 05764000 A EP05764000 A EP 05764000A EP 1776637 A2 EP1776637 A2 EP 1776637A2
Authority
EP
European Patent Office
Prior art keywords
delay unit
data
computer
commands
computer system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05764000A
Other languages
German (de)
English (en)
Inventor
Bernd Mueller
Werner Harter
Thomas Kottke
Andreas Steininger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP1776637A2 publication Critical patent/EP1776637A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1679—Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1695—Error detection or correction of the data by redundancy in hardware which are operating with time diversity
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845—Systems in which the redundancy can be transformed in increased performance

Definitions

  • the invention is based on a method for delaying the access to data and / or commands of a dual-computer system and a corresponding delay unit according to the features of the independent claims known from the prior art.
  • dual-computer systems or dual-processor systems are today's computer systems for safety-critical applications, in particular in vehicles such as for anti-lock braking systems, electronic stability program (ESP), X-by-wire systems such as drive-by-wire or steer-by-wire as well as break-by-wire, etc. or other networked systems.
  • ESP electronic stability program
  • X-by-wire systems such as drive-by-wire or steer-by-wire as well as break-by-wire, etc. or other networked systems.
  • powerful error mechanisms and error handling mechanisms are required, in particular to counteract transient errors that arise, for example, in miniaturization of the semiconductor structures of the computer systems.
  • Component such as a memory or other input / output elements, passed before it is ensured that the data and / or commands are correct. This can then lead to accesses, ie write operations and / or read operations, being performed on erroneous data and / or commands, in particular in the case of errors in memory accesses. This issue can lead to errors in restoring a particular system state, turning off the consequences of an error, generating correct data after a crash, restoring a system to breakdown, or returning to its original state circuitry (referred to as recovery hereafter) arise or this be possible only at very high cost.
  • Such errors when accessed by at least one computer of the dual-computer system, in the form of write operations and / or read operations, may result in errors in the entire system and devices connected thereto, all the more serious that it is not possible to determine which data and / or instructions were changed incorrectly.
  • the invention is based on a method and a delay unit for delaying accesses to data and / or commands of a computer system
  • the delay unit is adapted to compensate for the duration between the instantaneous access to data and / or commands and the error detection.
  • the invention is further based on a method for delaying access as write operations and / or read operations on data and / or commands of a dual-computer system with a first and second computer, wherein the first and second computer are operated with a, in particular predeterminable, time offset and this Time offset is compensated in the two-computer system in the accesses to data and / or commands in at least one of the two computers, including a delay unit according to the invention is designed accordingly, is used.
  • a delay unit and a method are proposed in which an error is detected by comparing the data and / or commands of the first computer with the data and / or commands of the second computer, wherein the delay unit is configured or a delay is such that the accesses, ie the write operations and / or read operations, are delayed with respect to the data and / or instructions of the two-processor system, in particular in the case of a computer, until the error detection is performed, whereby it is possible to prevent erroneous data and / or commands from accessing, ie undergo a write operation and / or a read operation.
  • the two computers of the dual-computer system or the dual-computer system itself is connected via a data bus with at least one first component, wherein the
  • Delay unit between at least one computer of the dual-computer system and the at least one first component is located on the data bus.
  • the dual-computer system or the two computers can be connected via a command bus with at least one second component, in which case advantageously the delay unit between at least one computer of the dual-computer system and the at least one second component is connected to the command bus or is located there.
  • the method is advantageously designed such that the delay unit is designed in such a way that only write operations and read operations, or only write operations and possibly only the read operations are delayed as accesses.
  • the delay unit advantageously includes a delay element, in particular with a predefinable or adjustable delay, as well as a change-over module, in particular as a multiplex component and thereby more convenient
  • the secure multiplexing module is designed such that bit switching elements are provided and a switchover between the delay of the accesses and brinVerzögerung the accesses by a drive signal, in particular a read / write signal or a signal derived therefrom, which in a test unit, in particular a Totally Self
  • TSC Checking
  • the delay unit may advantageously be designed such that it itself, in particular by the test unit, has a fault-detecting effect, that is to say is implemented in error-detecting manner and outputs a further usable error signal which can be used in particular for error handling.
  • the delay unit is advantageously designed such that change signals are provided by which a write operation is changed to a read operation, such that a erroneous writing of data and / or commands is avoided.
  • Such a delay unit according to the invention can thus be used equally for synchronous, ie in particular clock-synchronous, non-clock synchronous, ie non-synchronous two-processor systems or for dual-computer systems, as well as for other computers with error detection mechanisms in which the error only occurs during the output the data or after the date of the date can be detected and thereby not in time with the output of the data, the error signal is available in time for error prevention.
  • the aforementioned errors in the accesses to the data and / or commands are to be avoided, in particular it can be ensured that the data and / or commands relating to a memory access can not be destroyed by errors in the two-processor or dual-computer system.
  • the difficulties mentioned in the recovery of the dual-computer system can be avoided.
  • FIG. 1 shows a dual-processor system or two-processor system with a delay unit according to the invention.
  • FIG. 2 shows a first embodiment of a delay unit according to the invention.
  • FIG. 3 shows a second embodiment of a delay unit according to the invention.
  • FIG. 4 shows a multiplex component, in particular a secure multiplexer, of a delay unit according to the invention.
  • FIG. 1 shows a dual-computer system with a first computer 100, in particular a master computer and a second computer 101, in particular a slave computer.
  • the entire system is operated with a predeterminable clock or in predeterminable clock cycles (clock cycle) CLK.
  • CLK clock cycle
  • a dual-computer system contains, by way of example, a special feature for error detection, in which the first computer 100 and the second computer 101 work with a time offset, in particular a predefinable time offset or a specifiable clock offset.
  • a time offset in particular a predefinable time offset or a specifiable clock offset.
  • any time for a time offset can be predetermined and any clock with respect to an offset of
  • Clock cycles This may be an integer offset of the clock cycle, but just as shown in this example, for example, an offset of 1.5 clock cycles, in which case the first computer 100 just works 1.5 clock cycles before the second computer 101 respectively operated becomes.
  • This offset can be used to avoid common mode failures, the computers or
  • components 103 and 104 are provided which are connected via buses 116, consisting of the bus lines 116A and 116B and 116C and 117, consisting of the bus lines 117A and 117B to the two computers 100 and 101 , 117 is a command bus in which 117A is a command address bus and 117B is the partial command (data) bus.
  • Address bus 117A is connected to computer 100 via a command address connection IA1 (instruction address 1) and to computer 101 via an instruction address connection IA2 (instruction address 2).
  • the instructions themselves are transmitted via the sub-command bus 117B, which is connected to computer 100 via a command terminal II (Instruction 1) and to computer 101 via a command terminal 12 (Instruction 2).
  • this command bus 117 consisting of 117A and 117B is a component 103 z.
  • B. an instruction memory, in particular a secure instruction memory or the like interposed. This component, in particular as a command memory is operated in this example with the clock CLK.
  • a data bus is shown which includes a data address bus or a data address line 116A and a data bus or a data line 116B.
  • 116A that is to say the data address line
  • DA1 data address 1
  • DA2 data address 2
  • DA1 data address 1
  • DA2 data address 2
  • Data terminal DOl Data Out 1
  • DO2 Data Out 2
  • the data bus line 116C which is connected to computer 100 or computer 101 via a data connection Dil (Data In 1) and a data connection DI2 (Data In 2), respectively is.
  • a component 104 is interposed, for example a data memory, in particular a secure data memory o. ⁇ . This component 104 is also supplied with the clock CLK in this example.
  • the components 103 and 104 are representative of any components which are connected via a data bus and / or command bus to the computers of the dual-computer system and corresponding to the accesses via data and / or commands of the dual-processor system with respect to write operations and / or read operations erroneous data and / or commands receive or give away.
  • error prevention are indeed
  • Error detection generators 105, 106 and 107 are provided which generate an error detection such as a parity bit or other error code such as an error correction code, so ECC, o. ⁇ .. are also provided the corresponding Starbuckskennungsprüf healthyen or check Means 108 and 109 for checking the respective misrecognition, for example, the
  • Parity bit or other error code such as ECC.
  • Clock offset a computer here in particular computer 100 erroneous data and / or commands in components, in particular external components such. B. here in particular the memory 103 or 104, but also with respect to other participants or actuators or sensors write or read. Thus, it may also erroneously perform a write access instead of a designated read access by this clock offset.
  • these scenarios lead to errors in the entire system, in particular without clear display possibility which data and / or commands have just been changed incorrectly, which also causes the recovery problem.
  • a delay unit 102 is now connected as shown in the lines of the data bus and / or in the command bus. For reasons of clarity, only the activation in the data bus is shown.
  • This delay unit 102 or the delay unit delays the accesses, here in particular the memory accesses, in such a way that a possible time or clock offset is compensated, in particular for an error detection, for example via the comparators 110 and 111, for example at least until the error signal is generated in the dual-computer system. So the error detection is performed in the dual-computer system.
  • Different variants can be implemented:
  • Delay the write and read operations delay only the write operations, or, although not preferred, delay the read operations. It can be converted by a change signal, in particular the error signal, a delayed write operation in a read operation to prevent erroneous writing.
  • the purpose of the delay unit ie the delay unit 102, is to delay accesses within the said time offset or clock cycle offset in order to compensate for this, in particular to write operations of the delay unit
  • Calculator 100 to a component in particular external component to verify and thus correctness of the corresponding data and / or commands or the respective addresses to achieve.
  • the delay unit can also be implemented in such a way that it recognizes errors in itself and signals this by an error signal EO to the outside, this will be explained in more detail with reference to Figures 2 and 3.
  • FIG. 2 now shows a delay unit with two switching modules 201 and 200, in particular multiplex modules, a delay element 204 and a test device or test device 203, in particular a TSC checker.
  • the delay unit consists of two branches, a reading branch which corresponds to the lower input path of the multiplexer 200 (the lower three arrows) including multiplexer 201, and a write branch, ie the upper input path of multiplexer 200 (the upper three arrows). Ie. the delay unit exists, especially if it should only delay write operations from two paths between which by a switching device, in particular a multiplexer 200, can be switched.
  • the data and / or commands go here the data from DOl (Data Out 1), the corresponding addresses, here DAl (Data Address 1) and here in particular additional memory control signals MC (Memory Control) without delay, in the other branch delayed by the delay element 204.
  • a delay of two clock cycles occurs at a predetermined delay of 1.5 clock cycles as previously described and is thus longer than the required minimum of 1.5 clock cycles, thereby allowing a memory to be used same clock input CLK to be served. That the delay is at least as long as the intended time offset (here 1.5 clock cycles), but may be larger, as in this example.
  • the associated address and control signals are equally delayed. As already stated, this is just as possible for the data bus (as exemplified for the data bus with DA1 and DO1) as well as conceivable for the command bus. The representation would thus be easily transferable to a command bus for IAI.
  • bit numbers at the individual connections in Figures 2 and 3 are exemplified, i.
  • 64-bit plus parity bit or wider error detections is easily possible and conceivable according to the invention.
  • the choice of 4 bits for the memory control signal MC is exemplary.
  • number 5 bit is to be regarded as exemplary by the additionally injected R / W invert bit on 5 bit (4 bit + IR / W invert ⁇ 5 bit).
  • the delay is bypassed by switching means 200, thus bypassed, controlled by a switching signal (in particular by using the read / write signal R / W or the derived Invert R / W).
  • the second switching module 200 in particular the second multiplexer, which combines the data and / or commands (in this case the data, for example) again, is likewise triggered by this signal, in particular the read / write signal R / W and the signal inverted thereto.
  • the signal from the delayed path that is to say behind the delay element 204, is advantageous here, as described below.
  • a gap of the duration of the write operation occurs at the output of the switching block 200.
  • the switch block 200 ie the multiplexer, would activate the read branch, ie the three lower inputs of multiplexer 200, the non-delayed data or addresses and control information of this branch still belonging to the write operation.
  • the previous operation get on the bus switching device 201 is provided, which in this case uncritical constants z. 2, to the lower input of the multiplexer 200 while this waiting time exists until, under some circumstances, multiplexer 200 switches to the three upper input paths, ie the delayed one, and executes the current write operation.
  • the signals data address DAl (data address), data output DOl (data out) and control signal (memory control) MC are each a simple one in this example Parity bit secured. This parity is protected by the check units 109 and 108 for the command bus, wherein, as not shown in Figure 1, the memory control signal MC is secured by an additional memory checker 202. The parity bit of this signal MC is equally delayed by the delay element 204 as are the other signals. Since the signals of each signal type DAl, DOl and MC are independent in the
  • Delay unit are performed, this simple parity bit sufficient protection against single error. With multi-error detection or protection as well as correction of multiple errors, as already mentioned, more powerful error detections can be used.
  • An additional function can be realized via the path DAE / DOE, 206, 207 and 208.
  • a protection of write operations in the event of a failure in standard components such as a fail-safe memory or just as in the switching of a write operation in a read operation can be achieved.
  • the DAE / DOE dual core is available as dual rail code. This is converted into a single-rail signal before a time offset between them. This takes place in a comparison block 206 which can be embodied, in particular, as an XOR block. At the same time, the XOR gate 206 makes a single signal from the multiple signal.
  • a time delay of 0.5 clock cycles is now added in a delay element 207 in order to achieve a time alignment of the resulting error signal with the corresponding data word in the delay unit. This is because the delay unit in our example delays by 2 clock cycles according to delay 204. Is then as block 208 z. B. an AND gate used, the read / write signal R / W can be masked to block a write access as shown in connection with the wiring of block 208.
  • the error signal from the computers can also like the parity bit of the memory controller MC from 202 and the respective switching or Change signal of the switching devices 201 and 202, so in particular the read / write signal R / W and the derived inverse write / read signal (Invert R / W) the test module 203 (in particular designed as a TSC checker) are fed, resulting in a further error handling usable error signal EO (Error Out) results.
  • EO Error Out
  • an either non-delayed or delayed data signal or data output signal DOId data out delayed depending on a read operation or write operation and in this particular example if a memory device is used as component, especially external component, a memory control signal or memory control signal MCd (Memory Control delayed ) which is either not delayed or delayed.
  • FIG. 3 once again shows a delay unit in a second embodiment, where the delay unit can also be designed as shown only from one switching module or multiplexer 200 and two branches.
  • the second multiplexer 200 is used from Figure 2 so that the inputs DAl, DOl and MC are fed directly to this.
  • the same inputs are delayed as before via a delay element 204 and also supplied to the multiplexer 200.
  • the data in this case data address DA1, data DO1 and memory controller MC
  • write operations in the non-delayed path are converted into read operations.
  • This change or switching of the write operations in read operations can also be performed inverted by the read / write signals R / W or the R / W derived therefrom.
  • the second embodiment is constructed similar to the first
  • Embodiment except for the fact that the first multiplexer 201 has been omitted, whereby also the designations and the functions, if present, are identical.
  • the exception is the test unit, since these are supplied by the missing multiplexer 201 fewer signals and therefore may be slightly differently structured and therefore here is designated 303.
  • the reusable error signal EO which can be used in the context of error handling, likewise outputs.
  • safe multiplexers according to FIG. 4 can be used as switching modules or multiplexers.
  • the data is by a
  • Error detection code here, for example, a parity bit hedged and the control signals so switching or change signals, in particular the
  • Read / write signal R / W and the inverse read / write signal RIW derived from it are also protected, here by way of example in dual rail logic. That the R / W and the inverse signal are first supplied to the secure multiplexer and from there to
  • Test unit to the TSC checker 203 or 303.
  • an error affecting a track of the write / read signal is detected by the test unit TSC 203 or 303 while a single error in the multiplex circuit will affect a simple output bit and thus by the parity Check can be determined. That the data and / or commands as previously executed are switched as in a standard multiplexer, wherein in addition the parity bit or another error identifier are switched.
  • the control signals ie changeover or change signals R / W and R / W Invert, are first fed to all switches for the individual bits, here represented in the blocks 401 to 406, in particular as AND gates, to which the respective inputs 110, Il 1, 120, 121 are fed to InO, InI.
  • Output signals from 401-406 are then combined in blocks 407-409, respectively, as shown in FIG.
  • the blocks 407-409 are designed in particular as OR gates. This then results in outputs of the multiplex block Ol, 02 to On.
  • the structure shown in FIG. 4 is only a section of the overall structure of a multiplex module according to FIGS. 2 and 3 with the bit widths of 17 bits or 5 bits per signal path illustrated by way of example therein.
  • both multiplex modules 201 and 200 corresponding to FIGS. 2 and 3 are advantageously designed in the form of FIG. 4 in order to make it possible to identify a data path which has been incorrectly switched over as already described, and To simplify error detection. Such errors could not be determined by pure parity checking, since also the data of the wrong signal path have the correct parity, if there is no bit dump.
  • This security package is concluded by securing the interface to a component, in particular an external component corresponding to 103 and 104 from FIG. 1, by error detection units for generation of the error identification 105-107 and error checking units for checking the error detection such as 108 and 104 as already illustrated in FIG 109 are provided, in particular, as party bit checkers and party bit generators.
  • error detection units for generation of the error identification 105-107
  • error checking units for checking the error detection such as 108 and 104 as already illustrated in FIG 109 are provided, in particular, as party bit checkers and party bit generators.
  • the resulting error signals can then just as DAE / DOE signals according to Figure 2 and Figure 3 just as Data Address Error or Data Out Error in the delay module as described are used.
  • Switching or change signals R / W and R / W Invert are first passed to all switches for the individual bits and only then checked in the TSC Checker, errors in the control signals can thus be detected by the test of these or if only one bit is switched incorrectly, this is detected by the data encoding of the data to be switched.
  • the invention thus provides a considerable increase in security in the context of a dual-computer system with relatively simple means.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)

Abstract

L'invention concerne une unité de temporisation (102) et des procédés servant à retarder les accès à des données et/ou à des commandes d'un système à deux ordinateurs comprenant un premier (100) et un deuxième ordinateur (101). Le premier et le deuxième ordinateur fonctionnent avec un décalage dans le temps et l'unité de temporisation est conçue de manière à compenser, au niveau d'au moins un des deux ordinateurs, ce décalage temporel dans le système à deux ordinateurs pour les accès à des données et/ou à des commandes. L'invention concerne également des procédés et une unité de temporisation servant à retarder les accès à des données et/ou à des commandes d'un système informatique muni de mécanismes de découverte d'erreurs servant à détecter des erreurs. Ces procédés et cette unité de temporisation sont caractérisés en ce que la durée entre un accès non temporisé à des données et/ou à des commandes, d'une part, et la détection d'erreurs, d'autre part, est compensée.
EP05764000A 2004-08-06 2005-08-03 Procedes pour retarder les acces a des donnees et/ou a des commandes d'un systeme a deux ordinateurs et unite de temporisation correspondante Withdrawn EP1776637A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004038590A DE102004038590A1 (de) 2004-08-06 2004-08-06 Verfahren zur Verzögerung von Zugriffen auf Daten und/oder Befehle eines Zweirechnersystems sowie entsprechende Verzögerungseinheit
PCT/EP2005/053791 WO2006015964A2 (fr) 2004-08-06 2005-08-03 Procedes pour retarder les acces a des donnees et/ou a des commandes d'un systeme a deux ordinateurs et unite de temporisation correspondante

Publications (1)

Publication Number Publication Date
EP1776637A2 true EP1776637A2 (fr) 2007-04-25

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EP05764000A Withdrawn EP1776637A2 (fr) 2004-08-06 2005-08-03 Procedes pour retarder les acces a des donnees et/ou a des commandes d'un systeme a deux ordinateurs et unite de temporisation correspondante

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Country Link
US (1) US20070283061A1 (fr)
EP (1) EP1776637A2 (fr)
JP (1) JP2008509466A (fr)
KR (1) KR20070038543A (fr)
CN (1) CN1993680A (fr)
DE (1) DE102004038590A1 (fr)
WO (1) WO2006015964A2 (fr)

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WO2006015964A2 (fr) 2006-02-16
US20070283061A1 (en) 2007-12-06
KR20070038543A (ko) 2007-04-10
CN1993680A (zh) 2007-07-04
DE102004038590A1 (de) 2006-03-16
WO2006015964A3 (fr) 2006-05-11
JP2008509466A (ja) 2008-03-27

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