EP1774576A1 - Integrated circuit comprising a capacitor with metal electrodes, and method of producing one such capacitor - Google Patents

Integrated circuit comprising a capacitor with metal electrodes, and method of producing one such capacitor

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Publication number
EP1774576A1
EP1774576A1 EP05775544A EP05775544A EP1774576A1 EP 1774576 A1 EP1774576 A1 EP 1774576A1 EP 05775544 A EP05775544 A EP 05775544A EP 05775544 A EP05775544 A EP 05775544A EP 1774576 A1 EP1774576 A1 EP 1774576A1
Authority
EP
European Patent Office
Prior art keywords
capacitor
electrode
integrated circuit
metal
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05775544A
Other languages
German (de)
French (fr)
Inventor
Aomar Halimaoui
Rebha El Farhane
Benoît FROMENT
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
NXP BV
Original Assignee
STMicroelectronics Crolles 2 SAS
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Crolles 2 SAS, Koninklijke Philips Electronics NV filed Critical STMicroelectronics Crolles 2 SAS
Publication of EP1774576A1 publication Critical patent/EP1774576A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions

Definitions

  • the present invention relates to integrated circuits, more particularly to metal-electrode capacitors. Capacitors are especially used in memory array memory cells.
  • the manufacture of capacitors increasingly comes up against problems related to high densities of integration. Indeed, the increase of the integration density imposes the reduction of the surface of a memory cell, while maintaining an effective capacitance value. Thus, in current technologies, several approaches are possible. The most common is the formation of the capacitor in a trench to increase the surface of the capacitor without increasing the surface of the memory cell. The surface can be further increased by a factor of about 2. using as a lower electrode the hemispherical grain type doped polysilicon (HSG polysilicon).
  • HSG polysilicon hemispherical grain type doped polysilicon
  • An object of the present invention is to obtain capacitors of size adapted to integrated circuits of smaller and smaller size without reducing the value of their capacity.
  • the present invention also aims to use metal electrodes to overcome the problems of doping and depletion capacity related to three-dimensional polysilicon electrodes, while keeping the morphology of a deposit of the hemispherical grain type.
  • Capacitors according to the present invention also offer the advantage of having an efficient capacitance without increasing the leakage current of the dielectric.
  • the present invention is therefore based on the silicidation (formation of a metal silicide) of a polysilicon electrode HSG, for example.
  • the present invention thus proposes an integrated circuit comprising at least one metal electrode capacitor of which at least one of the two electrodes of the capacitor is formed of silicon or a silicon alloy of hemispherical grain type silicide at least on the surface.
  • This electrode can thus be either partially silicided, or preferably entirely silicided, that is to say entirely formed of a metal silicide.
  • the second metal electrode of the capacitor is also formed of a silicon layer or a silicon alloy of hemispherical grain type partially or wholly silicided.
  • the second electrode of the capacitor may comprise a metal layer, for example TiN.
  • the capacitor may have a planar or trench structure.
  • the present invention also proposes a method for manufacturing a capacitor within an integrated circuit as defined above in which the elaboration of the first electrode comprises the production of a layer of silicon or an alloy of hemispherical grain-type silicon and siliciding of said layer at least on the surface.
  • This method makes it possible to obtain a capacitor in which said first electrode can be either partially silicided or preferably entirely silicided.
  • the second electrode is produced either analogously to the first electrode, that is to say by depositing polysilicon of the hemispherical grain type then siliciding, or by metal deposition, for example TiN .
  • FIG. 1 schematically represents an integrated circuit according to a first embodiment of the present invention
  • Figures 2 to 4 schematically illustrate the main steps of a method for obtaining the integrated circuit of Figure 1
  • Figure 5 schematically show an integrated circuit according to a second embodiment of the present invention.
  • FIG. 1 shows an integrated circuit IC according to the invention comprising a capacitor Cr. comprising two metal silicide electrodes of hemispherical grain type.
  • the integrated circuit CI comprises a substrate SB, in which a hollow trench has been made comprising a first hemispherical grain type silicided metal electrode 10 surmounted by a dielectric 2, surmounted by a second metal silicide electrode of hemispherical grain type. 30.
  • the reference SB designates a semiconductor substrate, for example made of silicon.
  • a trench 4 is produced in the substrate SB in a conventional manner and known per se.
  • the first electrode 10 is then produced.
  • a layer 1 of silicon, germanium or a silicon alloy, such as, for example, silicon-germanium, of the hemispherical grain type is formed, also in a conventional manner and known per se, for example by deposition.
  • Figure 3 The characteristics of such a repository are for example described in "Manufacturing and Performance of Selective HSG Storage Cells for 256 Mb and 1 Gb DRAM Applications, A. Banerjee, RL Wise, DL Plunton, M. Bevan, ML Crenshaw, S.Aoyama. and MM Mansoori, IEEE Transactions on Electron Devices, Vol. 47, No.3, March 2000 ".
  • the layer 1 of silicon or of a hemispherical grain type silicon alloy has a thickness of 1000 to 1500 A.
  • siliciding that is the formation of a metal silicide, is obtained from cobalt.
  • this siliciding can be obtained from other metals such as, for example, tungsten, titanium or nickel.
  • a layer of nickel on the layer 1 of silicon or of a hemispherical grain type silicon alloy is deposited, for example by a plasma vapor deposition (PVD deposition).
  • PVD deposition plasma vapor deposition
  • the thickness of the nickel layer is determined as a function of the phase and the thickness of metal silicide which it is finally desired to obtain, knowing that when nickel is used, 1 N of nickel gives 2.2 A of silicide.
  • a first initial annealing is carried out, typically at a temperature below 600 ° C., for example at a temperature of 450 ° C. This annealing temperature depends on the nature of the metal used for siliciding.
  • the nickel then reacts with the silicon of layer 1 to form NiSi (FIG. 4). Excess unreacted nickel can then be selectively removed from the silicide. This selective removal operation is carried out for example by wet etching.
  • Such wet etching is conventional and known per se, and it uses, for example, a H 2 SO 4 : H 2 O 2 : H 2 O chemistry, or a HCl: H 2 O 2 : H 2 O chemistry. therefore in the presence of a silicided metal electrode with a hemispherical grain type morphology on which the dielectric 2 is deposited.
  • the dielectric may be a conventional dielectric with a relative dielectric constant k of, for example, 5.
  • k a relative dielectric constant
  • the main improvement over the prior art comes from the improvement of the depletion capacities, the strong reduction of the series resistance and the simplification of the process insofar as it is not necessary to dope by implementation the electrodes silicon or silicon alloy, sometimes difficult operation especially on the sides of the trenches.
  • the dielectric 2 is surmounted by the second electrode.
  • the electrode 30 can be made analogously to the first electrode 10, that is to say by deposition of HSG polysilicon, then siliciding, preferably total, and removal of the metal having not reacted.
  • the second electrode can also be made for example by direct deposition of metal (for example TiN) on the dielectric.
  • the capacitor comprises a first hemispherical grain silicided metal electrode 10, surmounted by a dielectric 2, surmounted by a second metal electrode 31.
  • the capacitors are not limited to trench structures, as described above, but can also be for example planar type.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention relates to an integrated circuit (IC) comprising at least one capacitor with metal electrodes, whereby at least one of said electrodes (10 or 30) is made from silicon or a silicon alloy having hemispherical grains and being silicided at least on the surface thereof. The invention also relates to a production method which can be used to obtain one such capacitor with silicided metal electrodes.

Description

CIRCUIT INTEGRE COMPRENANT UN CONDENSATEUR A ELECTRODES METALLIQUES ET PROCEDE DE FABRICATION INTEGRATED CIRCUIT COMPRISING A METAL ELECTRODE CAPACITOR AND METHOD OF MANUFACTURE
D'UN TEL CONDENSATEUROF SUCH CAPACITOR
La présente invention concerne les circuits intégrés, plus particulièrement les condensateurs à -électrodes métalliques. Les condensateurs sont notamment utilisés dans des cellules mémoire de plan mémoire.The present invention relates to integrated circuits, more particularly to metal-electrode capacitors. Capacitors are especially used in memory array memory cells.
La fabrication de condensateurs se heurte de plus en plus aux problèmes liés aux fortes densités d' intégration. En effet, l ' augmentation de la densité d' intégration impose la réduction de la surface d'une cellule mémoire, tout en maintenant une valeur de capacité efficace. Ainsi, dans les technologies actuelles, plusieurs approches sont possibles. La plus courante est la formation du condensateur dans une tranchée permettant d' augmenter la surface du condensateur sans augmenter la surface de la cellule mémoire. La surface peut encore être augmentée d' un facteur 2 environ, . en utilisant comme électrode inférieure du polysilicium dopé de type à grains hémisphériques (polysilicium HSG).The manufacture of capacitors increasingly comes up against problems related to high densities of integration. Indeed, the increase of the integration density imposes the reduction of the surface of a memory cell, while maintaining an effective capacitance value. Thus, in current technologies, several approaches are possible. The most common is the formation of the capacitor in a trench to increase the surface of the capacitor without increasing the surface of the memory cell. The surface can be further increased by a factor of about 2. using as a lower electrode the hemispherical grain type doped polysilicon (HSG polysilicon).
Pour des densités d'intégrations encore plus importantes, il existe plusieurs approches possibles qui permettent d' intégrer des capacités dans des cellules de plus en plus petites.For even greater integration densities, there are several possible approaches that can integrate capabilities into smaller and smaller cells.
L' approche classique consiste à augmenter la profondeur de la tranchée. Cependant, cette approche conduit à des facteurs de forme difficilement gérables. Une autre approche consiste a diminuer l' épaisseur du diélectrique, le risque étant l' augmentation du courant de fuite. De récentes recherches concernent l' utilisation d' un isolant à forte constante diélectrique et des électrodes métalliques permettant de s' affranchir des problèmes de dopage des électrodes en polysilicium tridimensionnelles et de réduire les capacités de déplétion (appauvrissement) liées aux électrodes en polysilicium. Cependant, les électrodes métalliques traditionnelles (par exemple en TiN) sont planes et leur utilisation conduit donc à perdre le facteur 2 apporté par l ' utilisation de polysilicium HSG.The classic approach is to increase the depth of the trench. However, this approach leads to shape factors that are difficult to manage. Another approach is to reduce the thickness of the dielectric, the risk being the increase of the leakage current. Recent research concerns the use of a high dielectric constant insulator and metal electrodes to overcome the doping problems of three - dimensional polysilicon electrodes and to reduce the depletion (depletion) capabilities associated with polysilicon electrodes. However, the traditional metal electrodes (for example TiN) are flat and their use therefore leads to losing the factor 2 provided by the use of HSG polysilicon.
L' invention vise à apporter une solution à ces problèmes. Un but de la présente invention est d' obtenir des condensateurs de taille adaptée à des circuits intégrés de taille de plus en plus réduite sans réduction de la valeur de leur capacité.The aim of the invention is to provide a solution to these problems. An object of the present invention is to obtain capacitors of size adapted to integrated circuits of smaller and smaller size without reducing the value of their capacity.
La présente invention a également pour but d' utiliser des électrodes métalliques permettant de s' affranchir des problèmes de dopage et de capacités de déplétion liés aux électrodes en polysilicium tridimensionnel, tout en gardant la morphologie d' un dépôt de type à grains hémisphériques.The present invention also aims to use metal electrodes to overcome the problems of doping and depletion capacity related to three-dimensional polysilicon electrodes, while keeping the morphology of a deposit of the hemispherical grain type.
Les condensateurs selon la présente invention offrent également l' avantage de présenter une capacité efficace sans augmentation du courant de fuite du diélectrique.Capacitors according to the present invention also offer the advantage of having an efficient capacitance without increasing the leakage current of the dielectric.
La présente invention est donc basée sur la siliciuration (formation d' un siliciure de métal) d' une électrode en polysilicium HSG, par exemple.The present invention is therefore based on the silicidation (formation of a metal silicide) of a polysilicon electrode HSG, for example.
La présente , invention propose donc un circuit intégré comprenant au moins un condensateur à électrodes métalliques dont l ' une au moins des deux électrodes du condensateur est formée de silicium ou d'un alliage de silicium de type à grains hémisphériques siliciure au moins en surface. Cette électrode peut être ainsi soit partiellement siliciurée, soit de préférence entièrement siliciurée, c' est-à-dire entièrement formée d' un siliciure de métal.The present invention thus proposes an integrated circuit comprising at least one metal electrode capacitor of which at least one of the two electrodes of the capacitor is formed of silicon or a silicon alloy of hemispherical grain type silicide at least on the surface. This electrode can thus be either partially silicided, or preferably entirely silicided, that is to say entirely formed of a metal silicide.
Selon un second mode de réalisation de l' invention, la seconde électrode métallique du condensateur est également formée d'une couche de silicium ou d'un alliage de silicium de type à grains hémisphériques partiellement ou entièrement siliciurée.According to a second embodiment of the invention, the second metal electrode of the capacitor is also formed of a silicon layer or a silicon alloy of hemispherical grain type partially or wholly silicided.
En variante, la seconde électrode du condensateur peut comporter une couche de métal, par exemple du TiN. Le condensateur peut présenter une structure planaire ou bien en tranchée.Alternatively, the second electrode of the capacitor may comprise a metal layer, for example TiN. The capacitor may have a planar or trench structure.
La présente invention propose également un procédé de fabrication d' un condensateur au sein d' un circuit intégré tel que défini ci-dessus dans lequel l' élaboration de la première électrode comprend la réalisation d' une couche de silicium ou d' un alliage de silicium de type à grains hémisphériques et la siliciuration de ladite couche au moins en surface.The present invention also proposes a method for manufacturing a capacitor within an integrated circuit as defined above in which the elaboration of the first electrode comprises the production of a layer of silicon or an alloy of hemispherical grain-type silicon and siliciding of said layer at least on the surface.
Ce procédé permet d' obtenir un condensateur dans lequel ladite première électrode peut être soit partiellement siliciurée, soit de préférence entièrement siliciurée.This method makes it possible to obtain a capacitor in which said first electrode can be either partially silicided or preferably entirely silicided.
Selon une variante de l'invention, la seconde électrode est élaborée soit de façon analogue à la première électrode, c' est-à-dire par dépôt de polysilicium de typé à grain hémisphérique puis siliciuration, soit par dépôt de métal, par exemple TiN. D' autres avantages et caractéristiques de l'invention apparaîtront à l' examen de la description détaillée de modes de réalisation et de mise en œuvre, nullement limitatifs, et des dessins annexés, sur lesquels : la figure 1 représentent schématiquement un circuit intégré selon un premier mode de réalisation de la présente invention ; les figures 2 à 4 illustrent schématiquement les principales étapes d' un procédé permettant d' obtenir le circuit intégré de la figure 1 ; et , la figure 5 représentent schématiquement un circuit intégré selon un second mode de réalisation de la présente invention.According to a variant of the invention, the second electrode is produced either analogously to the first electrode, that is to say by depositing polysilicon of the hemispherical grain type then siliciding, or by metal deposition, for example TiN . Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments and implementations, in no way limiting, and the accompanying drawings, in which: FIG. 1 schematically represents an integrated circuit according to a first embodiment of the present invention; Figures 2 to 4 schematically illustrate the main steps of a method for obtaining the integrated circuit of Figure 1; and, Figure 5 schematically show an integrated circuit according to a second embodiment of the present invention.
Sur la figure I , on a représenté un circuit intégré CI selon l' invention comportant -un condensateur Cr? comprenant deux électrodes métalliques siliciurées de type à grains hémisphériques.FIG. 1 shows an integrated circuit IC according to the invention comprising a capacitor Cr. comprising two metal silicide electrodes of hemispherical grain type.
Le circuit intégré CI comporte un substrat SB , dans lequel on a réalisé une tranchée creuse comprenant une première électrode métallique siliciurée de type à grains hémisphériques 10 , surmontée d' un diélectrique 2, surmonté d' une seconde électrode métallique siliciurée de type à grains hémisphériques 30.The integrated circuit CI comprises a substrate SB, in which a hollow trench has been made comprising a first hemispherical grain type silicided metal electrode 10 surmounted by a dielectric 2, surmounted by a second metal silicide electrode of hemispherical grain type. 30.
On va maintenant décrire plus en détails, les principales étapes d' un mode de mise en œuvre du procédé selon l'invention, permettant d' obtenir le condensateur de la figure 1.The main steps of an embodiment of the method according to the invention, which makes it possible to obtain the capacitor of FIG. 1, will now be described in greater detail.
Sur la figure 2, la référence SB désigne donc un substrat semi¬ conducteur, par exemple en silicium. On réalise une tranchée 4 dans le substrat SB de façon classique et connue en soi. On procède ensuite à la réalisation de la première électrode 10.In FIG. 2, the reference SB designates a semiconductor substrate, for example made of silicon. A trench 4 is produced in the substrate SB in a conventional manner and known per se. The first electrode 10 is then produced.
Pour cela, on forme, également de façon classique et connue en soi, par exemple par dépôt, une couche 1 de silicium, de germanium ou d'un alliage de silicium, tel que par exemple du silicium-germanium, de type à grains hémisphériques (figure 3). Les caractéristiques d' un tel dépôt sont par exemple décrits dans « Fabrication and performance of sélective HSG storage cells for 256 Mb and 1 Gb DRAM applications, A. Banerjee, R. L. Wise, D. L. Plunton, M. Bevan, M. L. Crenshaw, S.Aoyama et M. M. Mansoori, IEEE Transactions on électron devices, vol. 47, No.3, mars 2000 ». A titre indicatif, la couche 1 de silicium ou d' un alliage de silicium de type à grains hémisphériques a une épaisseur de 1000 à 1500 A.For this purpose, a layer 1 of silicon, germanium or a silicon alloy, such as, for example, silicon-germanium, of the hemispherical grain type is formed, also in a conventional manner and known per se, for example by deposition. (Figure 3). The characteristics of such a repository are for example described in "Manufacturing and Performance of Selective HSG Storage Cells for 256 Mb and 1 Gb DRAM Applications, A. Banerjee, RL Wise, DL Plunton, M. Bevan, ML Crenshaw, S.Aoyama. and MM Mansoori, IEEE Transactions on Electron Devices, Vol. 47, No.3, March 2000 ". As an indication, the layer 1 of silicon or of a hemispherical grain type silicon alloy has a thickness of 1000 to 1500 A.
Dans l' exemple décrit ici, la siliciuration, c' est-à-dire la formation d' un siliciure de métal , est obtenue à partir de cobalt.In the example described here, siliciding, that is the formation of a metal silicide, is obtained from cobalt.
Cependant, cette siliciuration peut être obtenue à partir d' autres métaux tels que par exemple le tungstène, le titane ou le nickel.However, this siliciding can be obtained from other metals such as, for example, tungsten, titanium or nickel.
On dépose, par exemple par un dépôt plasma en phase vapeur (dépôt PVD), une couche de nickel sur la couche 1 de silicium ou d' un alliage de silicium de type à grains hémisphériques.For example, a layer of nickel on the layer 1 of silicon or of a hemispherical grain type silicon alloy is deposited, for example by a plasma vapor deposition (PVD deposition).
Bien entendu, l ' épaisseur de la couche de nickel est déterminée en fonction de la phase et de l' épaisseur de siliciure de métal que l ' on souhaite finalement obtenir sachant que lorsque du nickel est utilisé, 1 À de nickel donne 2.2 À de siliciure. Puis on procède à un premier recuit initial, typiquement à une température inférieure à 600 0C, par exemple à une température de 450 0C. Cette température de recuit dépend de la nature du métal utilisé pour la siliciuration. Le nickel réagit alors avec le silicium de la couche 1 pour former du NiSi (figure 4) . L' excès de nickel n'ayant pas réagi peut ensuite être retiré sélectivement par rapport au siliciure. Cette opération de retrait sélectif s' effectue par exemple par gravure humide. Une telle gravure humide est classique et connue en soi, et elle utilise par exemple une chimie H2SO4:H2O2 :H2O, ou bien une chimie HCl : H2O2 :H2O. On se retrouve donc en présence d' une électrode 10 métallique siliciurée avec une morphologie de type à grains hémisphériques sur laquelle est déposée le diélectrique 2.Of course, the thickness of the nickel layer is determined as a function of the phase and the thickness of metal silicide which it is finally desired to obtain, knowing that when nickel is used, 1 N of nickel gives 2.2 A of silicide. Then, a first initial annealing is carried out, typically at a temperature below 600 ° C., for example at a temperature of 450 ° C. This annealing temperature depends on the nature of the metal used for siliciding. The nickel then reacts with the silicon of layer 1 to form NiSi (FIG. 4). Excess unreacted nickel can then be selectively removed from the silicide. This selective removal operation is carried out for example by wet etching. Such wet etching is conventional and known per se, and it uses, for example, a H 2 SO 4 : H 2 O 2 : H 2 O chemistry, or a HCl: H 2 O 2 : H 2 O chemistry. therefore in the presence of a silicided metal electrode with a hemispherical grain type morphology on which the dielectric 2 is deposited.
Le diélectrique peut être un diélectrique conventionnel avec une constante diélectrique relative k de, par exemple, 5. Dans ce cas, la principale amélioration par rapport à l' art antérieur vient de l ' amélioration des capacités de déplétion, de la forte réduction de la résistance série et de la simplification du procédé dans la mesure où il n ' est pas nécessaire de doper par implémentation les électrodes en silicium ou en alliage de silicium, opération parfois difficile particulièrement sur les flancs des tranchées.The dielectric may be a conventional dielectric with a relative dielectric constant k of, for example, 5. In this case, the main improvement over the prior art comes from the improvement of the depletion capacities, the strong reduction of the series resistance and the simplification of the process insofar as it is not necessary to dope by implementation the electrodes silicon or silicon alloy, sometimes difficult operation especially on the sides of the trenches.
Il est également possible d'utiliser des diélectriques à forte constante diélectrique, par exemple de l ' oxyde de Hafnium HfO2 (k= 17), ce qui augmente plus encore la capacité du condensateur. Le diélectrique 2 est surmontée de la seconde électrode.It is also possible to use dielectrics with a high dielectric constant, for example Hafnium oxide HfO 2 (k = 17), which further increases the capacity of the capacitor. The dielectric 2 is surmounted by the second electrode.
Comme illustré dans la figure 1, l' électrode 30 peut être réalisée de façon analogue à la première électrode 10, c' est-à-dire par dépôt de polysilicium HSG, puis siliciuration, de préférence totale, et retrait du métal n' ayant pas réagi. La seconde électrode peut également être réalisée par exemple par dépôt direct de métal (par exemple TiN) sur le diélectrique. Dans ce cas (figure 5), le condensateur comprend une première électrode métallique siliciurée de type à grains hémisphériques 10 , surmontée d ' un diélectrique 2, surmonté d' une seconde électrode métallique 31. Dans les circuits intégrés selon la présente invention, les condensateurs ne sont pas limités à des structures en tranchées, telles que décrites ci-dessus, mais peuvent également être par exemple de type planaire. As illustrated in FIG. 1, the electrode 30 can be made analogously to the first electrode 10, that is to say by deposition of HSG polysilicon, then siliciding, preferably total, and removal of the metal having not reacted. The second electrode can also be made for example by direct deposition of metal (for example TiN) on the dielectric. In this case (FIG. 5), the capacitor comprises a first hemispherical grain silicided metal electrode 10, surmounted by a dielectric 2, surmounted by a second metal electrode 31. In the integrated circuits according to the present invention, the capacitors are not limited to trench structures, as described above, but can also be for example planar type.

Claims

REVENDICATIONS
1. Circuit intégré (CI) comprenant au moins un condensateur à électrodes métalliques caractérisé par le fait qu' au moins une des deux électrodes (10,30) du condensateur est formée de silicium ou d'un alliage de silicium de type à grains hémisphériques siliciuré au moins en surface.An integrated circuit (IC) comprising at least one capacitor with metal electrodes characterized in that at least one of the two electrodes (10, 30) of the capacitor is formed of silicon or a hemispherical grain type silicon alloy. silicided at least on the surface.
2. Circuit intégré selon la revendication 1, dans lequel l ' électrode ( 10) est entièrement formée d' un siliciuré de métal .An integrated circuit according to claim 1, wherein the electrode (10) is entirely formed of a metal silicide.
3. Circuit intégré selon la revendication 1 ou 2, dans lequel la seconde électrode du condensateur est formée de silicium ou d'un alliage de silicium de type à grains hémisphériques siliciuré au moins en surface(30).An integrated circuit according to claim 1 or 2, wherein the second electrode of the capacitor is formed of silicon or an at least surface siliconized hemispherical grain type silicon alloy (30).
4. Circuit intégré selon la revendication 3, dans lequel la seconde électrode du condensateur est entièrement formée d' un siliciuré de métal (30).The integrated circuit of claim 3, wherein the second electrode of the capacitor is entirely formed of a metal silicide (30).
5. Circuit intégré selon l' une quelconque des revendications l à 3 , dans lequel la seconde électrode du condensateur comporte une couche de métal (31) .An integrated circuit according to any one of claims 1 to 3, wherein the second electrode of the capacitor has a metal layer (31).
6. Procédé de fabrication d' un condensateur au sein d' un circuit intégré comprenant l' élaboration d' une première électrode, d'un diélectrique et d' une seconde électrode, caractérisé en ce que l 'élaboration de la première électrode comprend la réalisation d' une couche de silicium ou d'un alliage de silicium de type à grains hémisphériques et la siliciuration de ladite couche au moins en surface.A method of manufacturing a capacitor in an integrated circuit comprising developing a first electrode, a dielectric and a second electrode, characterized in that the development of the first electrode comprises the making a silicon layer or a hemispherical grain-type silicon alloy and siliciding of said layer at least at the surface.
7. Procédé selon la revendication 6 dans lequel la couche de silicium ou d' un alliage de silicium de type à grains hémisphériques est complètement siliciurée.7. The method of claim 6 wherein the silicon layer or a hemispherical grain-type silicon alloy is completely silicided.
8. Procédé selon la revendication 6 ou 7 dans lequel l' élaboration de la seconde électrode est analogue à celle de la première électrode.8. The method of claim 6 or 7 wherein the development of the second electrode is similar to that of the first electrode.
9. Procédé selon la revendication 6 ou 7 dans lequel l' élaboration de la seconde électrode comprend un dépôt de métal. 9. The method of claim 6 or 7 wherein the development of the second electrode comprises a metal deposition.
EP05775544A 2004-06-18 2005-06-07 Integrated circuit comprising a capacitor with metal electrodes, and method of producing one such capacitor Withdrawn EP1774576A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0406674A FR2871935A1 (en) 2004-06-18 2004-06-18 INTEGRATED CIRCUIT COMPRISING A METAL ELECRODES CAPACITOR AND METHOD OF MANUFACTURING SUCH CAPACITOR
PCT/FR2005/001400 WO2006008356A1 (en) 2004-06-18 2005-06-07 Integrated circuit comprising a capacitor with metal electrodes, and method of producing one such capacitor

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EP1774576A1 true EP1774576A1 (en) 2007-04-18

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EP (1) EP1774576A1 (en)
JP (1) JP2008503077A (en)
CN (1) CN1957442A (en)
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WO (1) WO2006008356A1 (en)

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US20100320567A1 (en) 2010-12-23
US20080185681A1 (en) 2008-08-07
US7781296B2 (en) 2010-08-24
FR2871935A1 (en) 2005-12-23
JP2008503077A (en) 2008-01-31
CN1957442A (en) 2007-05-02
WO2006008356A1 (en) 2006-01-26
US8975682B2 (en) 2015-03-10

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