EP1743396A2 - Breitbandiger symmetrierübertrager - Google Patents
Breitbandiger symmetrierübertragerInfo
- Publication number
- EP1743396A2 EP1743396A2 EP05732248A EP05732248A EP1743396A2 EP 1743396 A2 EP1743396 A2 EP 1743396A2 EP 05732248 A EP05732248 A EP 05732248A EP 05732248 A EP05732248 A EP 05732248A EP 1743396 A2 EP1743396 A2 EP 1743396A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- conductor loop
- conductor
- signal input
- output
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims abstract description 132
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 description 12
- 230000008878 coupling Effects 0.000 description 11
- 238000010168 coupling process Methods 0.000 description 11
- 238000005859 coupling reaction Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P5/00—Coupling devices of the waveguide type
- H01P5/08—Coupling devices of the waveguide type for linking dissimilar lines or devices
- H01P5/10—Coupling devices of the waveguide type for linking dissimilar lines or devices for coupling balanced lines or devices with unbalanced lines or devices
Definitions
- the invention relates to a broadband balancing transformer - balun - for transmitting large high-frequency powers from an asymmetrical connection to a symmetrical two-pole connection and vice versa.
- Balancing transformers are required in the higher power range, for example in the case of amplifiers which are constructed from power transistors using push-pull technology in order to achieve the desired power level.
- These convert the high-frequency signal from an asymmetrical coaxial line or strip line to two signal lines designed to be as symmetrical as possible in order to supply it to two symmetrically operating power transistors or push-pull transistors.
- the two symmetrical output signals of the two power transistors or the push-pull transistor can be converted into a high-frequency signal for an unbalanced coaxial line or strip line via a symmetry transformer.
- balun by means of strip conductors arranged on a printed circuit board
- this type of implementation ensures that the balun, including its electrical properties, can be reproduced in mass production in comparison with a coaxial line technology.
- a stripline technology is characterized by a smaller construction volume and lower production costs compared to a coaxial conductor technology.
- balun is shown in EP 0 418 538 AI.
- the high-frequency signal power is transmitted by transformer Coupling between two conductor loops, of which one conductor loop is connected to the single-pole connection of the unbalanced line and the other conductor loop is connected to the two-pole symmetrical connection to the two power transistor amplifiers.
- a good transformer coupling between the two conductor loops is achieved by realizing the two conductor loops in terms of their geometrical position as mutually aligned conductor tracks on the top and bottom of a circuit board.
- Symmetrical transmission ratios on the side of the balancing transformer facing the power transistor amplifier are realized via electromagnetic coupling.
- the two symmetrical connections of the balun on the side of the power transistor amplifier are routed to ground via symmetrically dimensioned conductor loop regions.
- the conductor loop on the asymmetrical side which is routed to ground via symmetrically dimensioned conductor loop regions, is arranged on the printed circuit board in such a way that a symmetrical transformer coupling between these two symmetrical conductor loop regions occurs the side of the asymmetrical line and the two symmetrical conductor loop areas on the side of the power transistor amplifier. This ensures a symmetrical distribution of power from the unbalanced line to the two balanced poles on the side of the amplifier.
- the invention is therefore based on the object of further developing the balancing transformer in such a way that its bandwidth is significantly increased and, at the same time, a symmetrical power distribution from the asymmetrical connection to the two symmetrical poles is realized at the symmetrical connection within this bandwidth.
- the invention is solved by a balun according to claim 1.
- one of the two symmetrical conductor loop areas on the symmetrical side of the balancing transformer is divided into two further conductor loop areas.
- a transformer coupling takes place between the two conductor loop regions on the asymmetrical side and the two conductor loop regions which are connected directly to the two symmetrical poles on the symmetrical side.
- the conductor loop is no longer guided to ground at its end point on the asymmetrical side, but is galvanically coupled between the two divided conductor loop regions on the symmetrical side.
- FIG. 4 is a view of a balun according to the invention.
- Fig. 6 is a "view from below" on the balun according to the invention.
- Fig. 7 is a graphical representation of the transmission behavior of the balun according to the invention.
- the third has a first signal input / output 1 with the two symmetrical poles 2 and 3 and a second signal input / output 4 with a pole 5.
- the two symmetrical poles 2 and 3 of the first signal input / output 1 are, for. B. with the two inputs of a power transistor amplifier, which is not in Fig. 3 is shown connected.
- the pole 5 of the second signal input / output 4 can, for. B. with an inner conductor, not shown in FIG. 3, of a coaxial line. However, it can also be connected to an asymmetrical strip line, coplanar line or triplate line.
- One of the two symmetrical poles 3 of the first signal input / output 1 is led to ground 7 via a first conductor loop region 6, which has a characteristic impedance component in the circuit model of the symmetry transformer in FIG. 3.
- the other of the two symmetrical poles 2 of the first signal input / output 1 is guided to ground 7 via a first series circuit 8, consisting of two first conductor loop regions 9 and 10, which also have a characteristic impedance component.
- the component of the first conductor loop region 6 is constructed symmetrically to the component of the first series circuit 8, consisting of the two first conductor loop regions 9 and 10.
- the first outer connection 14 of a second series circuit 11, consisting of the second conductor loop regions 12 and 13, is connected to the pole 5 of the second signal input / output 4.
- the two second conductor loop regions 12 and 13 each have wave resistances which are each designed symmetrically to one another.
- the second outer connection 15 of the second series circuit 11 is electrically connected to the intermediate connection 16 of the first series circuit 8 of the two first conductor loop regions 9 and 10.
- the design of the second conductor loop areas 12 and 13 and the symmetrical design of the first conductor loop area 6 with respect to the first series circuit 8, consisting of the two first conductor loop areas 9 and 10, results in the electrical-galvanic coupling and the electromagnetic-transformer coupling a symmetrical transmission between the first signal input / output 1 and the second signal input / output 4 and vice versa.
- FIG. 4 shows a balun implemented in stripline technology using a printed circuit board 19.
- FIG. 5 shows a view - “view from above” - on the first side 18 of the circuit board 19
- FIG. 6 shows a view - “view from below” - on the second side 20 of the circuit board 19.
- the two poles 2 and 3 of the first signal input / output 1, the pole 5 of the second signal input / output 4, the first conductor loop regions 6, 9 and 10 and the second conductor loop regions 12 and 13 are as conductor tracks 21 on the first and second side 18 and 20 of the circuit board 19 realized.
- One of the two symmetrical poles 2 of the first signal input / output 1 is implemented as a first linear conductor track 22.
- a second linear conductor 23 is arranged, which is assigned to the other of the two symmetrical poles 3 of the first signal input / output 1.
- the first conductor loop areas 6, 9 and 10 are up to one summarized the gap 25 almost closed conductor loop 24.
- the two ends 26 and 27 of this conductor loop 24 are each connected to one end 28 and 29 of the two linear conductor tracks 22 and 23.
- the clear distance 34 between the two conductor tracks 22 and 23 corresponds to the width of the gap 25.
- the one loop half 30 of the conductor loop 24 contains the first conductor loop regions 9 and 10 arranged between the pole 2 of the first signal input / output 1 and the common ground 7, the other loop half 31 of the conductor loop 24 contains the one between the pole 3 of the first Signal input / output 1 and the common ground 7 arranged conductor loop area 6.
- the intermediate connection 16 of the first series circuit 8, consisting of the two first conductor loop areas 9 and 10 is attached ,
- This can be used for a direct current supply to the symmetrical inputs and outputs 1 and for temperature dissipation from ground.
- two parallel conductor track legs 33 are guided to the almost closed conductor loop 24, which are supported against ground by the interposition of a capacitor (not shown in FIGS. 4 and 5).
- the temperature is dissipated from ground by a through-contacting of the cold point 32 to ground on the second side 20 of the printed circuit board 19, also not shown in FIGS. 4 to 6.
- a third linear conductor 35 is arranged, which realizes the pole 5 of the second signal input / output 4 of the balun.
- a loop-shaped conductor track 36 is formed, which realizes the conductor loop of the two second conductor loop regions 12 and 13.
- This loop-shaped conductor track 36 is geometrically aligned on the second side 20 of the circuit board 19 such that it lies centrally above the conductor track 24 on the first side 18 of the circuit board 19.
- the first and second outer connections 14 and 15 of the second series circuit 11 of the two second conductor loop regions 12 and 13, which are each positioned at the ends of the loop-shaped conductor track 36, are in the region of the intermediate connection 16 of the first series circuit 8 of the first conductor loop Areas 9 and 10 are arranged on the loop half 30 of the almost closed conductor loop 24 and in the area of the pole 5 of the second signal input / output 4 on the third linear conductor track 35.
- the first conductor loop area 6 is directly in parallel with the second conductor loop area 12 and the first conductor loop area 9 is directly in parallel with the second conductor loop area 13 in order to ensure the most efficient electromagnetic-transformer coupling between the first signal. to implement output 1 and the second signal input / output 4.
- the intermediate connection 16 of the first series circuit 8 of the two first conductor loop regions 9 and 10 on the loop half 30 of the almost closed conductor loop 24 on the first side 18 of the circuit board 19 is preferably via a via 40 of the 'circuit board 19 with the second outer connection 15 second series circuit 11 of the second conductor loop regions 12 and 13 at one end of the loop-shaped conductor track 36 on the second side 20 of the circuit board 19 is electrically connected.
- Analog is the pole 5 of the second signal input 4 on the third linear conductor track 35 on the first side 18 of the circuit board 19 via a via 41 of the circuit board 19 with the first outer connection 14 of the second series circuit 11 of the second conductor loops regions 12 and 13 on the other End of the loop-shaped conductor track 36 on the second side 20 of the circuit board 19 electrically connected.
- the loop-shaped conductor track 36 belonging to the second conductor loop regions 12 and 13 on the second side 20 of the printed circuit board 19 is surrounded by a common ground conductor 37.
- FIG. 7 shows the transmission behavior of the balun according to the invention, which was determined in the form of S parameters with a field simulator.
- the balancing transformer according to the invention In contrast to the transmission behavior of the balancing transformer according to the prior art in FIG. 2, the balancing transformer according to the invention, given the design, has resonances in its transmission behavior only at a frequency of over 3 GHz.
- the balun according to the invention can consequently be operated without problems up to an operating frequency of approximately 2.5 GHz.
- the balancing transformer according to the invention has a substantially higher symmetry between the two symmetrical poles 2 and 3 of the first signal input / output 1 in its unproblematic operating frequency range.
- the transmission characteristic in the signal path from pole 5 of the second signal input 4 to pole 2 of the first signal input / output 1 (S parameter S1, 2 in FIG. 7) has an approximate one in the operating frequency range up to approximately 1.6 GHz same course as the transmission characteristic in the signal path from pole 5 of the second signal input / output 4 to pole 3 of the first signal input / output 1 (S parameter S1, 3 in FIG. 7).
- the intermediate connection 16 is preferably arranged such that the lengths 1 of the first conductor loop regions 9, 10 forming the first series circuit 8 have a ratio of 1: 3 to 3: 1.
- the length 1 of the second conductor loop region 13 of the second series circuit 11 is to be adapted to the length 1 of the first conductor loop region 9 of the first series circuit 8.
- the two conductor loop regions 9 and 10 of the first series circuit 8 preferably have a ratio of 1: 1.
- the first conductor loop region 9 consequently has a length of 1/4.
- the second conductor loop region 13 of the second series circuit 11 is consequently adapted with a length of 1/4.
- the invention is not limited to the embodiment shown.
- similar or analog conductor paths and arrangements, but which have the same effect on the bandwidth and symmetry of the balun as the balun shown above, are covered by the invention.
Landscapes
- Coils Or Transformers For Communication (AREA)
- Transmitters (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Amplifiers (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004022185A DE102004022185A1 (de) | 2004-05-05 | 2004-05-05 | Breitbandiger Symmetrierübertrager |
PCT/EP2005/003957 WO2005109975A2 (de) | 2004-05-05 | 2005-04-14 | Breitbandiger symmetrierübertrager |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1743396A2 true EP1743396A2 (de) | 2007-01-17 |
EP1743396B1 EP1743396B1 (de) | 2008-03-12 |
Family
ID=35267281
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP05732248A Active EP1743396B1 (de) | 2004-05-05 | 2005-04-14 | Breitbandiger symmetrierübertrager |
Country Status (6)
Country | Link |
---|---|
US (1) | US7656247B2 (de) |
EP (1) | EP1743396B1 (de) |
JP (1) | JP4437153B2 (de) |
DE (2) | DE102004022185A1 (de) |
ES (1) | ES2301006T3 (de) |
WO (1) | WO2005109975A2 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4674590B2 (ja) * | 2007-02-15 | 2011-04-20 | ソニー株式会社 | バラントランス及びバラントランスの実装構造、並びに、この実装構造を内蔵した電子機器 |
DE102009024997B4 (de) | 2009-06-16 | 2014-05-28 | Rohde & Schwarz Gmbh & Co. Kg | Koppler in planarer Leitertechnik |
EP2980656B1 (de) | 2010-06-11 | 2020-10-14 | Ricoh Company, Ltd. | Informationsspeichervorrichtung, entnehmbare vorrichtung, entwicklerbehälter und bilderzeugungsgerät |
US9784835B1 (en) | 2013-09-27 | 2017-10-10 | Waymo Llc | Laser diode timing feedback using trace loop |
US9350316B1 (en) | 2014-12-17 | 2016-05-24 | Freescale Semiconductor, Inc. | Wideband baluns and methods of their manufacture |
US9692387B2 (en) | 2015-07-24 | 2017-06-27 | Nxp Usa, Inc. | Balun transformer |
CN108270407B (zh) * | 2016-12-30 | 2023-09-05 | 通用电气公司 | 一种平面巴伦及一种多层电路板 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4118670A (en) * | 1975-05-08 | 1978-10-03 | Westinghouse Electric Corp. | Image phased and idler frequency controlled mixer formed on an integrated circuit dielectric substrate |
US4847626A (en) * | 1987-07-01 | 1989-07-11 | Motorola, Inc. | Microstrip balun-antenna |
FR2652197B1 (fr) * | 1989-09-18 | 1992-09-18 | Motorola Semiconducteurs Borde | Transformateurs du type symetrique-dissymetrique perfectionnes. |
US5917386A (en) * | 1997-03-12 | 1999-06-29 | Zenith Electronics Corporation | Printed circuit transformer hybrids for RF mixers |
US6351192B1 (en) * | 1999-03-25 | 2002-02-26 | Industrial Technology Research Institute | Miniaturized balun transformer with a plurality of interconnecting bondwires |
JP2001211010A (ja) * | 1999-11-16 | 2001-08-03 | Murata Mfg Co Ltd | 平衡−不平衡変換回路、平衡−不平衡変換器および通信機 |
DE10105696A1 (de) * | 2001-02-08 | 2002-08-14 | Rohde & Schwarz | Symmetrierübertrager |
-
2004
- 2004-05-05 DE DE102004022185A patent/DE102004022185A1/de not_active Withdrawn
-
2005
- 2005-04-14 ES ES05732248T patent/ES2301006T3/es active Active
- 2005-04-14 US US11/568,671 patent/US7656247B2/en active Active
- 2005-04-14 EP EP05732248A patent/EP1743396B1/de active Active
- 2005-04-14 JP JP2007511913A patent/JP4437153B2/ja not_active Expired - Fee Related
- 2005-04-14 DE DE502005003204T patent/DE502005003204D1/de active Active
- 2005-04-14 WO PCT/EP2005/003957 patent/WO2005109975A2/de active IP Right Grant
Non-Patent Citations (1)
Title |
---|
See references of WO2005109975A2 * |
Also Published As
Publication number | Publication date |
---|---|
ES2301006T3 (es) | 2008-06-16 |
US7656247B2 (en) | 2010-02-02 |
DE502005003204D1 (de) | 2008-04-24 |
EP1743396B1 (de) | 2008-03-12 |
WO2005109975A2 (de) | 2005-11-17 |
JP4437153B2 (ja) | 2010-03-24 |
WO2005109975A3 (de) | 2006-04-06 |
JP2007536839A (ja) | 2007-12-13 |
DE102004022185A1 (de) | 2005-12-01 |
US20080231388A1 (en) | 2008-09-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1743396B1 (de) | Breitbandiger symmetrierübertrager | |
DE3341719A1 (de) | Symmetrieuebertrager | |
DE19815651A1 (de) | Funkfrequenz-Leistungsteiler | |
DE102005009061A1 (de) | Koaxialgleichstromsperre | |
EP2517300B1 (de) | Breitbandrichtkoppler | |
DE112016006983T5 (de) | Koaxialwellenleiter-Hohlwellenleiter-Übergangsschaltung | |
EP0063819B1 (de) | Mikrowellen-Gegentaktmischerschaltung in Streifenleitungstechnik | |
DE2135569A1 (de) | Dreipolige Quadratur Hvbnde | |
DE10102891A1 (de) | Hochleistungsverstärker mit Verstärkerelement, dazugehörige Funkübertragungseinrichtung und Meßeinrichtung dafür | |
DE10202699B4 (de) | Nichtreziprokes Schaltungsbauelement und Kommunikationsvorrichtung, die dasselbe enthält | |
DE102013214818A1 (de) | Gekoppeltes Leitungssystem mit steuerbarem Übertragungsverhalten | |
DE112013004185B4 (de) | Richtkoppler | |
DE2837817A1 (de) | Vorspannungsschaltung | |
EP0683539A1 (de) | Mikrowellenleitungsstruktur | |
DE102009049609B4 (de) | Streifenleiter-Balun | |
DE2253175A1 (de) | Zirkulator mit in mic-technik ausgebildeten anschlussarmen | |
EP1014472B1 (de) | Richtkoppler | |
WO2010139392A1 (de) | Vorwärtskoppler mit bandleitern | |
DE60037125T2 (de) | Radiofrequenz-Verstärkerschaltung | |
EP1017124A1 (de) | Leistungsteiler für Hochfrequenzsignale | |
DE19934671C1 (de) | Planare Antenne | |
EP0649180B1 (de) | Streifenleitung mit abstimmbarer elektrischer Länge | |
EP1623479B1 (de) | Umsymmetrieranordnung | |
EP0518310B1 (de) | Schaltung zum Aufteilen oder Zusammenführen von Hochfrequenzleistung | |
DE2151478C2 (de) | Richtungskoppler |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20060406 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE ES FR GB IT |
|
17Q | First examination report despatched |
Effective date: 20070315 |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: KAEHS, BERNHARD |
|
DAX | Request for extension of the european patent (deleted) | ||
RBV | Designated contracting states (corrected) |
Designated state(s): DE ES FR GB IT |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE ES FR GB IT |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D Free format text: NOT ENGLISH |
|
REF | Corresponds to: |
Ref document number: 502005003204 Country of ref document: DE Date of ref document: 20080424 Kind code of ref document: P |
|
GBT | Gb: translation of ep patent filed (gb section 77(6)(a)/1977) |
Effective date: 20080408 |
|
REG | Reference to a national code |
Ref country code: ES Ref legal event code: FG2A Ref document number: 2301006 Country of ref document: ES Kind code of ref document: T3 |
|
ET | Fr: translation filed | ||
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed |
Effective date: 20081215 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20090424 Year of fee payment: 5 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20100414 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20100414 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 11 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: ES Payment date: 20150427 Year of fee payment: 11 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20150422 Year of fee payment: 11 Ref country code: IT Payment date: 20150429 Year of fee payment: 11 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST Effective date: 20161230 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20160502 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20160414 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: ES Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20160415 |
|
REG | Reference to a national code |
Ref country code: ES Ref legal event code: FD2A Effective date: 20181205 |
|
P01 | Opt-out of the competence of the unified patent court (upc) registered |
Effective date: 20230525 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20230418 Year of fee payment: 19 |