EP1714389A2

EP1714389A2 - Oscillator circuit, used in particular for mobile radio communication

Info

Publication number: EP1714389A2
Application number: EP04786892A
Authority: EP
Inventors: Alexander Belitzer; Stefan Herzinger; Giuseppe Li Puma
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2003-09-30
Filing date: 2004-09-30
Publication date: 2006-10-25
Also published as: DE10345497B4; DE10345497A1; CN101073202A; WO2005034354A2; US7777578B2; WO2005034354A3; US20060226918A1

Abstract

The invention relates to an oscillator circuit comprising an oscillator (4) that can be tuned using discrete values, said oscillator having a tuning member (6) that can be brought into circuit by means of a switching device (5). A rectifier circuit (8), which is connected to the output (41) of the oscillator (4), forms a clock pulse signal from the oscillator signal. In addition, the oscillator circuit contains a phase delay circuit (9) comprising a switching input (91), a clock pulse signal input (97), which is coupled to the output of the rectifier circuit (8) and a switching output (96), which is coupled to the switching device (5). The phase delay circuit (9) has a comparator circuit (94) for comparing a phase of the clock pulse signal that is applied to the signal input with a reference phase. The phase delay circuit is configured to deliver a switching signal, once an activation signal has been applied to the switching input (91) and once the phase of the clock pulse signal that is applied to the signal input (97) matches the reference phase. The switching operation is thus delayed until no phase shift occurs in the clock pulse signal as a result of the shift response of the output signal of the oscillator.

Description

description

Oscillator circuit, especially for mobile radio

The invention relates to an oscillator circuit, in particular for mobile radio.

Frequency-tunable oscillators are used for a wide variety of purposes. Among other things, they provide the clock signal for digital circuits, particularly in mobile radio devices. The output frequency of the oscillator changes due to external influences, such as temperature changes. It is therefore necessary to tune it again or to change the output frequency.

In voltage controlled oscillators (VCOs) this is done by applying a continuous voltage to a capacitance coupled to the resonant circuit of the oscillator. The capacity determines the resonance frequency of the oscillator.

By changing the capacitance due to the voltage change, the output frequency is also changed.

In contrast, in a digitally controlled oscillator (DCO), discrete-value capacities are added to or removed from the resonant circuit of the oscillator. Due to the gradual change in capacitance, a frequency change in individual steps is generated at the output of the digitally tunable oscillator. This discrete-frequency change produces a phase jump in the output frequency.

In modern communication systems, the different circuits use the same reference frequency and the same reference oscillator. For example, in a mobile radio device, the GSM system part and the Bluetooth transceiver use the clock signal from the same digitally tunable oscillator. The GSM system is very sensitive to fluctuations in the Frequency and now generates a control signal for setting a new clock frequency on the digitally tunable oscillator. As a result, a phase jump is generated at the output signal of the oscillator, which is also noticeable in the clock signal. If the Bluetooth transceiver is in a receiver mode at the same time, the transceiver may lose data received due to the phase jump in the clock signal or receive it incorrectly.

Since in general all digital and analog circuits are sensitive to phase changes in the clock signal, it is desirable to minimize the phase jump. Low-pass filters are therefore used in voltage-controlled oscillators, which filter the programmed voltage change and thus only produce a very slow and small phase transition. The disadvantage of this filter method, however, is the long time it takes to change the frequency. This also increases power consumption and the service life of mobile devices in particular decreases. In the case of a digitally tunable oscillator in which a frequency change is carried out by means of a discrete jump in capacitance, such filtering is also possible, but the discrete jump in capacitance cannot be completely avoided.

The object of the invention is to provide an oscillator control circuit in which a phase jump during a frequency change is reduced. Furthermore, it is an object of the invention to provide a method for a frequency change in an oscillator control circuit, in which a jump in the output signal of the control circuit is reduced.

This object is achieved with the objects of the independent claims.

An oscillator control circuit comprises a value-discrete tunable oscillator with an output for providing an oscillator signal. The tunable oscillator holds at least one tunable via a switching device for tuning the frequency of the oscillator signal. A rectifier circuit is connected to the output of the tunable oscillator and is designed to provide a clock signal formed from the oscillator to an output. The clock signal formed from the oscillator is a rectangular clock signal. The oscillator control circuit has a phase delay circuit which has a first switching input and a signal input coupled to the output of the rectifier circuit. A switching output of the phase delay circuit is coupled to the switching device of the oscillator. The phase delay circuit is designed to emit a switching signal at the switching output after an activation signal is present at the first switching input of the phase delay circuit and then when a specific phase of the clock signal is reached.

A phase jump in the clock signal formed by the rectifier circuit occurs especially when the tuning element of the discretely tunable oscillator is switched at a point in time at which the amplitude of the oscillator signal reaches the threshold value (threshold) of the rectifier. According to the invention, the switching operation of the tuning element takes place with the aid of the phase delay circuit at a point in time at which the output signal is significantly different from the threshold value, so that the output signal of the rectifier circuit now has a reduced or negligibly small phase jump during the step response of the oscillator circuit due to the activated tuning element ,

According to the invention, this is achieved by the phase delay circuit, which delays the transmission of the switching signal for the frequency change by a certain phase amount. The phase delay circuit waits until the clock signal reaches a certain phase has, preferably for example a rising or a falling edge. By delaying the switching process until a suitable point in time, a phase jump in the output signal is therefore reduced. The step response of the oscillator signal therefore has no effect on the phase of the derived clock signal.

In an advantageous development of the invention, the phase delay circuit contains a comparison circuit for comparing a phase of the clock signal present at the signal input with a first phase. The comparison circuit is preferably designed for the detection of the rising or falling edge of the clock signal, the first phase being assigned to the edges of the clock signal. The comparison circuit then emits a signal that is delayed by the set phase delay.

In another embodiment, the phase delay circuit contains a comparison circuit for comparing a phase of the clock signal present at the signal input with a reference phase. The phase delay circuit is then designed to emit a switching signal at the switching output after an activation signal has been applied to the first switching input of the phase delay circuit and after the phase of the signal at the signal input has matched the reference phase.

It is particularly expedient if the comparison circuit of the phase delay circuit is designed to emit the switching signal at the switching output of the phase delay circuit when the phase of the clock signal present at the signal input and the reference phase match. The comparison circuit of the phase delay circuit thus produces the switching signal for the switching device of the tunable oscillator, which then switches the tuning element on or off. In a development of the invention, the phase delay circuit has a first and a second operating state. In the first operating state, it is designed for the phase-defined synchronization of the switching signal with the clock signal. The second operating state represents a waiting state in which the phase synchronization circuit does not emit a signal. The comparison circuit can advantageously be switched from the second to the first operating state by the activation signal at the first switching input. It is therefore only activated when a signal for switching the oscillator frequency is present. The comparison circuit expediently switches back to the second operating state after the comparison or the output of the switching signal. In another advantageous development of the invention, the phase delay circuit has a second switching input for supplying a program signal. The second switching input is coupled to a means for setting the phase delay of the comparison circuit. This means that the phase delay can be changed. This is particularly useful when external operating parameters have changed so that a sufficient reduction in the phase jump in the clock output signal with the previous phase delay is no longer sufficient.

In a development of this invention, the setting means has a programmable memory device in which at least two reference phases that can be selected by the program signal are stored. As a result, different reference phases can be stored in the memory device, which are at

Can be selected by the program signal. This is particularly useful if the phase delay circuit is a programmable phase delay circuit with fixed phase values. The program signal thus selects the reference phase in which the phase jump of the clock signal is the smallest. Alternatively, are in the programmable memory device contain at least two phase delays selectable by the program signal.

In another embodiment of the invention, the phase delay circuit is designed to emit a switching signal dependent on the switching signal at the first switching input at the switching output. This is advantageous if the tunable oscillator has several tunable elements that can be switched on. The switching signal at the switching input of the phase delay circuit contains the information as to which of the switchable tuning elements is required for the frequency change. The phase delay circuit therefore switches the correct tuning element with its switching signal at the switching output.

It is advantageous if the at least one switchable tuning element of the oscillator is designed as a charge store. Alternatively, the at least one switchable tuning element of the oscillator is designed as a varactor diode. In another alternative, the at least one tunable tuning element of the oscillator is a capacitor. This changes the resonance frequency of the discretely tunable oscillator by means of a change in capacitance. Fixed capacitance values are always added or disconnected to the resonant circuit of the tunable oscillator via the switching device.

A method for carrying out a frequency change in an oscillator control circuit comprising a discretely tunable oscillator (4) is characterized by the steps:

- Receiving an activation signal for frequency switching of the oscillator at a switching input of the oscillator control circuit; - Comparison of a phase of a clock signal derived from the oscillator signal with a reference phase; - If the two phases match, a switching signal is generated for the frequency switching of the discretely tunable oscillator and - Switching the frequency of the oscillator by the switching signal.

By delaying the frequency switching of the discretely tunable oscillator, a phase jump in the output signal is reduced.

The method is particularly suitable for the circuit according to the invention. In this case, a phase jump in a clock signal of an oscillator circuit is reduced when the oscillator signal is switched over in frequency, in that a signal for frequency switching of the oscillator is fed to the first switching input of the phase delay circuit. The phase delay circuit then compares the phase of the clock signal formed from the oscillator with a reference phase. If the two phases match, the switching signal is generated at the switching output of the phase delay circuit and fed to the switching device for switching the tuning element of the oscillator.

In a further development of the method, if the phase matches the reference phase, a phase delay is additionally waited for and only then the switching signal is generated. The comparison is then expediently designed such that the rising or falling edge, to which a phase is assigned in each case, is detected.

The tuning signal to be switched by the switching device of the oscillator is also expediently selected by the switching signal at the first switching input. This makes sense if the oscillator has several switchable tuning links or a digital tuning matrix. Furthermore, by means of an additional program signal, the reference to be used for the comparison in the phase delay circuit phase can be selected. This makes it possible, for example, to compensate for temperature changes or component variations in production.

In a further development of the method, the frequency of the oscillator is switched over in that a reference signal is generated by the set phase delay and then the switching signal for the frequency changeover is synchronized with the reference signal.

The invention is explained in detail below with the aid of the drawings.

Show it:

FIG. 1 shows an exemplary embodiment of the invention,

FIG. 2 shows a block diagram of a digitally tunable oscillator,

FIG. 3 shows a block diagram of a phase delay circuit according to the invention,

FIG. 4 shows a time diagram,

Figure 5 shows a process example.

FIG. 1 shows an oscillator control circuit, at the output 1 of which a rectangular clock signal with a defined frequency can be tapped. The oscillator control circuit has a first switching input 2 and a program signal input 3.

The oscillator control circuit contains a value-discrete or digitally tunable oscillator (DCO), which has an output for providing an oscillator signal. The frequency of the oscillator signal is determined by a resonance circuit Right. In addition, the oscillator 4 in this exemplary embodiment has two inputs 42 and 43, which are connected via a switch 5 to one connection of a capacitor 6 each. The respective other connection of the capacitor 6 leads to a reference potential 7. When the switch is closed, the capacitors are connected to the resonance circuit (not shown) and thus change the frequency of the oscillator signal provided at the output 41.

The output 41 of the oscillator 4 is connected to a rectifier circuit 8. The rectifier circuit 8 in turn contains an output which is connected to the output 1 of the oscillator control circuit. The rectifier circuit 8 generates a rectangular clock signal from the sinusoidal oscillator signal of the oscillator 4 and outputs it at the output. In this exemplary embodiment, it uses a threshold voltage (Threshold), which it compares with the input signal. If the input signal is greater than this threshold voltage, a signal with a positive and in some cases constant amplitude is generated at the output, if the level of the oscillator signal at the input of the rectifier circuit 8 becomes lower than the threshold value, the rectifier circuit generates a signal with a negative amplitude.

The output of the rectifier 8 is connected to a clock signal input 97 of a phase delay circuit 9. The phase delay circuit 9 contains a switching input 91 and a program signal input 92. The switching input 91 is connected to the switching input 2 of the oscillator control circuit, the program signal input 92 to the program signal input 3. The phase delay circuit has a signal output 96 which is coupled to the switching device 5. Depending on the switching signal at the switching output of the phase delay circuit 9, the switching device 5 switches one of the two capacitors 6 to the inputs 42 and 43 and thus generates a frequency change of the digitally tuned The oscillator circuit 9 itself is activated by an activation signal at the switching input 91. It then compares the phase of the clock signal at the output of the rectifier circuit 8 with a reference phase.

The phase of a signal can be represented as a rotating pointer in a vector diagram. The speed at which the pointer rotates is a measure of the frequency. A phase jump in the clock signal at the output 1 of the oscillator control circuit always occurs when the frequency of the oscillator 4 is switched close to a point in time at which the amplitude of the sinusoidal output signal of the oscillator reaches the threshold value of the rectifier circuit 8. The step response of the oscillator output signal resulting from the frequency changeover also generates a phase jump in the oscillator signal. This can lead to the threshold value being reached not only twice, but more often during a period of time. This also changes the clock output signal. According to the invention, the circuit ensures that the frequency changeover occurs at a point in time at which it is ensured that the step response resulting therefrom does not cause any additional clock signal change.

Reaching the threshold value by the amplitude of the oscillator signal represents a reference point in time, to which phase 0 degrees is assigned in this exemplary embodiment. It makes sense that this is also the rising edge of the clock signal. After half a period of time, the threshold is reached again, which corresponds to a phase of 180 degrees. After a period of time the phase angle is

360 degrees or again the 0 degrees of the starting point.

The comparison circuit of the phase delay circuit 9 now compares the phase of the clock signal with the reference phase. When the rotating pointer reaches the value of the reference phase, the comparison circuit outputs the switching signal to the switching output of the phase delay circuit and that Switching device 5 switches the capacitor 6 to the tunable oscillator. The sudden change in capacitance produces a step response in the output signal of the oscillator 4. However, this has already subsided when the amplitude of the output signal of the oscillator reaches the threshold value of the rectifier circuit. This prevents a phase jump at the output of the clock signal.

For the comparison circuit of the phase delay circuit, it is irrelevant how fast the phase pointer of the clock signal rotates. Starting from the phase 0 degrees, corresponding to the time of the zero crossing of the amplitude, the switching signal is delayed until the two phases match. This depends on the speed of rotation of the phase pointer or on the frequency of the clock signal. However, the reference phase must be set so that the step response of the oscillator signal has already decayed to such an extent that the phase value in the rectified clock signal does not occur when the threshold value crosses again.

In this case, the rectifier circuit only has a threshold voltage. It can be implemented, for example, by means of a suitably designed comparator position. Likewise possible implementations are bistable flip-flops such as Schmitt triggers, which however have a hysteresis or two threshold values. Suitable flip-flop circuits can also be implemented as a rectifier circuit.

An embodiment of the phase delay circuit 9 is shown in FIG. 3. This contains a comparison circuit 94 which can be activated by a switching signal at the input 91 and which carries out a comparison with the phase of the signal present at the clock signal input 97 with a reference phase. The reference phase is freely selectable. It is provided by a circuit 95 which is connected to the program input 92 for the Program signal is connected and has a memory device 921. Various predetermined reference phases are stored in the memory device 921. Depending on the program signal at the program signal input 92, the circuit 95 selects a reference phase from the memory device 921 and sends it to the comparison device 94.

Furthermore, the phase delay circuit 9 contains a circuit 93, which is connected with one input to the comparison circuit 94 and a second input to the switching input 91.

The switching signal at input 91 is a digital switching signal and, in addition to the request for a frequency change, also contains information about which frequency change is to be carried out. This results in a defined state as to which capacitance is to be switched into the resonant circuit of the oscillator. The circuit 93 evaluates this information and generates a switching signal from it. The switching signal is emitted at the input 96 as soon as the comparison means 94 in turn has emitted the start signal to the circuit 93.

In the embodiment of FIG. 3, the phase delay circuit is a programmable phase delay circuit. Several reference phases are stored in the memory device 921. One of these reference phases is selected by the signal at input 95 and used for the comparison. This is particularly useful if the reference phase to be set is not known in advance, but must first be determined through a series of tests.

FIG. 6 shows another embodiment of the phase delay circuit according to the invention. The circuit contains an edge detector which detects the rising edge of the clock signal at the clock signal input 97. If a rising edge is detected in the clock signal, the edge detector 94a generates a signal to the delay circuit 94b. This is delayed the signal around a certain phase, for example around pi / 8. The circuit 95b can be used to set various phase delays for the delay circuit 94b. For this purpose, the circuit 95b receives information about the current clock frequency from the edge detector 94a. This embodiment is simpler than that in FIG. 3, since only a simple edge detector and a delay circuit are required. However, the edge detector is ultimately also a comparison circuit which detects the phase assigned to the edge.

The image shown in FIG. 4 results in all versions. At time T1, the switching signal for frequency switching is sent to the phase delay circuit according to FIG. 1, 3 or 6. At this point in time, the undelayed clock signal TS1 has a falling edge, a frequency change would lead to a strong phase jump in the clock signal. The switchover is therefore delayed until a rising edge has been detected again and the phase has additionally reached a certain amount. This is equivalent to the lapse of a certain time. At time T2, the switching signal for frequency switching is sent out by the phase delay circuit. The step response has already subsided sufficiently by the next falling edge.

The edge detector of the phase delay circuit according to FIG. 6 detects the rising edge of the clock signal TS1 and forwards a signal to the delay circuit 94b. This is delayed by the specific phase amount pi / 8, which at the same time also corresponds to a frequency-dependent delay time. In contrast, the comparison circuit of FIG. 1 or 3 detects the phase of the clock signal TS1. For example, the rising edge of the clock signal corresponds to phase 0 ° and the falling edge to phase 180 °. Accordingly, at the time T1, the phase of the clock signal TS1 was just 180 °. The reference phase in the comparison circuit is however, for example pi / 8, i.e. 22.5 °. When this phase is reached with the clock signal TS1, the phase delay circuit sends out the switching signal vSchl. Both phase delay circuits therefore each generate a delayed switching signal.

FIG. 2 shows a block diagram as an exemplary embodiment of a digitally tunable oscillator, in which the switching devices 5 and the capacitors 6 are contained in a digitally switchable capacitance field 44. The oscillator shown in Figure 2 is a symmetrical LC oscillator. A voltage source 45 is connected to one end of an inductor 46 and 47, respectively. The other two ends of the inductors 46 and 47 form both the symmetrical switching output of the oscillator 4 and one

Connection for the digital controllable capacitance field 44. This also has a control input 441, which is connected to the switching output, not shown, of the phase delay circuit 9.

The switched capacitances within the capacitance field 44 as well as the inductors 46 and 47 determine the resonance frequency of the oscillator and thus also the output frequency at the output 41. Furthermore, the oscillator contains a damping amplifier, which is formed by two MOS transistors 48 and 49. The source connections of the MOS transistors 48 and 49 are connected to the reference potential 50. The drain connection of the field effect transistor 48 is connected to the capacitance field 44 and the inductance 46, the drain connection of the field effect transistor 49 is connected to the inductance 47. The gate connections of the MOS transistors 48 and 49 are each cross-coupled to the drain connection of the other transistor. This provides a negative impedance, which serves to dampen the oscillator 4. The capacitance field 44 contains the capacitors shown in FIG. 1 and the switching device which, depending on the control signal at the input 441, enables the individual capacitances to be switched on and off independently of one another. The control signal is preferably a digital signal that controls the individual switches for the capacitances to be switched. The capacities used are provided both by capacitors and by varactor diodes.

A method for a series of tests for determining the optimal phase delay can be seen in FIG. In the first step S1, one of the stored reference phases REF is selected by the program signal PES at the input 95 and transmitted to the comparison circuit in step S2. Then a first frequency F1 is set at the output of the oscillator in step S3. In step S4 of the method, a second frequency is set at the output of the oscillator in that a switching signal AS is applied to the input 94 of the phase delay circuit 9. The comparison circuit then compares the phase of the clock signal with the previously set reference phase and only outputs the switching signal when the two phases are the same.

In step S5 of the method, it is observed whether a phase jump occurs at output 1 of the oscillator control circuit after a frequency change. If this is the case, the set reference phase was not optimally selected and the resulting phase delay was not sufficient. It then becomes a second reference phase with a different program signal

PRS2 selected and the further steps S1 to S5 repeated. Overall, the process is repeated with different reference phases until the phase jump has a minimum or disappears completely. The optimal reference phase determined in this way is identified in step S6 as the optimal phase and is used in the following and in particular in operation. There are various variations of the procedure. In particular, a frequency change with a set reference phase can be carried out several times in order to be sure that the optimal reference phase has been found.

In this method, the memory device contains a number of preset reference phases. In a slightly different embodiment, the comparison means directly comprises several adjustable reference phases which can be controlled directly by the PRS program signal. A storage device is dispensed with.

Of course, a reference phase can also be defined depending on the frequency change to be carried out. When changing frequencies with a big difference between the two frequencies, it makes sense to divide them into several smaller ones. This reduces the size of the step response. To determine the optimal reference phase, the clock signal must be examined for a possible phase jump or additional clock changes. This can be done with a measuring instrument such as a

Oscilloscope done manually, for example in production. However, it is also possible to provide a circuit which automatically determines an optimal phase delay. This can be particularly useful if changes in the external operating parameters such as temperature and operating time make it necessary to change the reference phase.

In another embodiment of the method, a wide variety of reference phases are selected by the program signal. The optimal reference phases are then stored in the memory device and selected by a second program signal at the program input. This method differs from the previous one in that it is more flexible since phases that have already been defined in the memory device are not used. In this embodiment, the comparison means is designed such that it has different reference phases for the same and in particular can use value-continuous reference phases.

FIG. 7 shows an alternative embodiment of the method. In step S11, a fixed phase delay is selected via the signal PRS and transmitted to the delay circuit. In the second step, the signal for a frequency change of the oscillator is given. In step S33, the edge detector detects a rising or alternatively a falling signal edge and then emits a signal AS1 to the delay circuit in the event of such an event. The delay circuit delays the switching signal by the set phase amount in step S44. Then it outputs the switching signal vSchl at the output and the oscillator switches the frequency. Here too, an optimal observation of the clock signal during the frequency change and selection of other phase delays in the delay circuit can be used to find an optimal phase delay in which a phase jump is minimized.

The oscillator control circuit according to the invention can be used not only for transmitters or receiving devices for mobile radio, but also whenever clock signals have to be generated which are very sensitive to phase changes.

LIST OF REFERENCE NUMBERS

1 output of the oscillator control circuit 2 switching input of the oscillator control circuit

3 Program signal input of the oscillator control circuit

4 digitally tunable oscillators

5 switching device

6 capacitors

7 Reference potential

8 rectifier circuit

9 phase delay circuit

41 exit

42 43: entrance

44 digitally switchable capacity field

45 voltage source

46 47: Inductors

48 _. 49: MOS transistors

50: reference potential

441: digital switching input

91: switching input

92: Program signal input

93, 95: circuit

94: comparison circuit

921: storage device

96: digital switching output

97: clock signal input t: time

Tl, T ₂ : times

Δt: time difference

TS1, TS2: clock signals

Ski: switching signal

VSchl: Delayed switching signal

Claims

Claims:

1. Oscillator circuit with a control for a frequency change, in particular for mobile radio, comprising: - an oscillator (4) that can be tuned discretely with an output (41) for providing an oscillator signal and with at least one tuning element that can be activated via a switching device (5) 6) to tune a frequency of the oscillator signal; - One connected to the output (41) of the oscillator (4)

Threshold circuit (8) with an output for providing a clock signal, which is formed from the oscillator signal and has a phase; characterized by - a phase delay circuit (9) with a first

Switching input (91), with a signal input (97), which is coupled to the output of the threshold circuit (8), with a switching output (96), which is coupled with the switching device (5) of the oscillator (4), and with a comparison circuit (94) which is designed to compare the phase of the clock signal present at the signal input (97) with a reference phase,

- The phase delay circuit (9) is designed to emit a switching signal at the switching output (96) by applying an activation signal to the first switching input (91) and then reaching a predetermined phase of the clock signal.

2. Oscillator circuit according to claim 1, characterized in that the phase delay circuit (9) comprises an edge detector circuit (94a) for detecting an edge of the clock signal present at the signal input (97) and wherein the phase delay circuit (9) for emitting the switching signal after detection the edge and a subsequent phase delay is formed.

3. Oscillator circuit according to claim 1, characterized in that the comparison circuit (94) of the phase delay circuit (9) for emitting the switching signal at the switching output (96) of the phase delay circuit (9) when the phase of the clock signal applied to the signal input (97) matches the reference phase is trained.

4. Oscillator circuit according to one of claims 1 to 3, characterized in that the phase delay circuit (9) is formed in a first operating state for delivering the delayed switching signal and a second operating state of the phase delay circuit (9) forms a waiting state, the phase delay Delay circuit (9) can be switched from the second operating state to the first operating state by the activation signal.

5. Oscillator circuit according to one of claims 1 to 4, characterized in that the phase delay circuit (9) has a second switching input (92) for supplying a program signal, which has a means (95, 95b) for setting the reference phase or the phase delay of the circuit (94, 94b) is coupled.

6. Oscillator circuit according to claim 5, characterized in that the means (95) for setting comprises a programmable memory device (921) in which at least two predetermined reference phases or at least two predetermined phase delays can be stored, the means (95) for one Selection of one of the at least two reference phases or phase delays depending on the program signal is formed.

7. Oscillator circuit according to one of claims 1 to 6, characterized in that the phase delay circuit (9) is designed to emit a switching signal dependent on the activation signal at the first switching input (91) at the switching output (96).

8. Oscillator circuit according to one of claims 1 to 7, characterized in that the at least one switchable tuning element (6) of the oscillator (4) is designed as a charge store.

9. Oscillator circuit according to one of claims 1 to 8, characterized in that the at least one switchable tuning element (6) of the oscillator (4) is designed as a varactor diode.

10. A method for carrying out a frequency change in an oscillator circuit comprising a discretely tunable oscillator (4), in which (a) an activation signal for frequency switching of the oscillator (4) is fed to a switching input (2) of the oscillator circuit; (b) a phase of a clock signal derived from the oscillator signal is compared with a reference phase; (c) if the two phases match, a switching signal for the frequency switching of the discretely tunable oscillator is generated; (d) the frequency of the oscillator signal is switched by the switching signal.

11. The method according to claim 10, characterized in that a rising or falling edge is detected in step (c) and the generation of the switching signal is delayed by a certain phase delay upon detection.

12. The method according to any one of claims 10 to 11, characterized in that a tuning element (6) to be switched by a switching device (5) of the oscillator (4) is selected by the activation signal at the switching input (2) of the oscillator circuit.

13. The method according to any one of claims 10 to 12, characterized in that the reference phase to be used for the comparison is selected from a set of predetermined reference phases by a program signal.