EP1702369A1

EP1702369A1 - Semiconductor arrangement with non-volatile memories

Info

Publication number: EP1702369A1
Application number: EP04802810A
Authority: EP
Inventors: Recai Sezi; Andreas Walter; Reimund Engl; Anna Maltenberger; Christine Dehm; Arkalgud Sitaram; Ihar Kasko; Joachim Nützel; Jakob Kriz; Thomas Mikolajick; Cay-Uwe Pinnow
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2003-11-28
Filing date: 2004-11-24
Publication date: 2006-09-20
Also published as: DE10355561A1; US20070194301A1; WO2005053027A1

Abstract

The invention relates to a semiconductor arrangement comprising at least one non-volatile memory cell that is provided with a first electrode which consists of at least two layers. Said semiconductor arrangement further comprises an organic material that forms a bond with the layer of the first electrode, which is in direct contact therewith. The invention also relates to a method for producing said non-volatile memory cell, a semiconductor arrangement comprising a plurality of inventive memory cells, and a method for the production thereof.

Description

description

Semiconductor device with non-volatile memories.

Various cells are known from the prior art which can be used in the production of semiconductors. US 4,371,883 describes a cell which has a film of an organic material between two metal electrodes, the electron acceptor with one of the electrodes, which consists of copper (Cu) or silver (Ag), a charge transfer complex (CT complex) forms. The organic material described in US 4,371,883 is, for example, tetracyanoquinodimethane (TCNQ), tetracyanonaphthoquinodimethane (TNAP), tetracyanoethylene (TCNE), dichlorodicyanobenzoquinone (DDQ), or their derivatives. Using an electric field, the cell can be switched between two states which have different resistances (ON or OFF state), so that these two states can be evaluated as "0" or "1", for example.

However, the cell according to US 4,371,883 has significant disadvantages, so that such a cell is out of the question for use in microelectronics. A disadvantage of the cell according to US 4,371,883 is, among other things, that the film thickness considered necessary is between 1 and 10 μm. The further disadvantage is that the ratio between the resistances of the ON or OFF state is very low and is only 66 and that the structure of the cell according to US 4,371,883 is not compatible with the conventional structures in microelectronics. For example, electrodes such as gold, magnesium or chrome are used in

Ersatzbiatt chip manufacture avoided. The decisive disadvantage, however, is that the cell cannot be used as a non-volatile memory cell, since such a cell changes from the ON state to the OFF state after the electrical field has been switched off (US 4,371,883, column 5, lines 15-17 ). The transition time depends on the film thickness. Further versions of such cells are e.g. B. in US 4,652,894 or 5,161,149.

The object of the present invention is to provide a semiconductor arrangement with a non-volatile memory cell, which enables a high integration density, is compatible with the common manufacturing processes in microelectronics, and has improved properties compared to the memory cells according to the prior art.

This object was achieved by the subject matter of patent claim 1.

The advantages of the cell structure according to the invention are reversible switchability, a ratio between ON and

OFF resistors up to 1000 or higher, non-destructive reading, since there is no need to rewrite after reading, since the cell works according to the resistive principle, scalability up to an area of 40 n ² , non-volatile information storage, functionality down to

Film thicknesses of approx. 30nm, thermal stability up to 350 ° C, the functionality of the cell even at a temperature of up to 200 ° C, good adhesion of the layers to each other, switchability in the presence of air and moisture, selective formation of the electrical switchable chemical Substance directly above the electrode, so that in the presence of an insulator, such as. B. silicon dioxide, the complex is formed only over the electrode, simple and inexpensive generation of the complex and the suitability of the memory cell for the production in multiple layers, such as. B. in the Cu Damascene technique.

The semiconductor arrangement according to the invention with a non-volatile memory cell consists of a substrate which has two electrodes and an organic material lying between them (identified in the drawings as material X), one electrode forming a connection with the organic material. This "connection" can form with the formation of covalent or ionic bonds, but also with the formation of charge transfer complexes or weak bonds such as dipole-dipole interactions etc.

In addition to organic materials, inorganic or inorganic-organic materials (also as material X) can also be used in special cases to form the above-mentioned compound. These are especially sulfur, selenium or tellurium both in pure and in bound form (i.e. organo compounds of sulfur,

Selenium or tellurium and optionally oligo- or polymers). However, since mainly organic materials are used, the material is defined below as organic material. The organic material is preferably selected from the following group:

where R 1, R ₂ , R ₃ , R, R5, Rβ _r R7, and R _{8 can} independently have the following meanings: H, F, Cl, Br, I (iodine), alkyl, alkenyl, alkynyl, O-alkyl , 0-alkenyl, O-alkynyl, S-alkyl, S-alkenyl, S-alkynyl, OH, SH, aryl, heteroaryl, O-aryl, S-aryl, NH-aryl, O-heteroaryl, S-heteroaryl, CN , N0 ₂ , - (CF ₂ ) _n - CF ₃ , - CF ((CF ₂ ) _n CF ₃ ) 2, - Q— (CF ₂ ) _n - F3, - CF (CF ₃ ) ₂ , - ^ (CF ₃ ) ₃ as well

The following applies to n: n = 0 to 10 The following applies to Q: —S—

R _g , Rio, Rn, Rχ ₂ can be independent of one another: F, Cl, Br, I, CN, N0 ₂ R ₁ 3, Rχ, R ₁₅ , Ri _ß , Rχ can be independent of one another: H, F, Cl, Br, I, CN, N0 ₂

Xi and X ₂ can be independent of each other:

For Y: 0, S, Se For Zi and Z _{2 the} following applies independently: CN, N0 ₂

The substrate can be silicon, germanium, galium arsenide, galium nitride; any material that contains any compound of silicon, germanium or galium; a polymer (ie plastic; filled or unfilled, e.g. as a molded part or film), ceramic, glass or metal. This substrate can also be a material that has already been processed and can contain one or more layers of contacts, conductor tracks, insulating layers and other microelectronic components. The substrate is, in particular, silicon, which is already processed in accordance with the front end of line (FEOL), that is to say already contains electrical components such as transistors, capacitors, etc. — manufactured using silicon technology. There is preferably an insulating layer between the substrate and the next electrode; especially if the substrate is electrically conductive. However, there may also be several layers between the substrate and the next electrode. The substrate can only serve as a carrier material or fill an electrical function (evaluation, control). In the latter case, there are electrical contacts between the substrate and the electrodes that are on the substrate be applied. These electrical contacts are, for example, contact holes (vias) filled with an electrical conductor. However, it is also possible for the contacts to be made from the lower to the upper layers by means of metallizations in the edge regions of the substrate or the chips.

A preferred device of the invention is the so-called hybrid memory, the substrate being processed in the conventional front-end-of-the-line (FEOL) CMOS silicon technology and the memory layer (s) then being applied to it. However, as mentioned above, the substrate is not limited to this.

The sandwich structure of the memory cell (s) described above, consisting of two electrodes and the organic material or the compound formed between them, can be applied to the substrate not only once but several times in a stacked form. This creates several "levels" for the memory cells, each level consisting of two electrodes and the connection between them (the electrodes adjoin the two surfaces of the connection). Of course, there can also be several cells in one level (Zeil array). The different Layers can be separated from one another with an insulator. It is also possible that two, but not three, electrodes are used for two layers lying one above the other, ie the “middle” electrode is shared.

It was surprisingly found that the cell according to the invention in the semiconductor arrangement can keep the applied state for a very long time without an applied voltage, so that the cell therefore as one non-volatile memory can serve. It could be shown that the semiconductor arrangement according to the invention with the cell according to the invention is still clearly legible or functional even after several thousand cycles of the ON / OFF change and can even maintain the applied state for several months. The electrode which faces the substrate (hereinafter referred to as the lower electrode) preferably consists of at least two layers, the layer which is in direct contact with the substrate (hereinafter referred to as layer 1 of the lower electrode), titanium ( Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), further TiW, TaW, WN or WCN as well as IrO, RuO, SrRuO or any combination of these materials - also in two or more Layers - can be. Furthermore, in combination with the above-mentioned layers or materials, thin layers of Si, TiNSi, SiON, SiO, SiC, SiN or SiCN can also be present. Thus, the layer 1 of the lower electrode itself can consist of more than one layer.

The abbreviations TiN, TaN etc. are only symbolic, ie they do not reflect exact stoichiometric relationships (e.g. silicon dioxide is not identified as Si02 here, but rather as SiO). The ratio of the components can be changed as desired within possible limits. The other layer (hereinafter referred to as layer 2 of the lower electrode) has a metal, preferably copper, which forms the above-mentioned connection with the organic material (material X). This layer (layer 2) that forms the connection can either be pure metal or an alloy of several metals. It is crucial, however, that this layer contains a metal that can form the connection with the organic material. The preferred material is copper and its alloys with other metals. Silver and its alloys with other metals are also suitable.

Various methods are suitable for depositing the above-mentioned layers. These can e.g. B. PVD, CVD, PECVD, vapor deposition, electroplating, electroless plating or atomic layer CVD (ALCVD); however, the methods are not limited to these.

The second electrode (upper electrode) can consist of one or more layers. The second electrode is preferably aluminum, copper, silver, AlCu, AlSiCu, titanium, (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), furthermore TiW, TaW, WN or WCN as well IrO, RuO, SrRuO or any combination of these materials - also in two or more layers - can be. In combination with the layers or materials mentioned above, thin layers of Si, TiNSi, SiON, SiO, SiC, SiN or SiCN can also be present. Thus, the layer 1 of the lower electrode itself can consist of more than one layer.

However, the type of electrodes suitable is not limited to the materials mentioned above.

02 = layer 2 of the upper electrode 01 = layer 1 of the upper electrode V = formed connection U2 = layer 2 of the lower electrode Ul = layer 1 of the lower electrode

The organic material which is arranged between the electrodes is preferably an electron acceptor, ie a molecule with electron-withdrawing atoms (e.g. -Cl, -F, -Br, -I) or groups (e.g. -CN, -C0-, -N0 ₂ ) and forms the corresponding connection with the lower electrode. Molecules which contain at least one of the above-mentioned atoms and / or groups in their framework are particularly preferred as the electron acceptor. Of course, several of the atoms or groups mentioned above can also be present. The preferred organic materials are TCNQ and DDQ. The compound is formed by a selective reaction of the organic material with layer 2 of the lower electrode, which, for. B. contains copper or silver. The composition of the lower electrode and the organic material is not limited to TCNQ and copper, but can on the one hand be made of any organic material (which contains at least one of the above-mentioned atoms or groups and on the other hand can be made of any metal). that the electrode contains a metal that with the organic material or with a component of the organic material forms the connection. The suitable organic material can e.g. B. correspond to one of the structures listed in Table 1. It is also possible for more than one of the molecules mentioned in Table 1 to form the compound with the metal. However, the number of electron acceptors is not limited to the molecules listed in Table 1.

In addition to the electron acceptors mentioned above, other materials such as. B. sulfur in elemental form or sulfur-containing organic compounds with the (lower) electrode form the connection (z. B. copper sulfide). Furthermore, for example, selenium or compounds containing selenium or tellurium or compounds containing tellurium can also form a connection with the lower electrode.

The advantageous properties of the cell according to the invention are shown in Table 2.

Explanations: Threshold voltage: threshold voltage at which the cell switches from OFF to ON. Retention time: Time period in which the memory state (ON or OFF) is maintained without applied voltage Endurance: number of the maximum possible write and

Deletion cycles / pulses

Imprint: Number of the maximum possible (one-sided) write or erase pulses without the properties (threshold voltage, values for ON and OFF

Resistances, course of the U-I diagram etc.) show a clear, permanent change.

Read: Number of the maximum possible reading pulses

The basic condition for everyone is that the cells do not break during the experiments or that the electrical values do not exceed certain permitted tolerances.

The semiconductor arrangement according to the invention can also have a plurality of non-volatile memory cells and the plurality of cells can be built into the semiconductor arrangement with a high integration density.

The method for producing the semiconductor arrangement is described below.

To manufacture the semiconductor arrangement with the memory cell according to the invention, a substrate is first provided.

The substrate can be silicon, germanium, galium arsenide, galium nitride as described above; any material that contains any compound of silicon, germanium or galiu; a polymer (ie plastic; filled or unfilled, e.g. as a molded part or film), ceramic, glass or metal. This substrate can also be an already processed material and one or more layers Contacts, conductor tracks, insulating layers and other microelectronic components included.

The substrate is in particular silicon, which has already been processed in accordance with front-end-of-line (FEOL); H. already contains electrical components such as transistors, capacitors etc. - manufactured using silicon technology. There is preferably an insulating layer between the substrate and the next electrode; especially when the substrate is electrically conductive. However, there may also be multiple layers between the substrate and the next electrode.

The substrate can only serve as a carrier material or fill an electrical function (evaluation, control). In the latter case, there are electrical contacts between the substrate and the electrodes which are applied to the substrate. These electrical contacts are, for example, contact holes (vias) filled with an electrical conductor. However, it is also possible for the contacts to be made from the lower to the upper layers by means of metallizations in the edge regions of the substrate or the chips.

The lower electrode is first applied to the substrate. An insulating layer is optionally located between the substrate and the lower electrode, but this is particularly necessary if the substrate or the top layer of the substrate is electrically conductive. In the case of silicon as a substrate, this insulating layer can, for. B. be silicon oxide. The lower electrode introduced into the substrate consists of at least two layers and can be produced by the methods described below. The electrode can be deposited from the gas phase or from solution. For this purpose, methods such. B. PVD, CVD, PECVD, vapor deposition, electroplating, electroless plating or atomic layer CVD (ALCVD) are suitable. The layers U1 and U2 are, for example, deposited one behind the other and then structured. For this purpose, a photoresist is placed on the layer U2 and this is structured in accordance with customary processes (exposure, development, etc.). This structure is then transferred into the two layers by means of etching through a gas or a gas mixture or else through a liquid or liquid mixture. The two layers can be etched with the same reagent (gas or liquid) or require different reagents.

In addition to structuring by etching, the layers can also be structured using the so-called da ascene technique. For this purpose, for example, an insulating layer (preferably silicon oxide) lying above the substrate is structured by means of lithography and etching. After stripping the photoresist, the two layers are deposited, so that the trenches or holes formed during the structuring in the insulating layer are completely filled with the electrode materials. Then the part of these materials that is above the surface of the insulating layer is ground back. The grinding process can be carried out using the so-called CMP technique (CMP = chemical mechanical planarization or chemical mechanical polishing). This results, for example, in conductor tracks and / or contact holes which are filled with the electrode materials and embedded in the insulating layer or have exactly the same height as the insulating layer. The layer 2 of the lower electrode (U2) is preferably copper or copper-containing and forms the corresponding connection with the organic material, which is subsequently applied. It can also contain silver. The organic material can e.g. B. be applied to the electrode in a solvent mixture. If the organic material is TCNQ, a solvent mixture of at least two solvents is preferably used, one of which is preferably acetonitrile or propionitrile or another solvent which contains -CN groups. The second solvent is preferably a ketone, an alcohol, an ester, an aromatic, an aliphatic or cycloaliphatic or an ether and mixtures thereof. Are suitable for. B. acetone, diethyl ketone, cyclohexanone, cyclopentanone, butanone, cyclohexane, gamma-butyrolactone, ethyl acetate,

Ethoxyethyl acetate, methoxypropyl acetate, ethoxyethyl propionate, ethyl alcohol, propyl alcohol, iso-propanol, dibutyl ether, tetrahydrofuran, chlorobenzene, benzyl alcohol. The duration of this treatment can be between 10 seconds and 10 minutes. Depending on the properties of the solvent, the treatment temperature is between -20 and 100 ° C. Solvent mixtures are also suitable for many substances mentioned in Table 1. The proportion of the solvent containing the -CN group is 0.01 to 65 vol%. Its share depends on the composition of the entire solution. This solution can also contain more than two solvents, as well as more than one organic material (i.e. material X).

It is then rinsed with one of the solvents mentioned above, such as acetone. This rinsing step serves in particular to remove the excess TCNQ from the substrate, so that only the connection formed in the area the electrode remains because the connection can only be formed in this area.

The organic material can also be evaporated onto the lower electrode. After vapor deposition, it is necessary to subject the substrate to thermal treatment in order to make the connection. Only after this temperature treatment can the substrate be rinsed with a solvent to remove the excess TCNQ. If the organic material is evaporated onto the electrode, it is advantageous if the evaporation time is between 2 and 30 minutes. The pressure to be used is in a range between 0.000001 to 200 bar and the vapor deposition is carried out at a substrate temperature between -50 to 150 ° C. It is also possible for not just one, but two or more organic materials X to be vapor-deposited onto the electrode simultaneously or in succession.

The properties of the semiconductor device with the

Memory cells can be further improved if the compound formed is post-treated in a cell produced by the method described above, preferably immediately after the formation of the compound, sometimes also during the formation of the compound. The

Post-treatment is accomplished by contacting a solution of an after-treatment reagent with the compound. As the aftertreatment reagent, amines, amides, ethers, ketones, carboxylic acids, thioethers, esters, aromatics, heteroaromatics, alcohols or various sulfur- or selenium-containing compounds such as sulfur heterocycles, compounds with -SO groups or thiols are particularly suitable, however the number of suitable reagents not only for those limited. In addition to saturated, the reagents can also contain unsaturated groups. Examples of aftertreatment reagents are diethylamine, triethylamine, dimethylaniline, cyclohexylamine, diphenylamine, dimethylformamide, dimethylacetamide, dimethyl sulfoxide, acetone, diethyl ketone, diphenyl ketone, benzoic acid phenyl ester, benzofuran, N-methylpyrrolidone, gamma-butyl lactone, toluene moleolene, toluene , Oxazole, benzimidazole, benzopxazole, quinoline, quinoxaline, fulvalene, furan, pyrrole, thiophene or diphenyl sulfide. The

Treatment time is preferably between 15 s to 15 min. At a temperature of preferably -30 to 100 ° C, either in air or under an inert gas, such as. B. nitrogen or argon.

Experience has shown that the aftertreatment reagent can be built into the storage cell or it can attach to the cell. The existence of the aftertreatment reagent can be demonstrated, for example, after thermal desorption at higher temperatures using gas chromatography GC or mass spectrometry MS.

Surprisingly, even very small amounts (from a few pp) of the built-in or attached after-treatment reagent can cause significant improvements in the properties of the memory cell. However, the incorporation of the aftertreatment reagent is not necessary to improve the properties, u. An aftertreatment may also suffice for this, without an installation being proven by GC or MS.

Alternatively, the compound can be contacted with gaseous (or steam) aftertreatment reagent. In air or under an inert gas, such as. B. nitrogen or argon, the aftertreatment runs at a pressure of 0.00001 to 1000 bar at a substrate temperature between -30 and 150 ° C. A temperature step can then follow, but is not necessary in every case.

A cell which has been post-treated in this way has an improved (ie lower) threshold voltage when switching the cell by up to 40%, a ratio between the ON and OFF state which is ten times higher than that of a cell which has not been post-treated, and a factor of up to 100 times higher endurance as well as improved I print characteristics and an improvement in shift adhesion by up to 20%.

However, some of the "aftertreatment reagents" can also be evaporated simultaneously with the material X or directly in succession (they also bring the advantages mentioned above), so that they are subjected to the subsequent temperature step together.

In a further aspect, the invention relates to a

Integration concept for a semiconductor arrangement with several cells according to the invention. The cell according to the invention can lie in the semiconductor arrangement between a word line and a bit line which cross perpendicularly. The cell is then switched to the ON or OFF state by applying corresponding voltages to the word line and the bit line. This allows the state of the cell to be changed. The ON or OFF states correspond, for example, to the states with lower or higher electrical resistance.

As a rule, the electrodes are manufactured in such a way that they serve as a word or bit line. But it can also be that an (additional) layer of the upper and / or lower electrode is only applied in the area of the cell - in direct contact with the connection - ie not along the entire conductor track (word or bit line). This applies in particular to the via concept described below.

In the case of a "cross-point structure", the individual memory cells lie directly between intersecting conductor tracks and bit lines or word lines. To produce the individual cells, for example, the lower electrodes can be completely covered with the connection and the upper electrodes can be applied thereon The cross point cells, the size of which is defined solely by the width of the electrodes, are created at the intersection points, but it is also possible that the lower electrodes are not completely covered with the connection, but only at the points where the cross point cell This is possible either through the integration process, as will be described later, or through a direct structuring of the connection.

With this crosspoint structure, several levels of such memory cells can easily be provided in stacked memory cell fields. Each “level” of such a memory cell array then contains the associated upper and lower electrodes and the connection between them. It is possible for an electrode to be shared by two levels, for example the upper electrode of the first level can be used simultaneously serve as the lower electrode of the second level lying above it. The prerequisite is, of course, that this electrode consists of at least two suitable layers. Depending on requirements, an insulating layer can also be introduced between two levels. This enables very high integration densities to be achieved, the so-called “bit size” being of the order of “4F ² / n”, where n is the number of individual, stacked levels of memory cell arrays and “F” is the width (smallest possible structure of the ones used) Technology) means.

As an alternative to the cross point concept mentioned above, you can directly over the lower electrode - z. B. in an insulating layer - create contact holes and then form the connection in the contact hole directly on the lower electrode. The size of the cell is then defined by the size of the contact hole (so-called "via concept").

The examples for the integration concept are explained in the figures described below. Show it:

FIG. 1 a shows a via concept in which the size of the cell is precisely defined and is not dependent on the size (i.e. width) of the crossing conductor tracks;

1b shows an integration concept in which a cell size of approximately 4F ² can be achieved (cross-point concept);

1c shows a further integration concept with levels stacked one above the other and a bit size of approximately 4F ² / n; with n = number of levels

2 to 10 steps leading to the integration concept according to FIG. La.

11 to 22 steps leading to the integration concept according to FIG. 1b 23 to 27 steps which lead to an alternative crosspoint structure, the connection being produced only in the region of the crosspoint cell (and not along an entire electrode as in FIG. 14)

28 to 44 detailed representation of the method according to the invention

2 shows a silicon wafer in which the FEOL processes have been completed and the layers recorded there have been applied. Kl denotes a contact (contact hole filled with a conductor material, preferably made of tungsten), B the position 1 of the lower electrode (i.e. Ul according to the previous sketch), C a cover layer, I an insulating layer and M a conductor track. The conductor tracks M1 or M2 consist, for example, of layer 1 (= B, for example tantalum) and layer 2 (for example copper).

K2 denotes a contact, i. H. a contact hole that was filled with the same materials as the conductor track M2. This is done e.g. B. in the dual damascene process, in which first the layer 1 is simultaneously deposited in contact holes K2 and trenches and then the layer 2. The filled trenches then form the conductor tracks or

Electrodes. The layer 1 can also preferably consist of two or more layers, e.g. B. tantalum nitride and tantalum.

The cover layer C is preferably Si, TiNSi, SiON, SiO, SiC, SiN, SiCN and any combination of these layers or materials. D is either a combination of two superimposed contacts or a contact and a pad to make electrical contact with the substrate and / or the upper levels.

Even if the substrate was designated as a silicon wafer in FIG. 2, the substrate can also be one of the alternatives described earlier. An insulating layer, preferably silicon oxide, is then applied to such a substrate, as described in FIG. 2.

FIG. 3 shows how the contact holes L are opened in this insulating layer by means of photolithography and etching along the conductor tracks in order to arrive at the structure as shown in FIG. 3a. The cover layer under the contact holes is also opened so that, for example, the copper surface is free there. After the copper surface is exposed, the organic material can be applied to make the connection.

FIG. 4 shows how the organic material, in the special case TCNQ, is deposited on the substrate surface (FIG. 4 relates to vacuum evaporation). TCNQ can be deposited using a vacuum process, such as vapor deposition, or by a solution of TCNQ. The exact parameters of how the organic material is applied to the electrode are described in the general part of the application. When the organic material from the solvent is contacted with the electrode, the desired one is selectively formed only over the electrode

Connection. However, if the organic material is deposited on the electrode by means of vapor deposition, a Heat treatment is done to make the connection.

Fig. 5 shows how the compound is selectively formed in the contact holes either after the thermal treatment if the organic material is evaporated or immediately after the solution of the organic material is brought into contact with the electrode. The insulation layer does not react with TCNQ.

Figure 6 shows the substrate surface after rinsing with a solvent such as acetone. The solvent removes the excess organic material that has not formed a compound. For this purpose, the substrate surface can be rinsed by dipping, spraying or spinning (in the spin coater). The dimensions of the cell are clearly defined and neighboring cells are isolated from each other by the insulating layer.

7 shows how a further layer of insulating layer can be applied, and in particular how the - newly created - substrate surface can be structured for the production of the conductor tracks. This can be done using common lithographic techniques and subsequent etching. The structuring is preferably carried out using the conventional dual Cu damascene structuring. The trenches and contact holes are simultaneously filled with the materials of the corresponding layers and then ground. After the covering layer has been applied, the structure shown in FIG. 8 is obtained. Layer B is preferably made of tantalum nitride or a combination of tantalum and tantalum nitride. The webs M2 and M3 produced in FIG. 8 are perpendicular to one another. This gives the structure shown in FIG. 1 a (with M2 as the bottom electrode, M3 as the top electrode).

By applying a further layer of the insulating layer and repeating the steps explained in FIGS. 3 to 8, a structure is obtained which is shown in FIG. 9. The conductor track M3 can serve both as an upper electrode for the lower cell and as a lower electrode for the upper cell. M4 is the top electrode of the top cell and is perpendicular to M3. The structure shown in Fig. 9 is similar to Fig. Lc, with the

Difference that Fig. Lc shows a stack (structure with more than one cell level) based on the cross point concept and Fig. 9 shows a stack based on the via concept. The advantage of the latter structure is that the cell size is precisely defined and that the lateral isolation of the individual memory cells by means of the insulating layer prevents crosstalk from the neighboring cells. The disadvantage of this structure is that the bit size is more than 4F ² / n (lower integration density).

FIG. 10 shows how further processing should be carried out in order to apply an insulating layer between the first and second cell levels (ie M3 would then no longer serve as a common electrode for two cells). After the cover layer had been applied to the substrate according to FIG. 10, processing would take place according to FIGS. 3 to 8 in order to produce the next cell level. 11 to 19 show an integration concept for the semiconductor arrangement according to the present invention, the integration concept allowing a bit size of 4F ² / n.

11 shows a substrate similar to that in FIG. 2. FIGS. 2 and 11 make it clear that the substrate can be different. It is also possible to start with a substrate as shown in FIG. 2. Fig. 11a shows the top view of the structure shown in Fig. 11.

As already described in FIG. 2, the substrate can either be a silicon wafer or silicon, germanium, galium arsenide, galium nitride; any material that contains any compound of silicon, germanium or galium; be a polymer, ceramic, glass or metal.

As shown in Fig. Ϊ2, the cover layer C is opened by means of photolithography and etching in order to expose the conductor tracks. The connection is to be formed later via these conductor tracks.

13 shows the structure after the organic material X is deposited. The connection has not yet formed over the conductor track, since the organic material was evaporated using a vacuum process. Only after the substrate obtained in this way has been subjected to a temperature treatment does the connection form over the conductor track. Since the connection between the metal, e.g. B. copper, and the organic material is selectively formed only over the metal (Fig. 14), the opening in the cover layer can be larger than the width of the conductor track Ml and the overlay tolerances in photolithography should also be taken into account. The organic material can as described above, either by means of a vacuum process or by treatment with a solvent. If the organic material is applied to the substrate in the solvent, the structure shown in FIG. 13 is omitted.

The substrate is then rinsed with acetone, for example, to remove the excess organic material. The result of this step is described in FIG. 15. The trapezoidal structure of the connection is only schematic. After the connection has formed over the entire length of the conductor track, a layer of insulation is applied and ground, e.g. B. using CMP to get to the structure shown in Fig. 16a.

Then, according to FIG. 16b, contact holes for the contacts and trenches for the conductor tracks can be opened using common lithography and etching techniques. The conductor tracks which are now to be formed run transversely to the conductor tracks drawn as Ml in FIG. 11. The structuring can take place, for example, by means of dual Cu damascene structuring. In Fig. 16b, T1 is either a contact hole or a trench for a pad and L is a contact hole. T2 is a trench for a conductor track, which must show an expansion at least by the amount of the adjustment tolerances above the contact hole. 16c shows the top view of the structure shown in FIG. 16b. The hatched area shows the area where the formed connection is visible through the created trench T2.

As shown in FIG. 17, the trenches and holes can be filled and planarized using the dual Cu damascene technique. B here is position 1 of the upper electrode, the preferably consists of tantalum nitride or a combination of tantalum and tantalum nitride. The layer 2 of the upper electrode preferably forms copper. 17, the webs M1 and M2 are perpendicular to one another. The memory cells are thus defined wherever the paths intersect. D is either a combination of two contacts K or a contact and a pad, and is used to wire the different conductor tracks in different planes with the substrate -.

By applying a further cover layer and then repeating the steps shown in FIGS. 12 to 17, the structure shown in FIG. 18 is obtained. In this figure, the conductor track M2 (consisting for example of Ta and Cu or Ta, TaN and Cu) can serve both as an upper electrode for the lower cell and as a lower electrode for the upper cell. M3 is the top electrode of the top cell and is perpendicular to M2. The structure shown in FIG. 18 corresponds to FIG. 1c.

As FIG. 19 shows, a conductor track, such as M2, does not necessarily have to serve as an electrode for upper and lower cells. It is also possible that one does not form a connection on the conductor track M2, but instead applies a cover layer and then an insulating layer and first generates and contacts the conductor track plane M3. After applying a further cover layer, one can continue as shown in FIG. 12. In such a construction, each trace serves only as an upper or a lower electrode, i.e. H. no common electrodes for two superimposed cell levels.

The advantage of this concept is that a bit size of 4F ² / n can be achieved. The disadvantage, however, is that organic material is deposited over the entire conductor track so that the cells are not separated from one another by a dielectric. This means that the cells are separated from each other by dielectric only in one direction (e.g. x direction), but not in the y direction, ie along the conductor track.

The following embodiment shows an alternative to producing the integration concept according to FIGS. 11 to 18 or 19. In this embodiment, after the step shown in FIG. 15, an insulating layer is deposited and ground back to the level of the connection formed, which is the structure which is shown in Fig. 19a. Then the substrate is z. B. argon plasma, etched for about 20 s to 5 min. The connection is etched much faster than the insulation layer, so that a height difference is generated between the connection layer and the insulation, as shown in FIG. 20. This selective etching can also be carried out by wet chemical means, for example by treating the substrate with a mixture of ammonia and a solvent, such as, for example, dimethylformamide. The purpose of this step is to make room for another protective layer SC which is deposited on the connection. This protective layer is initially deposited over the entire area, as shown in FIG. 21 a, but after chemical-mechanical planarization (CMP), this layer is only retained over the conductor track M 1 or over the connection (FIG. 21 b). This layer preferably consists of the same material as the upper electrode or the layer 1 of the upper electrode if the upper electrode consists of several layers. However, it can also consist of one of the other electrode materials already mentioned. Then one another insulating layer applied to get to the structure as shown in Fig. 21c.

As shown in Fig. 22, using conventional lithography and etching techniques such. B. Dual Damascene technology, contact holes for the contacts and trenches for the conductor tracks or pads can be opened, as already described in Fig. 16b. After deposition and grinding of the electrode materials, the structure is obtained in a manner similar to that in FIG. 17, with the difference that in the present case (FIG. 22a), layer B is somewhat thicker over the connection. For further construction, a covering layer can be applied again and then proceed according to FIG. 15 and a construction such as e.g. B. in Fig. 18 and 22b. If the same material as the protective layer SC is used as for the layer B, the layer B in FIG. 22b is thicker than in FIG. 18. If different materials are used for the layers B and SC, two layers are obtained, as in FIG 22b. The structure shown in FIG. 22b corresponds to the structure of FIG. 18 with an additional SC layer.

The integration concept according to FIGS. 19a to 22b or 22c differs from the method shown in FIGS. 11a to 19 in that the protective layer is applied selectively to the connection. This has the particular advantage that the connection through this protective layer, for. B. is protected during the etching processes.

The following embodiment shows an alternative to producing an integration concept for the semiconductor arrangement according to the invention. In this embodiment, the first conductor track, which is also the represents the lower electrode for the cell according to the invention, an insulating layer is deposited, and only then is the connection formed (ie the step carried out in FIG. 16a takes place before the step carried out in FIGS. 13 and 14). This concept results in a reduction in process complexity.

23, which corresponds approximately to FIGS. 2 and 11a, a cover layer C (cap) is applied first, then an insulating layer, preferably made of silicon dioxide, in order to arrive at the structure as shown in FIG. 24. The trenches for the later conductor tracks are then opened in this insulating layer by means of photolithography and etching, as shown in FIG. 25. The cover layer under the trenches is also opened, so that the copper surface is free at the points where the (upper) trenches intersect with the (underneath) copper tracks.

The organic material is then deposited on the copper surface or the connection is formed on this substrate surface either by means of a vacuum process or by treatment with a solution of the organic material. If the deposition of the organic material is carried out by a vacuum technique, then one

Heat treatment take place, the z. B. can be carried out on a hot plate or in the oven, so that the connection is formed selectively over copper, as shown in Fig. 26, since the insulating layer does not react with the organic material.

The substrate surface is then rinsed with a solvent such as acetone. This can be done by diving, spraying or in the spin coater. Thus, the dimensions of the cell are clearly defined and neighboring cells are separated from one another by the insulating layer, as shown in FIG. 26. In this case, the connection is not made along the entire conductor tracks, but only locally at the crossing points.

The trenches are then filled with the electrode material or materials (if the electrode consists of more than one layer). After that, grinding can be done as an option. 27a and 27b show the two possibilities, i. H. with and without grinding (polishing) the upper electrode.

By applying a cover layer and then repeating the steps shown in FIGS. 24 to 27, a structure is obtained which essentially corresponds to the integration concept shown in FIG. 1c.

The advantage of this integration concept is that an exact definition of the cell dimensions of the memory cells is possible, so that crosstalk between the cells is largely prevented. This makes it possible to achieve an integration concept with the 4F ² / n bit size.

It should be noted that those disclosed in the description

Single layers can consist of several layers if it is desirable. The structures shown in FIGS. 28 to 36 explain in more detail how the individual layers can be built up.

Fig. 28 shows the substructure in which FEOL and MOL processes are carried out and are provided with contacts K1 at the end. The contacts Kl are preferably made of tungsten. The structure according to FIG. 28 is merely an alternative that can serve as a substrate for the desired structure with the memory cells according to the invention.

An insulating layer (Jl), preferably SiO, is applied to the substrate. If necessary, a Cu CMP stop layer S1 made of z. B. silicon carbide (SiC) and to protect them during the lithography process, another protective layer J2, which preferably again consists of SiO, are applied. The state after the layers J1, S1 and J2 have been deposited is shown in FIG.

The layers J1, S1 and J2 are structured by means of photolithography and RIE (reactive ion etching), as a result of which the contacts K1 are exposed, as shown in FIG. 30.

The two-layer lower electrode is applied using a standard Cu damascene process. The barrier layer B1, which consists of common barrier materials or a combination thereof, is first deposited. After the Cu Seed Layer has been applied, copper is deposited using an ECD (electrochemical deposition) process and, if necessary, subsequently thermally treated. This is followed by the chemical mechanical polishing of copper and of the barrier layer, a high selectivity between the copper and the barrier CMP being necessary. The CMP stop layer S1 is necessary in order to ensure a selective barrier CMP process. Otherwise the CMP process must be carried out unselectively. The structure thus obtained is shown in Fig. 31. A copper diffusion barrier S4, preferably made of HDP (high density plasma) Si and N, can be applied to the position of the conductor track (M1) generated in this way (not shown in FIGS. 31 and 32, but later in FIG. 41). There is then an insulating layer J3, which is preferably applied from SiO. If necessary, a CMP stop layer S2 made of z. B. SiC applied, and another protective layer J4 are deposited to protect them during the lithography process. The protective layer J4 is also made of SiO. The structure thus obtained is shown in Fig. 32.

In the following step, trenches are created that are at a 90 ° angle in this plane to the MI tracks in the previous plane. The trenches produced are shown in FIG. 33. The layers S2 and J3 and possibly J4 are structured by means of lithography and RIE (reactive ion etching), as a result of which the Ml tracks are partially exposed. The organic material is now deposited on the exposed areas of the Ml tracks by a method as described in the previous embodiments in order to achieve the connection according to the invention. The structure thus generated is shown in Fig. 34. It corresponds to FIG. 26, with the difference that more details of the layers are shown in FIG. 34. Then, for example, it can continue as in FIG. 27a. After applying the required number of levels according to Figs. 24-27a, a final (uppermost) conductor track M2 can be built up, for example by depositing suitable electrode materials over the entire surface. In this case, common materials, such as. B. Ti / AICu / TiN can be used. The structure obtained is in Fig. 35 displayed. The structuring is done here by an RIE process.

The last layer is a standard passivation layer P (e.g. SiO, SiN, SiON, SiC and any combination of these layers) deposited and the bond pads opened. The structure obtained is shown in Fig. 36.

The following figures show a variant of the concept described in FIGS. 11 to 19, a detailed layer structure being shown below.

An insulating layer J1, preferably made of SiO, is applied to the substrate. If necessary, a Cu-CMP stop layer S1, z. B. from SiC and for their protection during the lithography process protective layer J2, preferably again deposited from SiO. The structure thus obtained corresponds to the arrangement shown in FIG. 37. The dielectric is structured in order to achieve a structure as shown in FIG. 38.

The conductor track that forms the lower electrode is separated using a standard Cu damascene process. As described above, the lower electrode consists of at least two layers. In order to produce the conductor track Ml, the barrier layer B1 is separated from common ones

Barrier materials or their combination. After the application of the Cu seed layers, Cu is deposited using an ECD (Electrochemical Deposition) process and possibly subsequently thermally treated. This is followed by the chemical mechanical polishing of the copper layer and the barrier layer, with a high selectivity between the Copper or barrier CMP is necessary. The structure is shown in Fig. 39.

The organic material can now be selectively deposited on the conductor track, as already shown in Figs. 13-15 explained. The structure thus obtained is shown in Fig. 40. The organic material can be deposited as described in FIG. 13. Then a layer can be deposited, the z. B. consists of HDP (High Density Plasma) SiN. This layer serves as a copper diffusion barrier S4. A further insulating layer J3, which preferably consists of SiO, can now be deposited on this layer. If necessary, a CMP stop layer S3 can be deposited on the dielectric layer, which e.g. consists of SiC. To protect the S3 layer during the

A further protective layer J4, preferably also made of SiO, can be deposited in the lithography process steps. The structure thus obtained is shown in Fig. 41.

The next step is to generate the trenches for the conductor tracks to create the top electrodes. The structure after the etching is shown in FIG. 42. The trenches to be generated are at a 90 ° angle to the Ml tracks in the previous levels.

After the required number of levels has been applied, the final (uppermost) conductor track M2 can be constructed, as shown in FIG. 43. After structuring, a passivation layer P is deposited as the last layer in order to arrive at the structure shown in FIG. 44. The passivation layer P can be SiO, SiN, SiON or SiC as well as any combination of these layers. At the last level, the conductor track M1 is treated with the organic material arranged thereon after the CMP process, the connection between the organic material and the metal being produced selectively on the copper tracks. A final conductor track M2, which serves as an electrode, is constructed by depositing suitable electrode materials over the entire surface, as already described in FIG. 34.

Instead of silicon dioxide, a so-called “low k” material can also be used as the insulating layer I or J. Here, k means the dielectric constant. These are insulating layers which, because of the lower k values, allow a higher signal speed in comparison to silicon dioxide.

Examples of such materials are:

Polymers such as polyimides, polyquinolines, polyquinoxalines,

Polybenzoxazoles, polyimidazoles, aromatic polyethers., Polyarylenes including the commercial dielectric SILK, polynorbornenes; furthermore copolymers of these materials; porous silicon-containing materials, porous organic materials (porous polymers), porous inorganic-organic materials.

LIST OF REFERENCE NUMBERS

S substrate

K contact D cover layer

I insulating layer, which has several layers

IJ individual layers of the insulating layer I

M conductor track

T trench for a conductor track B lower layer of the lower electrode

Claims

claims

1. A semiconductor device comprising at least one nonvolatile memory cell comprising a first electrode, which consists of at least two layers and comprising an organic material, the organic material forms a connection with the ^'standing posture in direct contact the first electrode.

2. Semiconductor arrangement with a non-volatile memory cell according to claim 1, characterized in that the organic material comprises at least one of the following materials or compounds: sulfur, selenium or tellurium both in pure and in bound form, in particular as organo compounds of sulfur, selenium or tellurium and oligomers or polymers containing sulfur, selenium or tellurium, and / or one of the following compounds:

where Ri, R2, R ₃ , R ₄ , R5, Rβ _r Ri _r and Rs independently of one another have the following meaning: H, F, Cl, Br, I (iodine), alkyl, alkenyl, alkynyl, O-alkyl, 0 Alkenyl, O-alkynyl, S-alkyl, S-alkenyl, S-alkynyl, OH, SH, aryl, heteroaryl, O-aryl, S-aryl, NH-aryl, O-heteroaryl, S'-heteroaryl, CN, N0 ₂ , - (CF ₂ ) _n - ^ F ₃ , —CF ((CF ₂ ) _n CF ₃ ) ₂ , - Q— (CF ₂ ) _n - ^ F ₃ , - CF (CF ₃ ) ₂ , - ( CF ₃ ) 3 as well

n: n = 0 to 10

Q: -S - Rg, Rio, Rn, ₁₂ can be independent of one another: F, Cl, Br, I, CN, N0 ₂ Rι ₃ , R ₁₄ , R ₁₅ , Riβ, R ₁₇ can be independent of one another: H, F, Cl, Br, I, CN, N0 ₂

Xi and X ₂ can be independent of each other:

Y: O, S, Se and Zi and Z _{2 are} independently: CN, N0 ₂ .

3. Semiconductor arrangement with a non-volatile memory cell according to claim 1 or 2, characterized in that the organic material is an electron acceptor.

4. Semiconductor arrangement with a non-volatile memory cell according to claims 3, characterized in that the electron acceptor has electron-withdrawing atoms or groups which are selected from: -Cl, -F, -Br, -I, -CN, -CO-, -N0 ₂ ,

5. Semiconductor arrangement with a non-volatile memory cell according to one of claims 1 to 4, d a d u r c h g e k e n n z e i c h n e t that the organic material forms a charge transfer complex with the lower electrode.

6. Semiconductor arrangement with a non-volatile memory cell according to one of claims 1 to 5, d a d u r c h g e k e n n z e i c h n e t that that in contact with the organic material

The position of the first electrode contains copper or silver.

7. Semiconductor arrangement with a non-volatile memory cell according to one of the preceding claims, so that the organic material is present in a film thickness of between 30 and 1000 nm, preferably between 30 and 300 nm.

8. Semiconductor arrangement with a non-volatile memory cell according to one of the preceding claims, characterized in that the cell is scalable up to an area of 40 nm ² .

9. Semiconductor arrangement with a non-volatile memory cell according to one of the preceding claims, characterized in that the position of the first electrode which is not in contact with the organic material is titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), TiW, TaW, WN, WCN, IrO, RuO, SrRuO or a combination of these Layers and / or materials and is optionally additionally provided with a layer made of Si, TiNSi, SiON, SiO, SiC or SiCN.

10. Semiconductor arrangement with a non-volatile memory cell according to one of the preceding claims, characterized in that the second electrode made of aluminum, copper, AlCu, AlSiCu, silver (Ag), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride ( TaN), tungsten (W), TiW, TaW, WN, WCN, IrO, RuO, SrRuO or a combination of these layers and / or materials and optionally additionally with a layer of Si, TiNSi, SiON, SiO, SiC or SiCN is provided.

11. A semiconductor arrangement with a non-volatile memory cell according to one of the preceding claims, that the cell is switchable between an ON and an OFF state.

12. Semiconductor arrangement with a non-volatile memory cell according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the ON and OFF state has different electrical resistances.

13. A semiconductor device with a non-volatile memory cell according to claim 12, characterized in that the ratio between the ON and OFF states is more than 66.

14. A method for producing a non-volatile memory cell according to one of the preceding claims, characterized by the following steps:

Provision of a first electrode, which consists of at least two layers and one layer of the first electrode can form a connection with an organic material;

Contacting the electrode with an organic material to form a connection;

- And formation of a second electrode on the connection formed.

15. The method for producing a non-volatile memory cell according to claim 14, so that the organic material is evaporated under reduced pressure on the electrode.

16. The method for producing a non-volatile memory cell according to claim 14, which also means that the organic material is dissolved in a solvent when the first electrode is brought into contact.

17. The method according to any one of the preceding claims 14 to 16, that the organic material prior to formation of the second

Electrode is subjected to a thermal treatment.

18. The method according to any one of claims 14 to 17, characterized in that the excess organic material is rinsed with a solvent before forming the second electrode.

19. The method according to claim 15, so that the organic material is evaporated at a pressure between 0.00001 to 200 mbar.

20. The method according to any one of claims 14-19, that the contacting of the organic material takes place at a substrate temperature between -50 ° C and 150 ° C.

21. The method according to any one of claims 14, 15, 17 to 20, d a d u r c h g e k e n n e e i c h n e t that the organic material is mixed in the gas phase with a carrier gas.

22. The method according to any one of claims 14 to 21, so that the compound formed is treated with an aftertreatment reagent before the second electrode is attached.

23. The method according to claim 22, so that the post-treatment reagent is selected from the following group: amines, amides, ethers, ketones, carboxylic acids, thioethers, esters, aromatics, heteroaromatics, alcohols or compounds containing sulfur or selenium.

24. The method according to claim 23, characterized in that the smoldering compounds are selected from the group comprising: sulfur heterocycles, -SO- containing compounds and thiols.

25. The method according to any one of claims 22-24, characterized in that the aftertreatment reagent is selected from the group comprising: diethylamine, triethylamine, dimethylaniline, cyclohexylamine, diphenylamine, dimethylformamide, dimethylacetamide, dimethyl sulfoxide, acetone, diethyl ketone, diphenyl ketone, benzoic acid, phenyl ester, benzofuran - Methylpyrrolidone, gamma-butyrolactone, toluene, xylene, mesitylene, naphthalene, anthracene, imidazole, oxazole, benzimidazole, benzopxazole, quinoline, quinoxaline, fulvalenes, furan, pyrrole, thiophene or diphenyl sulfide.

26. The method according to any one of claims 22 to 25, so that the aftertreatment reagent is in a solution.

27. The method according to any one of claims 22-25, so that the aftertreatment reagent is present as a vapor.

28. The method according to any one of claims 22-27, so that the after-treatment time is between 15 seconds and 15 minutes.

29. The method according to any one of claims 22 to 28, so that the aftertreatment takes place at a temperature of -30 ° C to 150 ° C.

30. The method according to any one of claims 14-21, characterized in that when the first electrode is brought into contact with the organic material, the aftertreatment reagent according to one of claims 22-25 is added to the solution containing the organic material or to the vapor containing the organic material.

31. Semiconductor arrangement according to one of claims 1-13, comprising the aftertreatment reagent according to one of claims 22-25, and / or a reaction product of the aftertreatment reagent with the organic material and / or the electrode material.

32. Semiconductor arrangement with a bit line and a word line having a non-volatile memory cell according to one of claims 1-13 and / or 31, the non-volatile memory cells being located directly between intersecting bit or word lines.

33. The semiconductor device as claimed in claim 32, so that the non-volatile memory cells are present in a plurality of layers.

34. Semiconductor arrangement according to claim 32 or 33, producible by the following steps in any order:

- Forming at least one first conductor track on a substrate, which serves as the first electrode for the memory cell according to one of claims 1-13 or 31;

- depositing an insulating layer; Structuring of the insulating layer so that trenches for at least one conductor track are structured in the insulating layer transversely to the first conductor tracks applied;

- depositing an organic material according to one of claims 2 to 5; - Deposition of at least one second electrode, which is arranged transversely to the first applied conductor track and serves as a second electrode for the memory cell.

35. Semiconductor arrangement according to claim 34, characterized in that the deposition of the insulating layer takes place after the deposition of the organic material.

36. The semiconductor arrangement according to claim 33, which can be produced by the following steps in this order:

- Forming at least a first conductor track on a substrate; - depositing an insulating layer;

- structuring the contact holes over the first electrode;

Depositing an organic material according to any one of claims 2-5 into the contact holes via the first electrode; - depositing a second insulating layer;

Structuring of the second insulating layer so that trenches for at least one second conductor track, which runs transversely to the first applied conductor tracks and covers the contact holes in the cell field, are structured in the insulating layer;

- Deposition of at least one second conductor track, which serves as a second electrode for the memory cell according to one of claims 1-13 and / or 31.

37. The semiconductor device as claimed in one of claims 32 to 34, that it is produced by a Cu damascene technique.

38. A method for producing a semiconductor arrangement according to any one of claims 32-37, g e k e n n z e i c h n e t d u r c h

- Forming at least one first conductor track on a substrate, which serves as the first electrode for the memory cell according to one of claims 1-13 and / or 31; - the deposition of an insulating layer;

structuring of the insulating layer so that trenches for at least one conductor track are structured in the insulating layer transversely to the first conductor tracks applied;

- depositing an organic material according to any one of claims 2-5;

- The deposition of at least one second electrode, which is arranged transversely to the first applied conductor track and as second electrode for the memory cell according to one of claims 1-13 and / or 31 is used.

39. The method of claim 38, so that the insulating layer is deposited after the organic material has been deposited.

40. A method for producing a semiconductor arrangement according to any one of claims 32-37, g e k e n n z e i c h n e t d u r c h

- The application of at least a first conductor track on a substrate;

- the deposition of an insulating layer; - structuring the contact holes over the first electrode;

- depositing an organic material according to any one of claims 2-5 into the contact holes via the first electrode; - depositing a second insulating layer;

the structuring of the second insulating layer, so that trenches for at least one second conductor track, which runs transversely to the first applied conductor tracks and covers the contact holes in the cell field, are structured in the insulating layer;

- The deposition of at least one second conductor track, which serves as a second electrode for the memory cell according to one of claims 1-13 or and / or 31.

41. The method according to any one of claims 38-40, characterized in that after the deposition of the organic material on the organic material, a protective layer is deposited before further processing.

42. Memory device containing a plurality of the non-volatile memory cells according to one of claims 1-13 and / or 31.

43. Memory device according to claim 39, so that a plurality of memory cells is arranged in one plane.

44. Memory device according to claim 42 or 43, so that a plurality of memory cells according to one of claims 1 to 13 and / or 31 are arranged in the XY and in the XZ or YZ plane.