Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N7/00—Television systems
  • H04N7/015—High-definition television systems
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
  • G09G5/006—Details of the interface to the display terminal
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L65/00—Network arrangements, protocols or services for supporting real-time applications in data packet communication
  • H04L65/1066—Session management
  • H04L65/1101—Session protocols
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L65/00—Network arrangements, protocols or services for supporting real-time applications in data packet communication
  • H04L65/60—Network streaming of media packets
  • H04L65/70—Media network packetisation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
  • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
  • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
  • H04N21/238—Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams
  • H04N21/2381—Adapting the multiplex stream to a specific network, e.g. an Internet Protocol [IP] network
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
  • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
  • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
  • H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
  • H04N21/4363—Adapting the video stream to a specific local network, e.g. a Bluetooth® network
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
  • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
  • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
  • H04N21/438—Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
  • H04N21/4381—Recovering the multiplex stream from a specific network, e.g. recovering MPEG packets from ATM cells
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N5/00—Details of television systems
  • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04W—WIRELESS COMMUNICATION NETWORKS
  • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
  • H04W88/02—Terminal devices

Definitions

• the present invention relates generally to wireless multimedia systems.
• DVI Digital Visual Interface
• HDMI High Definition Multi-media Interface
• a projector on the ceiling or to mount a plasma display or liquid crystal high definition (HD) television display on a wall, out of the way and capable of receiving multimedia data for display without the need for wires, since as understood herein among other things, while power lines exist in ceilings and
• the present invention recognizes the need for a very short range, preferably directional, high bandwidth wireless link that is particularly suited for the short range wireless communication of uncompressed multimedia, particularly the rather voluminous genre of multimedia known as HD video. In any case, as mentioned above for the DVI standard, wireless transmission is not envisioned.
• a DVI receiver chip can receive 1 clock line and 3-data physical signaling streams representing DVI clock, data and control functions and demultiplex it to baseband video of 24 bits video and 7 control lines.
• the baseband video can be fed into a processor that re-multiplexes the signals and produces both "in-phase”, I and "quadrature”, Q, signals that can be up converted (modulated) by a radio and wirelessly transmitted to a DVI
• the DVI transmitter chip can perform the inverse of the above process to produce a clock and 3-data physical signaling stream that is sent to drive a display.
• the above-discussed system while useful, can be further simplified. Accordingly, the solution herein is provided.
• a system includes a transition minimized differential signaling (TMDS) receiver on a first substrate, with the TMDS receiver being configured for receiving digital visual interface (DVI) or high definition multi-media interface (HDMI) data.
• TMDS transition minimized differential signaling
• a transmitter processor is on the first substrate and receives data from the TMDS receiver.
• the transmitter processor may be implemented a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).
• a wireless transmitter on the first substrate receives data from the transmitter processor for wireless transmission thereof.
• the system also includes a wireless receiver configured to receive data from the wireless transmitter, and a receiver processor receiving data from the wireless receiver. Like the transmitter processor, the receiver processor may be implemented by an FPGA or ASIC.
• a TMDS transmitter is configured for receiving data from the receiver processor and outputting DVI input signals to a display.
• the preferred system thus does not reduce data to a baseband video signal during processing.
• the preferred transmitter processor can include phase-locked loop circuitry for clock stabilization, de-jitter circuitry for input data stabilization, and it can apply forward error correction prior to differential encoding of data.
• the transmitter processor may output I and
• a method for wireless transmission of video data includes receiving the video data at a physical signaling stream receiver, rendering the data into a physical signaling stream, and rendering the physical signaling stream into data suitable for modulation by a radio transmitter.
• the rendering acts are undertaken without rendering the data into baseband video at any time, and then the data is wirelessly transmitted.
• the method includes receiving the data and rendering demodulated data from the received data.
• physical signaling stream data is rendered from the demodulated data, and these rendering acts likewise are undertaken without rendering the data into baseband video at any time.
• the data is output to a display device using a physical signaling stream transmitter.
• a digital video transmitter includes a transmitter processor configured to receive a physical signaling stream representing digital video data and based thereon, without rendering baseband information representing the digital video data, outputting a quadrature signal suitable for processing by a wireless transmitter.
• a digital video receiver includes a receiver processor configured to receive a demodulated quadrature signal and based thereon, without rendering baseband information representing the digital video data, outputting a physical signaling stream representing digital video data.
• Figure 1 is a block diagram showing the inventive system
• Figure 2 is a flow chart of the present transmitter logic
• Figure 3 is a flow chart of the present receiver logic.
• a system is shown, generally designated 10, which includes a source 12 of Digital Visual Interface (DVI) or HDMI data that may be a set-top box, laptop computer or other multimedia computer or server. Or, it can be a satellite, broadcast, or cable receiver, or it can be a DVD player or other multimedia source.
• the data is sent to a physical signaling receiver 14 of a transmitter board 16 that preferably contains all of its components on a single substrate.
• the receiver 14 is a transition minimized differential signaling (TMDS) receiver.
• the output of the receiver 14 is sent to a transmitter processor 18 that can be implemented by an application specific integrated circuit (ASIC) or field programmable gate array (FPGA).
• ASIC application specific integrated circuit
• FPGA field programmable gate array
• the processor 18 processes the data in accordance with the disclosure below for wireless transmission by a wireless transmitter 20 over a transmitting antenna 22.
• the transmitter processor 18 can, among other things, render the input data into I and Q quadrature signals such as might be required to support QPSK, DQPSK, or similar modulation by the wireless transmitter 20. Additional control signals for the display may also be multiplexed within the video data stream. Also, error correction may be
• the multimedia data is wirelessly transmitted over a wireless linlc to a receiver antemia 24, which sends the data to a wireless receiver 26 of a receiver board 27 that preferably contains all of its components on a single substrate.
• the link carries a frequency which is sufficiently high that the signal on the link substantially cannot be received outside the room.
• multimedia may be transmitted in an uncompressed form on the link such that so much data is transmitted each second that bootlegging the content is essentially untenable, although some data compression less preferably may be implemented.
• the data may also be transmitted in compressed form if desired.
• the transmitter 20 and receiver 26 (and, hence, the linlc there between) preferably operate at a fixed (unvarying, single-only) frequency of approximately sixty Gigahertz (60GHz), and more preferably in the range of 59GHz-64GHz, and the link has a data rate, preferably fixed, of at least two Giga bits per second (2.0 Gbps).
• the data rate may be 2.2 Gbps
• the linlc may have a data rate of approximately 2.5 Gbps.
• the link may have a fixed bandwidth of two and half Gigahertz (2.5GHz).
• the data is modulated at approximately 30GHz by a 30.125GHz modulator and up converted by a subharmonic mixer to a frequency of approximately 60GHz for transmission over the link 30.
• a 30.125GHz modulator and up converted by a subharmonic mixer to a frequency of approximately 60GHz for transmission over the link 30.
• the wireless receiver 26 includes circuitry that is complementary to the wireless transmitter 20, namely, a downconverter, a 60 GHz demodulator, and a decoder.
• I and Q data from the wireless receiver 26 is sent to a receiver processor 28 for error correction and for recovering the 3-data physical signaling stream from the I and Q data.
• the receiver processor 28 may be implemented by, e.g., an ASIC or FPGA.
• the output of the receiver processor 28 is sent to a TMDS transmitter 30, which sends the data over a cable or other wire to a display device 32 that may be part of a media player such as a DVD player or TV or other player.
• the display device 32 decrypts the multimedia data (if encrypted) and presents the data on a display such as a cathode ray tube (CRT), liquid crystal display (LCD), plasma display panel (PDP), or TFT, or projector with screen, etc.
• CTR cathode ray tube
• LCD liquid crystal display
• PDP plasma display panel
• TFT projector with screen, etc.
• the system 10 does not derive or render twenty four lines of baseband video and control signals from the 3-data and 1-clock TMDS stream received from the source 12, nor does it render baseband video from the I and Q signals received over the wireless linlc from the transmitter 16 prior to outputting data to the display device 32.
• the components (14 and 18) of the transmitter 16 may be contained on a single chip, or on separate substrates. Indeed, the transmitter 16 may be integrated into the source 12. Likewise, the components (28 and 30) of the wireless
• FIG. 1 illustrates the operation of the transmitter 16 and receiver 27, respectively.
• DVI data is received from the source 12 and rendered into a 3-data physical signaling stream by the TMDS receiver 14 at block 36.
• the data is sent to the transmitter processor 18 which, at block 38, uses phase-locked loop (PLL) principles known in the art to stabilize the signal clock, and which also applies de-jitter to the signal in accordance with de-jitter principles known in the art.
• PLL phase-locked loop
• the stabilized 3-data and 1-clock physical streams are multiplexed into 2 streams.
• the transmitter processor 18 can, at block 40, apply forward error correction (using, e.g., Reed-Solomon principles), randomize the data, and differentially encode the data.
• Block 42 indicates that importantly, the processor 42 renders the 3-data physical signaling stream into I and Q quadrature modulation input data, which is input to the radio transmitter 20.
• the radio transmitter 20 up converts the data and wirelessly transmits it in accordance with wireless transmission principles known in the art. Now referring to Figure 3, at block 46 the data is received by the wireless receiver 26 and downconverted to I and Q data.
• the I and Q data is sent to the receiver processor 28, which, at block 48, demultiplexes and renders it into 3-data and 1-clock physical signaling stream (and which can undertake conventional functions if desired, such as decryption, etc.).
• the 3-data physical signaling stream is sent to the TMDS transmitter 30, which sends it to the display device 32 for display at block 50. While the particular METHOD AND SYSTEM FOR WIRELESS DIGITAL

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• Engineering & Computer Science (AREA)
• Multimedia (AREA)
• Signal Processing (AREA)
• Computer Networks & Wireless Communication (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• General Business, Economics & Management (AREA)
• Business, Economics & Management (AREA)
• Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
• Compression Or Coding Systems Of Tv Signals (AREA)
• Television Systems (AREA)
• Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
• Mobile Radio Communication Systems (AREA)

Applications Claiming Priority (3)

Publications (2)

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Family Applications (1)

Country Status (6)

Families Citing this family (52)

Citations (8)

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• 2004
  • 2004-03-01 US US10/790,162 patent/US7020121B2/en active Active
  • 2004-10-14 CN CN2004800338135A patent/CN1939072B/zh not_active Expired - Fee Related
  • 2004-10-14 WO PCT/US2004/034028 patent/WO2005053302A2/en not_active Application Discontinuation
  • 2004-10-14 KR KR1020067009514A patent/KR101083560B1/ko active IP Right Grant
  • 2004-10-14 JP JP2006541162A patent/JP4480725B2/ja not_active Expired - Fee Related
  • 2004-10-14 EP EP04795218A patent/EP1685700A4/en not_active Ceased
• 2005
  • 2005-10-03 US US11/242,497 patent/US7965663B2/en not_active Expired - Fee Related

Patent Citations (8)

Non-Patent Citations (1)

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