EP1672695A1 - Semiconductor device and process for manufacturing the same - Google Patents

Semiconductor device and process for manufacturing the same Download PDF

Info

Publication number
EP1672695A1
EP1672695A1 EP04788124A EP04788124A EP1672695A1 EP 1672695 A1 EP1672695 A1 EP 1672695A1 EP 04788124 A EP04788124 A EP 04788124A EP 04788124 A EP04788124 A EP 04788124A EP 1672695 A1 EP1672695 A1 EP 1672695A1
Authority
EP
European Patent Office
Prior art keywords
thinned portion
wiring substrate
electrodes
semiconductor substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP04788124A
Other languages
German (de)
French (fr)
Other versions
EP1672695A4 (en
EP1672695B1 (en
Inventor
Hiroya Kobayashi
Masaharu Muramatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hamamatsu Photonics KK
Original Assignee
Hamamatsu Photonics KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hamamatsu Photonics KK filed Critical Hamamatsu Photonics KK
Publication of EP1672695A1 publication Critical patent/EP1672695A1/en
Publication of EP1672695A4 publication Critical patent/EP1672695A4/en
Application granted granted Critical
Publication of EP1672695B1 publication Critical patent/EP1672695B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/90Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14636Interconnect structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/1464Back illuminated imager structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/148Charge coupled imagers
    • H01L27/14806Structural or functional details thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83194Lateral distribution of the layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01058Cerium [Ce]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30105Capacitance

Definitions

  • This invention concerns a semiconductor device and a method for manufacturing the same, and particularly concerns a back-illuminated semiconductor device and a method for manufacturing the same.
  • a so-called back-illuminated semiconductor photodetecting device has been known conventionally as a semiconductor device.
  • This type of semiconductor device has a semiconductor substrate and has a photodetecting unit on one surface of the semiconductor substrate. A portion of the semiconductor substrate on the side opposite the photodetecting unit is trimmed to form a recessed portion in the semiconductor substrate. A thinned portion is thus provided at the portion of the semiconductor substrate at which the photodetecting unit is disposed. This thinned portion is provided to accommodate ultraviolet rays, soft X-rays, electronic beams, and other energy rays that will be absorbed and cannot be detected at high sensitivity by a thick semiconductor substrate. At this thinned portion, light that is made incident on the surface at the recessed portion side of the semiconductor substrate is detected by the photodetecting unit.
  • a back-illuminated semiconductor device there is a semiconductor device that has a BT-CCD (back-thinned CCD).
  • the BT-CCD is used as a detecting unit of a semiconductor inspecting device.
  • An example of a conventional semiconductor device having a BT-CCD is described in Patent Document 1.
  • Fig. 7 is a sectional view of an arrangement of the semiconductor device described in Patent Document 1.
  • a P-type silicon layer 104 which is a semiconductor substrate having a CCD 103 on a surface that opposes a wiring substrate 102, is mounted via metal bumps 105 onto wiring substrate 102, which is fixed to a bottom portion of the interior of a package 101.
  • Each wiring 106 on wiring substrate 102 is connected at one end to a metal bump 105 and has a bonding pad (not shown) for externally taking out detected signals at the other end, and each bonding pad is electrically connected by a bonding wire 107 to a lead terminal (not shown) of package 101.
  • a gap between wiring substrate 102 and P-type silicon layer 104 is filled with an underfill resin 108 for reinforcing the bonding strengths of metal bumps 105.
  • Patent Document 1 Japanese Published Unexamined Patent Application No. Hei 6-196680
  • the thinned portion may crack due to the stress that arises due to a thermal expansion coefficient difference between the underfill resin and the semiconductor substrate in the process of heating or cooling to cure the underfill resin. Even if cracking does not occur, the thinned portion may become distorted by being pulled by the contraction of the underfill resin. Such distortion of the thinned portion of the semiconductor substrate may bring about adverse effects on focusing with respect to the photodetecting unit and uniformity and stability of sensitivity of the photodetecting unit during use of the semiconductor device.
  • This invention was made in view of the above issue and an object thereof is to provide a semiconductor device, with which the distortion and cracking of a thinned portion of a semiconductor substrate are prevented to enable high precision focusing with respect to a photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit to be maintained.
  • this semiconductor device comprises: a semiconductor substrate, having a photodetecting unit formed on one surface, a thinned portion formed by etching a region, opposing the photodetecting unit, of another surface, and first electrodes disposed on the one surface at an outer edge of the thinned portion and electrically connected to the photodetecting unit; a wiring substrate, disposed to oppose the one surface side of the semiconductor substrate and having second electrodes connected via conductive bumps to the first electrodes; and a resin, filling a gap between the wiring substrate and the outer edge of the thinned portion to reinforce the strengths of bonding of the respective first electrodes and the respective second electrodes with the conductive bumps; and wherein the resin is a resin sheet that is formed in advance so as to surround a periphery of a gap between the thinned portion and the wiring substrate except for portions of the periphery.
  • the resin fills the gap between the wiring substrate and the outer edge of the thinned portion.
  • the strength of bonding of the conductive bumps with the first electrodes that are disposed at the outer edge of the thinned portion and the strength of bonding of the conductive bumps with the second electrodes of the wiring substrate are thus reinforced.
  • the resin does not fill a gap between the wiring substrate and the thinned portion of the semiconductor substrate, even when stress due to the thermal expansion coefficient difference between the resin and the semiconductor substrate arises during heating or cooling in the process of curing the resin, etc., the influence of the stress on the thinned portion will be small and distortion and cracking of the thinned portion will be prevented.
  • high precision focusing is enabled with respect to the photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit can be exhibited during use.
  • the resin sheet which is formed in advance to a desired shape, that is, a shape that surrounds the periphery of the gap between the thinned portion and the wiring substrate except for portions of the periphery, is used.
  • a desired shape that is, a shape that surrounds the periphery of the gap between the thinned portion and the wiring substrate except for portions of the periphery.
  • a sealed space may form when the gap between the thinned portion and the wiring substrate is completely surrounded by the resin.
  • the thinned portion may become distorted due to expansion or contraction of the air inside the sealed space during heating or cooling in the process of curing the resin, etc.
  • the arrangement wherein the resin surrounds the periphery of the gap except at portions of the periphery is provided to prevent the gap from becoming sealed. Moreover, by use of the resin sheet formed in advance, this arrangement can also be realized readily and reliably.
  • the photodetecting unit may have a plurality of pixels that are arrayed one-dimensionally or two-dimensionally.
  • This invention's semiconductor device is especially useful in this case because uniformity and stability of high sensitivity is required among the plurality of pixels.
  • a semiconductor device manufacturing method of this invention comprises the steps of: preparing a semiconductor substrate, having a photodetecting unit formed on one surface, a thinned portion formed by etching a region, opposing the photodetecting unit, of another surface, and first electrodes disposed on the above-mentioned one surface at an outer edge of the thinned portion and electrically connected to the photodetecting unit; preparing a wiring substrate, disposed to oppose the above-mentioned one surface side of the semiconductor substrate and having second electrodes connected via conductive bumps to the first electrodes; adhering a solid resin sheet onto a predetermined region on the above-mentioned other surface of the semiconductor substrate; and thermocompression bonding the semiconductor substrate, with the resin sheet, to the wiring substrate; and the predetermined region is
  • a semiconductor device can be realized with which the distortion and cracking of a thinned portion of a semiconductor substrate are prevented to enable high precision focusing with respect to a photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit to be maintained.
  • Fig. 1 is a sectional view of an embodiment of this invention's semiconductor device.
  • a semiconductor device 1 has a semiconductor substrate 10, a wiring substrate 20, conductive bumps 30, and a resin 32.
  • Semiconductor substrate 10 is a BT-CCD (back-thinned CCD) and has a CCD 12 formed as a photodetecting unit on a portion of a top layer of its front surface S1 side.
  • Semiconductor substrate 10 includes, for example, a silicon P + layer, a P-type epitaxial layer formed above the silicon P + layer, and an unillustrated set of transfer electrodes, formed on the epitaxial layer and to which driving signals are provided.
  • CCD 12 has a plurality of pixels that are arrayed two-dimensionally.
  • a thinned portion 14 is formed by thinning by etching a region, opposing CCD 12, of a back surface S2.
  • the etched portion has a truncated rectangular pyramidal profile.
  • a surface of thinned portion 14 at the etched side is a flat and rectangular, light-incident surface S3, and this light-incident surface S3 is formed to be substantially the same in size as CCD 12.
  • Semiconductor substrate 10 as a whole has a rectangular shape in plan view.
  • Semiconductor substrate 10 is, for example, approximately 15 to 40 ⁇ m thick at thinned portion 14 and approximately 300 to 600 ⁇ m thick at an outer edge 15 of thinned portion 14.
  • Outer edge 15 of thinned portion 14 refers to a portion of semiconductor substrate at the periphery of thinned portion 14 and is thicker than thinned portion 14.
  • Electrodes 16 are formed on front surface S1 of outer edge 15. These electrodes 16 are electrically connected to the set of transfer electrodes of CCD 12 by wirings that are omitted from illustration.
  • Accumulation layer 18 is of the same conductive type as semiconductor substrate 10, however, is higher in impurity concentration than semiconductor substrate 10.
  • Wiring substrate 10 is mounted onto wiring substrate 20 by flip-chip bonding.
  • Wiring substrate 20 is thus positioned to oppose the front surface S1 side of semiconductor substrate 10.
  • Electrodes 22 (second electrodes) are formed at positions of wiring substrate 20 that oppose electrodes 16 of semiconductor substrate 10, and these electrodes 22 are connected via conductive bumps 30 to electrodes 16.
  • Lead terminals 24, electrodes 22, conductive bumps 30, and electrodes 16 are thus connected to the CCD transfer electrodes and CCD drive signals are input into lead terminals 24.
  • An output of an amplifier that outputs a CCD read signal is taken out from a lead terminal 24 via an electrode 16, a conductive bump 30, and an electrode 22.
  • Wiring substrate 20 is formed, for example, of a multilayer ceramic substrate.
  • An upper surface S4 (surface opposing semiconductor substrate 10) of wiring substrate 20 has a wider area than semiconductor substrate 10 and a region that does not oppose semiconductor substrate exists at an edge of upper surface S4.
  • Lead terminals 24 are disposed at a bottom surface S5 (surface at the opposite side of upper surface S4) of wiring substrate 20. Lead terminals 24 are connected to internal wirings (not shown) of wiring substrate 20.
  • Resin 32 is a resin sheet, and as this sheet, a resin sheet, with which, for example, an epoxy-based resin, a urethane-based resin, a silicone-based resin, an acrylic-based resin, or a composite of such resins is formed to a sheet form, may be used.
  • Fig. 2 is a plan view of wiring substrate 20 as viewed from its upper surface S4 side.
  • broken lines L1 and L2 indicate outlines of semiconductor substrate 10 and thinned portion 14, respectively.
  • the sectional view along line I-I of this figure corresponds to being Fig. 1.
  • resin 32 surrounds a periphery of a gap between thinned portion 14 of semiconductor substrate 10 and wiring substrate 20, it does not surround the entire periphery but surrounds the periphery with the exception of portions of the periphery.
  • resin 32 is disposed while leaving regions respectively extending from the four corners of a region of wiring substrate 20 that opposes the thinned portion (the rectangular region surrounded by broken lines L2) to the outer side of a region opposing semiconductor substrate 10.
  • Communicating portions 34 that put the gap between thinned portion 14 and wiring substrate 20 in communication with the exterior of semiconductor device 1 are thus defined at the gap between semiconductor substrate 10 and wiring substrate 20.
  • Chip resistors 28 are disposed on upper surface S4 of wiring substrate 20. Chip resistors 28 are aligned one-dimensionally in the left/right direction of the figure, respectively at an upper portion and a lower portion in the figure in the region of wiring substrate 20 that opposes thinned portion 14.
  • Resin 32 fills the gap between outer edge 15 of thinned portion 14 and wiring substrate 20.
  • the strength of bonding of electrodes 16, disposed on outer edge 15 of thinned portion 14, with conductive bumps 30 and the strength of bonding of conductive bumps 30 with electrodes 22 of wiring substrate 20 are thereby reinforced.
  • the gap between thinned portion 14 of semiconductor substrate 10 and wiring substrate 20 is not filled with resin 32, even if stress due to the thermal expansion coefficient difference between resin 32 and semiconductor substrate 10 arises between the two during heating or cooling in the process of curing resin 32, etc., the influence of the stress on thinned portion 14 will be low and distortion and cracking of thinned portion 14 are prevented.
  • semiconductor device 1 high precision focusing with respect to CCD 12 is enabled and uniformity and stability of the high sensitivity of CCD 12 can be exhibited during use. Also, because cracking of thinned portion 14 is prevented, the manufacturing yield of semiconductor device 1 is improved.
  • resin 32 a resin sheet that has been formed in advance to a desired shape, that is, a shape that surrounds the periphery of the gap between thinned portion 14 and the wiring substrate 20 except for portions of the periphery, is used.
  • the arrangement, wherein resin 32 fills the gap at which conductive bumps 30 exist, that is, the gap between the outer edge of thinned portion 14 and wiring substrate 20 while the gap between thinned portion 14 and wiring substrate 20 is left unfilled, can thus be realized readily and reliably.
  • a sealed space may form when the gap between thinned portion 14 and wiring substrate 20 is completely surrounded by the resin 32.
  • thinned portion 14 may become distorted due to expansion or contraction of the air inside the sealed space during heating or cooling in the process of curing the resin, etc.
  • the arrangement, wherein resin 32 surrounds the periphery of the gap except at portions of the periphery, is provided to prevent the gap from becoming sealed.
  • this arrangement can also be realized readily and reliably.
  • Semiconductor substrate 10 is provided with accumulation layer 18.
  • the accumulation state of semiconductor substrate 10 is thereby maintained. Thereby the uniformity and stability of the sensitivity of CCD 12 with respect to short wavelength light can be improved further.
  • semiconductor device 1 because semiconductor substrate 10 is mounted onto wiring substrate 20 via conductive bumps 30, there is no need to perform wire bonding of semiconductor substrate 10 with wiring substrate 20. Furthermore, because wiring substrate 20 is provided with lead terminals 24, there is no need to provide a package besides wiring substrate 20 and thus, with semiconductor device 1, there is no need to perform wire bonding of wiring substrate 20 with lead terminals of a package. Thus with semiconductor device 1, because all of the wirings can be arranged without using wire bonding, even if a large area is to be realized, the above-mentioned problems of increased resistance, occurrence of crosstalk, and forming of capacitance do not occur. Semiconductor device 1 can thus meet the demands of both large area and high-speed response.
  • Fig. 3 is a sectional view for describing an example of a method for manufacturing semiconductor device 1 of Fig. 1.
  • a solid transfer sheet resin sheet
  • this solid transfer sheet is adhered onto a predetermined region of front surface S 1 of semiconductor substrate 10.
  • This predetermined region is a region that surrounds the periphery of thinned portion 14 except for portions of the periphery.
  • thermocompression bonding semiconductor substrate 10 onto wiring substrate 20 semiconductor device 1, shown in Fig. 1, is obtained. Since bumps 30 pierce the solid transfer sheet in the thermocompression bonding process, there is no need to form openings, etc., in advance at portions of the solid transfer sheet corresponding to bumps 30.
  • Fig. 4 is a plan view of an arrangement example of wiring substrate 20 of Fig. 1.
  • Wiring substrate 20 of this arrangement example is a multilayer ceramic substrate.
  • This wiring substrate 20 has a substantially square shape of 58.420mm square in plan view.
  • the plurality of chip resistors 28 are disposed in the rectangular region (indicated by broken lines L2) of wiring substrate 20 that opposes thinned portion 14. In this region, chip resistors 28 are aligned one-dimensionally in the left/right direction of the figure (in the direction of the long sides of the rectangle) in two columns at each of an upper portion and a lower portion in the figure.
  • the plurality of electrodes 22 are formed in a region at the outer side of the region. Electrodes 22 are aligned along each of the four sides of the rectangle, forming three columns along each of the long sides and forming two columns along each of the short sides. The diameter of each electrode 22 is 0.080mm.
  • Fig. 5 is a sectional view of an arrangement of internal wirings of wiring substrate 20 of the arrangement example of Fig. 4.
  • Internal wirings 60 include signal output wirings 60a and 60b, clock supplying wirings 60c and 60d, and DC bias (ground) supplying wirings 60e.
  • Each internal wiring 60 electrically connects an electrode 22, a lead terminal 24, and a chip resistor 28 to each other.
  • the arrangement of internal wirings 60 shall now be described in more detail using Fig. 6.
  • lead terminals 24 are indicated overlappingly on a plan view of wiring substrate 20 for the sake of description.
  • clock supplying wirings 60c and 60d and DC bias (clock) supplying wiring 60e are formed outside the region.
  • This invention can be applied to a semiconductor device and a method of manufacturing the same and particularly to a back-illuminated semiconductor device and a method for manufacturing the same.

Abstract

With this semiconductor device, the distortion and cracking of a thinned portion of a semiconductor substrate are prevented to enable high precision focusing with respect to a photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit to be maintained. A semiconductor device 1 has a semiconductor substrate 10, a wiring substrate 20, conductive bumps 30, and a resin 32. A CCD 12 and a thinned portion 14 are formed on semiconductor substrate 10. Electrodes 16 of semiconductor substrate 10 are connected via conductive bumps 30 to electrodes 22 of wiring substrate 20. Insulating resin 32 fills a gap between outer edge 15 of thinned portion 14 and wiring substrate 20 to reinforce the bonding strengths of conductive bumps 30. This resin 32 is a resin sheet that has been formed in advance so as to surround a periphery of a gap between thinned portion 14 and wiring substrate 20 except for portions of the periphery.

Description

    Technical Field
  • This invention concerns a semiconductor device and a method for manufacturing the same, and particularly concerns a back-illuminated semiconductor device and a method for manufacturing the same.
  • Background Art
  • A so-called back-illuminated semiconductor photodetecting device has been known conventionally as a semiconductor device. This type of semiconductor device has a semiconductor substrate and has a photodetecting unit on one surface of the semiconductor substrate. A portion of the semiconductor substrate on the side opposite the photodetecting unit is trimmed to form a recessed portion in the semiconductor substrate. A thinned portion is thus provided at the portion of the semiconductor substrate at which the photodetecting unit is disposed. This thinned portion is provided to accommodate ultraviolet rays, soft X-rays, electronic beams, and other energy rays that will be absorbed and cannot be detected at high sensitivity by a thick semiconductor substrate. At this thinned portion, light that is made incident on the surface at the recessed portion side of the semiconductor substrate is detected by the photodetecting unit.
  • As an example of a back-illuminated semiconductor device, there is a semiconductor device that has a BT-CCD (back-thinned CCD). The BT-CCD is used as a detecting unit of a semiconductor inspecting device. An example of a conventional semiconductor device having a BT-CCD is described in Patent Document 1.
  • Fig. 7 is a sectional view of an arrangement of the semiconductor device described in Patent Document 1. As shown in Fig. 7, a P-type silicon layer 104, which is a semiconductor substrate having a CCD 103 on a surface that opposes a wiring substrate 102, is mounted via metal bumps 105 onto wiring substrate 102, which is fixed to a bottom portion of the interior of a package 101. Each wiring 106 on wiring substrate 102 is connected at one end to a metal bump 105 and has a bonding pad (not shown) for externally taking out detected signals at the other end, and each bonding pad is electrically connected by a bonding wire 107 to a lead terminal (not shown) of package 101. Furthermore, a gap between wiring substrate 102 and P-type silicon layer 104 is filled with an underfill resin 108 for reinforcing the bonding strengths of metal bumps 105.
  • Patent Document 1: Japanese Published Unexamined Patent Application No. Hei 6-196680
  • However, when the underfill resin fills the gap between the wiring substrate and the thinned portion of the semiconductor substrate as shown in Fig. 7, the thinned portion may crack due to the stress that arises due to a thermal expansion coefficient difference between the underfill resin and the semiconductor substrate in the process of heating or cooling to cure the underfill resin. Even if cracking does not occur, the thinned portion may become distorted by being pulled by the contraction of the underfill resin. Such distortion of the thinned portion of the semiconductor substrate may bring about adverse effects on focusing with respect to the photodetecting unit and uniformity and stability of sensitivity of the photodetecting unit during use of the semiconductor device.
  • This invention was made in view of the above issue and an object thereof is to provide a semiconductor device, with which the distortion and cracking of a thinned portion of a semiconductor substrate are prevented to enable high precision focusing with respect to a photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit to be maintained.
  • Disclosure of the Invention
  • In order to achieve the above object, this semiconductor device comprises: a semiconductor substrate, having a photodetecting unit formed on one surface, a thinned portion formed by etching a region, opposing the photodetecting unit, of another surface, and first electrodes disposed on the one surface at an outer edge of the thinned portion and electrically connected to the photodetecting unit; a wiring substrate, disposed to oppose the one surface side of the semiconductor substrate and having second electrodes connected via conductive bumps to the first electrodes; and a resin, filling a gap between the wiring substrate and the outer edge of the thinned portion to reinforce the strengths of bonding of the respective first electrodes and the respective second electrodes with the conductive bumps; and wherein the resin is a resin sheet that is formed in advance so as to surround a periphery of a gap between the thinned portion and the wiring substrate except for portions of the periphery.
  • With this semiconductor device, the resin fills the gap between the wiring substrate and the outer edge of the thinned portion. The strength of bonding of the conductive bumps with the first electrodes that are disposed at the outer edge of the thinned portion and the strength of bonding of the conductive bumps with the second electrodes of the wiring substrate are thus reinforced. Meanwhile, because the resin does not fill a gap between the wiring substrate and the thinned portion of the semiconductor substrate, even when stress due to the thermal expansion coefficient difference between the resin and the semiconductor substrate arises during heating or cooling in the process of curing the resin, etc., the influence of the stress on the thinned portion will be small and distortion and cracking of the thinned portion will be prevented. Thus with this semiconductor device, high precision focusing is enabled with respect to the photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit can be exhibited during use.
  • Furthermore, as the above-mentioned resin, the resin sheet, which is formed in advance to a desired shape, that is, a shape that surrounds the periphery of the gap between the thinned portion and the wiring substrate except for portions of the periphery, is used. An arrangement, wherein the resin fills the gap at which the conductive bumps exist, that is, the gap between the outer edge of the thinned portion and the wiring substrate while the gap between the wiring substrate and the thinned portion is left unfilled, can thus be realized readily and reliably.
  • A sealed space may form when the gap between the thinned portion and the wiring substrate is completely surrounded by the resin. In this case, the thinned portion may become distorted due to expansion or contraction of the air inside the sealed space during heating or cooling in the process of curing the resin, etc. In regard to this issue, with the present semiconductor device, the arrangement wherein the resin surrounds the periphery of the gap except at portions of the periphery is provided to prevent the gap from becoming sealed. Moreover, by use of the resin sheet formed in advance, this arrangement can also be realized readily and reliably.
  • The photodetecting unit may have a plurality of pixels that are arrayed one-dimensionally or two-dimensionally. This invention's semiconductor device is especially useful in this case because uniformity and stability of high sensitivity is required among the plurality of pixels.
    A semiconductor device manufacturing method of this invention comprises the steps of: preparing a semiconductor substrate, having a photodetecting unit formed on one surface, a thinned portion formed by etching a region, opposing the photodetecting unit, of another surface, and first electrodes disposed on the above-mentioned one surface at an outer edge of the thinned portion and electrically connected to the photodetecting unit; preparing a wiring substrate, disposed to oppose the above-mentioned one surface side of the semiconductor substrate and having second electrodes connected via conductive bumps to the first electrodes; adhering a solid resin sheet onto a predetermined region on the above-mentioned other surface of the semiconductor substrate; and thermocompression bonding the semiconductor substrate, with the resin sheet, to the wiring substrate; and the predetermined region is set to surround a periphery of a gap between the thinned portion and the wiring substrate except for portions of the periphery.
    In this case, the semiconductor device with the above-mentioned functions can be manufactured readily by adhering on the resin sheet.
  • By this invention, a semiconductor device can be realized with which the distortion and cracking of a thinned portion of a semiconductor substrate are prevented to enable high precision focusing with respect to a photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit to be maintained.
  • Brief Description of the Drawings
    • Fig. 1 is a sectional view of an embodiment of this invention's semiconductor device;
    • Fig. 2 is a plan view for describing an arrangement of resin 32 of Fig. 1;
    • Fig. 3 is a sectional view for describing an example of a method of manufacturing semiconductor device 1 of Fig. 1;
    • Fig. 4 is a plan view of an arrangement example of wiring substrate 20 of Fig. 1;
    • Fig. 5 is a sectional view of an arrangement of internal wirings of wiring substrate 20 of the arrangement example of Fig. 4;
    • Fig. 6 is a sectional view for describing the arrangement of internal wirings 60 of Fig. 5; and
    • Fig. 7 is a sectional view of an arrangement of a conventional semiconductor device.
    Explanation of Reference Numerals
    • 1...semiconductor device
    • 10...semiconductor substrate
    • 14...thinned portion
    • 15...outer edge
    • 16...electrode
    • 18...accumulation layer
    • 20...wiring substrate
    • 22...electrode
    • 24...lead terminal
    • 28...chip resistor
    • 30...conductive bumps
    • 32...resin
    • 34...communicating portion
    Best Modes for Carrying Out the Invention
  • Preferred embodiments of this invention's semiconductor device shall now be described in detail along with the drawings. In the description of the drawings, the same elements shall be provided with the same symbols and overlapping description shall be omitted. The dimensional proportions in the drawings do not necessary match those of the description.
  • Fig. 1 is a sectional view of an embodiment of this invention's semiconductor device. A semiconductor device 1 has a semiconductor substrate 10, a wiring substrate 20, conductive bumps 30, and a resin 32. Semiconductor substrate 10 is a BT-CCD (back-thinned CCD) and has a CCD 12 formed as a photodetecting unit on a portion of a top layer of its front surface S1 side. Semiconductor substrate 10 includes, for example, a silicon P+ layer, a P-type epitaxial layer formed above the silicon P+ layer, and an unillustrated set of transfer electrodes, formed on the epitaxial layer and to which driving signals are provided. CCD 12 has a plurality of pixels that are arrayed two-dimensionally. Also, a thinned portion 14 is formed by thinning by etching a region, opposing CCD 12, of a back surface S2. The etched portion has a truncated rectangular pyramidal profile. A surface of thinned portion 14 at the etched side is a flat and rectangular, light-incident surface S3, and this light-incident surface S3 is formed to be substantially the same in size as CCD 12. Semiconductor substrate 10 as a whole has a rectangular shape in plan view. Semiconductor substrate 10 is, for example, approximately 15 to 40µm thick at thinned portion 14 and approximately 300 to 600µm thick at an outer edge 15 of thinned portion 14. Outer edge 15 of thinned portion 14 refers to a portion of semiconductor substrate at the periphery of thinned portion 14 and is thicker than thinned portion 14.
  • Electrodes 16 (first electrodes) are formed on front surface S1 of outer edge 15. These electrodes 16 are electrically connected to the set of transfer electrodes of CCD 12 by wirings that are omitted from illustration. The entirety of back surface S2 of semiconductor substrate 10, including light-incident surface S3, is covered by an accumulation layer 18. Accumulation layer 18 is of the same conductive type as semiconductor substrate 10, however, is higher in impurity concentration than semiconductor substrate 10.
  • Semiconductor substrate 10 is mounted onto wiring substrate 20 by flip-chip bonding. Wiring substrate 20 is thus positioned to oppose the front surface S1 side of semiconductor substrate 10. Electrodes 22 (second electrodes) are formed at positions of wiring substrate 20 that oppose electrodes 16 of semiconductor substrate 10, and these electrodes 22 are connected via conductive bumps 30 to electrodes 16. Lead terminals 24, electrodes 22, conductive bumps 30, and electrodes 16 are thus connected to the CCD transfer electrodes and CCD drive signals are input into lead terminals 24. An output of an amplifier that outputs a CCD read signal is taken out from a lead terminal 24 via an electrode 16, a conductive bump 30, and an electrode 22. Wiring substrate 20 is formed, for example, of a multilayer ceramic substrate. An upper surface S4 (surface opposing semiconductor substrate 10) of wiring substrate 20 has a wider area than semiconductor substrate 10 and a region that does not oppose semiconductor substrate exists at an edge of upper surface S4.
  • Lead terminals 24 are disposed at a bottom surface S5 (surface at the opposite side of upper surface S4) of wiring substrate 20. Lead terminals 24 are connected to internal wirings (not shown) of wiring substrate 20.
  • Due to the interposition of conductive bumps 30, a gap exists between semiconductor substrate 10 and wiring substrate 20. Of this gap, a portion that is sandwiched by outer edge 15 and wiring substrate 20 is filled with insulating resin 32 (underfill resin) for reinforcing the bonding strengths of conductive bumps 30 (specifically the strengths of bonding of conductive bumps 30 with the respective electrodes 16 and electrodes 22). Resin 32 is a resin sheet, and as this sheet, a resin sheet, with which, for example, an epoxy-based resin, a urethane-based resin, a silicone-based resin, an acrylic-based resin, or a composite of such resins is formed to a sheet form, may be used.
  • The arrangement of resin 32 shall now be described in detail using Fig. 2. Fig. 2 is a plan view of wiring substrate 20 as viewed from its upper surface S4 side. In Fig. 2, broken lines L1 and L2 indicate outlines of semiconductor substrate 10 and thinned portion 14, respectively. The sectional view along line I-I of this figure corresponds to being Fig. 1. As shown in this figure, although resin 32 surrounds a periphery of a gap between thinned portion 14 of semiconductor substrate 10 and wiring substrate 20, it does not surround the entire periphery but surrounds the periphery with the exception of portions of the periphery. Specifically, resin 32 is disposed while leaving regions respectively extending from the four corners of a region of wiring substrate 20 that opposes the thinned portion (the rectangular region surrounded by broken lines L2) to the outer side of a region opposing semiconductor substrate 10. Communicating portions 34 that put the gap between thinned portion 14 and wiring substrate 20 in communication with the exterior of semiconductor device 1 are thus defined at the gap between semiconductor substrate 10 and wiring substrate 20.
  • Furthermore, a plurality of chip resistors 28 are disposed on upper surface S4 of wiring substrate 20. Chip resistors 28 are aligned one-dimensionally in the left/right direction of the figure, respectively at an upper portion and a lower portion in the figure in the region of wiring substrate 20 that opposes thinned portion 14.
  • Returning now to Fig. 1, operations of semiconductor device 1 shall be described. Light made incident on thinned portion 14 of semiconductor substrate 10 from light-incident surface S3 is detected by CCD 12. The detected signals pass through electrodes 16, conductive bumps 30, electrodes 22, in that order, and are thereby transmitted to wiring substrate 20. The detected signals (CCD read signals) are then transmitted to lead terminals 24 and output from lead terminals 24 to the exterior of semiconductor device 1.
  • The effects of semiconductor device 1 shall now be described. Resin 32 fills the gap between outer edge 15 of thinned portion 14 and wiring substrate 20. The strength of bonding of electrodes 16, disposed on outer edge 15 of thinned portion 14, with conductive bumps 30 and the strength of bonding of conductive bumps 30 with electrodes 22 of wiring substrate 20 are thereby reinforced. Meanwhile, because the gap between thinned portion 14 of semiconductor substrate 10 and wiring substrate 20 is not filled with resin 32, even if stress due to the thermal expansion coefficient difference between resin 32 and semiconductor substrate 10 arises between the two during heating or cooling in the process of curing resin 32, etc., the influence of the stress on thinned portion 14 will be low and distortion and cracking of thinned portion 14 are prevented. Thus with semiconductor device 1, high precision focusing with respect to CCD 12 is enabled and uniformity and stability of the high sensitivity of CCD 12 can be exhibited during use. Also, because cracking of thinned portion 14 is prevented, the manufacturing yield of semiconductor device 1 is improved.
  • Furthermore, as resin 32, a resin sheet that has been formed in advance to a desired shape, that is, a shape that surrounds the periphery of the gap between thinned portion 14 and the wiring substrate 20 except for portions of the periphery, is used. The arrangement, wherein resin 32 fills the gap at which conductive bumps 30 exist, that is, the gap between the outer edge of thinned portion 14 and wiring substrate 20 while the gap between thinned portion 14 and wiring substrate 20 is left unfilled, can thus be realized readily and reliably.
  • A sealed space may form when the gap between thinned portion 14 and wiring substrate 20 is completely surrounded by the resin 32. In this case, thinned portion 14 may become distorted due to expansion or contraction of the air inside the sealed space during heating or cooling in the process of curing the resin, etc. In regard to this issue, with semiconductor device 1, the arrangement, wherein resin 32 surrounds the periphery of the gap except at portions of the periphery, is provided to prevent the gap from becoming sealed. Moreover, by use of the resin sheet formed in advance, this arrangement can also be realized readily and reliably.
  • Semiconductor substrate 10 is provided with accumulation layer 18. The accumulation state of semiconductor substrate 10 is thereby maintained. Thereby the uniformity and stability of the sensitivity of CCD 12 with respect to short wavelength light can be improved further.
  • In recent years, demands for large area and high-speed response characteristics have been increasing for back-illuminated semiconductor devices. However, with an arrangement, such as that of the semiconductor device shown in Fig. 7, wherein the semiconductor substrate is die bonded once to the wiring substrate and then the wiring substrate is wire bonded to the lead terminals of the package, it is difficult to realize a large area and a high-speed response at the same time. That is, when the semiconductor device of this arrangement is made large in area, the resistance increases due to the accompanying elongation of the wires. Moreover, because in accordance with the making of the area large, the occurrence of crosstalk, the forming of capacitance (capacitor) between the wires, and other issues arise due to wires becoming close to each other and high in density, the realization of high-speed response is made even more difficult.
  • Meanwhile, with semiconductor device 1, because semiconductor substrate 10 is mounted onto wiring substrate 20 via conductive bumps 30, there is no need to perform wire bonding of semiconductor substrate 10 with wiring substrate 20. Furthermore, because wiring substrate 20 is provided with lead terminals 24, there is no need to provide a package besides wiring substrate 20 and thus, with semiconductor device 1, there is no need to perform wire bonding of wiring substrate 20 with lead terminals of a package. Thus with semiconductor device 1, because all of the wirings can be arranged without using wire bonding, even if a large area is to be realized, the above-mentioned problems of increased resistance, occurrence of crosstalk, and forming of capacitance do not occur. Semiconductor device 1 can thus meet the demands of both large area and high-speed response. For example, when the number of pixels of CCD 12 is 2054 pixels × 1024 pixels (with the chip size (area of semiconductor substrate 10) being slightly over 40.0mm × 20mm), whereas speeding up of the response to a rate of 1.6Gpixels/sec or more is difficult with the conventional semiconductor device, high-speed operation at 3.2Gpixels/sec is enabled with semiconductor device 1.
  • Fig. 3 is a sectional view for describing an example of a method for manufacturing semiconductor device 1 of Fig. 1. In this example, a solid transfer sheet (resin sheet) is used as resin 32, and this solid transfer sheet is adhered onto a predetermined region of front surface S 1 of semiconductor substrate 10. This predetermined region is a region that surrounds the periphery of thinned portion 14 except for portions of the periphery. Thereafter, by thermocompression bonding semiconductor substrate 10 onto wiring substrate 20, semiconductor device 1, shown in Fig. 1, is obtained. Since bumps 30 pierce the solid transfer sheet in the thermocompression bonding process, there is no need to form openings, etc., in advance at portions of the solid transfer sheet corresponding to bumps 30.
  • Fig. 4 is a plan view of an arrangement example of wiring substrate 20 of Fig. 1. Wiring substrate 20 of this arrangement example is a multilayer ceramic substrate. This wiring substrate 20 has a substantially square shape of 58.420mm square in plan view. The plurality of chip resistors 28 are disposed in the rectangular region (indicated by broken lines L2) of wiring substrate 20 that opposes thinned portion 14. In this region, chip resistors 28 are aligned one-dimensionally in the left/right direction of the figure (in the direction of the long sides of the rectangle) in two columns at each of an upper portion and a lower portion in the figure. The plurality of electrodes 22 are formed in a region at the outer side of the region. Electrodes 22 are aligned along each of the four sides of the rectangle, forming three columns along each of the long sides and forming two columns along each of the short sides. The diameter of each electrode 22 is 0.080mm.
  • Fig. 5 is a sectional view of an arrangement of internal wirings of wiring substrate 20 of the arrangement example of Fig. 4. Internal wirings 60 include signal output wirings 60a and 60b, clock supplying wirings 60c and 60d, and DC bias (ground) supplying wirings 60e. Each internal wiring 60 electrically connects an electrode 22, a lead terminal 24, and a chip resistor 28 to each other. The arrangement of internal wirings 60 shall now be described in more detail using Fig. 6. In Fig. 6, lead terminals 24 are indicated overlappingly on a plan view of wiring substrate 20 for the sake of description. As shown in this figure, whereas only signal output wirings 60a and 60b are formed inside the region opposing thinned portion 14, clock supplying wirings 60c and 60d and DC bias (clock) supplying wiring 60e are formed outside the region. By thus positioning the driving system wirings such as clock supplying wirings 60c and 60d and DC bias supplying wiring 60e separately from signal output wirings 60a and 60b, the occurrence of crosstalk between the driving system signals and the output system signals can be prevented.
  • Industrial Applicability
  • This invention can be applied to a semiconductor device and a method of manufacturing the same and particularly to a back-illuminated semiconductor device and a method for manufacturing the same.

Claims (3)

  1. A semiconductor device comprising:
    a semiconductor substrate, having a photodetecting unit formed on one surface, a thinned portion formed by etching a region, opposing the photodetecting unit, of another surface, and first electrodes disposed on the one surface at an outer edge of the thinned portion and electrically connected to the photodetecting unit;
    a wiring substrate, disposed to oppose the one surface side of the semiconductor substrate and having second electrodes connected via conductive bumps to the first electrodes; and
    a resin, filling a gap between the wiring substrate and the outer edge of the thinned portion to reinforce the strength of bonding of the respective first electrodes and the respective second electrodes with the conductive bumps; and
    wherein the resin is a resin sheet that is formed in advance so as to surround a periphery of a gap between the thinned portion and the wiring substrate except for portions of the periphery.
  2. The semiconductor device according to Claim 1, wherein the photodetecting unit has a plurality of pixels that are arrayed one-dimensionally or two-dimensionally.
  3. A semiconductor device manufacturing method comprising the steps of:
    preparing a semiconductor substrate, having a photodetecting unit formed on one surface, a thinned portion formed by etching a region, opposing the photodetecting unit, of another surface, and first electrodes disposed on the one surface at an outer edge of the thinned portion and electrically connected to the photodetecting unit;
    preparing a wiring substrate, disposed to oppose the one surface side of the semiconductor substrate and having second electrodes connected via conductive bumps to the first electrodes;
    adhering a solid resin sheet onto a predetermined region on the other surface of the semiconductor substrate; and
    thermocompression bonding the semiconductor substrate, with the resin sheet, to the wiring substrate; and
    wherein the predetermined region is set to surround a periphery of a gap between the thinned portion and the wiring substrate except for portions of the periphery.
EP04788124.8A 2003-09-25 2004-09-24 Semiconductor device and process for manufacturing the same Active EP1672695B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003333690A JP4494745B2 (en) 2003-09-25 2003-09-25 Semiconductor device
PCT/JP2004/013965 WO2005031872A1 (en) 2003-09-25 2004-09-24 Semiconductor device and process for manufacturing the same

Publications (3)

Publication Number Publication Date
EP1672695A1 true EP1672695A1 (en) 2006-06-21
EP1672695A4 EP1672695A4 (en) 2008-10-01
EP1672695B1 EP1672695B1 (en) 2014-07-23

Family

ID=34385998

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04788124.8A Active EP1672695B1 (en) 2003-09-25 2004-09-24 Semiconductor device and process for manufacturing the same

Country Status (5)

Country Link
US (1) US7696595B2 (en)
EP (1) EP1672695B1 (en)
JP (1) JP4494745B2 (en)
CN (1) CN100440520C (en)
WO (1) WO2005031872A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1879230A1 (en) * 2006-07-10 2008-01-16 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method of the same
EP2043153A1 (en) * 2006-07-11 2009-04-01 Hamamatsu Photonics K.K. Wiring board and solid-state imaging device
US8053852B2 (en) 2005-02-17 2011-11-08 Semiconductor Components Industries, Llc Light sensor receiving light from backside

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4351012B2 (en) * 2003-09-25 2009-10-28 浜松ホトニクス株式会社 Semiconductor device
JP4494746B2 (en) * 2003-09-25 2010-06-30 浜松ホトニクス株式会社 Semiconductor device
WO2006090684A1 (en) * 2005-02-23 2006-08-31 A. L. M. T. Corp. Semiconductor element mounting member and semiconductor device using same
US8907473B2 (en) * 2009-02-02 2014-12-09 Estivation Properties Llc Semiconductor device having a diamond substrate heat spreader
JP5940887B2 (en) * 2012-05-18 2016-06-29 浜松ホトニクス株式会社 Solid-state imaging device

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0544294A2 (en) * 1991-11-27 1993-06-02 Nec Corporation Method of bonding circuit boards
EP0821408A2 (en) * 1996-07-25 1998-01-28 Sharp Kabushiki Kaisha A structure of mounting a semiconductor element onto a substrate and a mounting method thereof
JPH1126922A (en) * 1997-07-02 1999-01-29 Matsushita Electric Ind Co Ltd Method for mounting chip
DE19848834A1 (en) * 1997-10-24 1999-07-01 Seiko Epson Corp Applying integrated circuit flip-chip to substrate
US6204163B1 (en) * 1998-04-13 2001-03-20 Harris Corporation Integrated circuit package for flip chip with alignment preform feature and method of forming same
EP1154457A1 (en) * 1999-01-21 2001-11-14 Hamamatsu Photonics K.K. Electron tube
US6410415B1 (en) * 1999-03-23 2002-06-25 Polymer Flip Chip Corporation Flip chip mounting technique
US20020084532A1 (en) * 2000-12-29 2002-07-04 Sudipto Neogi IC package pressure release apparatus and method
EP1223612A1 (en) * 2000-05-12 2002-07-17 Matsushita Electric Industrial Co., Ltd. Semiconductor device mounting circuit board, method of producing the same, and method of producing mounting structure using the same
US20020115278A1 (en) * 1999-11-24 2002-08-22 Wakahiro Kawai Method of mounting a semiconductor chip, circuit board for flip-chip connection and method of manufacturing the same, electromagnetic wave readable data carrier and method of manufacturing the same, and electronic component module for an electromagnetic wave readable data carrier

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2821062B2 (en) * 1992-07-09 1998-11-05 浜松ホトニクス株式会社 Manufacturing method of semiconductor energy detector
JPH06196680A (en) * 1992-12-22 1994-07-15 Hamamatsu Photonics Kk Semiconductor energy detector and manufacture thereof
JP3263288B2 (en) 1995-09-13 2002-03-04 株式会社東芝 Semiconductor device
JPH1084014A (en) * 1996-07-19 1998-03-31 Shinko Electric Ind Co Ltd Manufacture of semiconductor device
JP3430040B2 (en) * 1998-11-19 2003-07-28 シャープ株式会社 Two-dimensional image detector and manufacturing method thereof
DE19854733A1 (en) 1998-11-27 2000-05-31 Heidenhain Gmbh Dr Johannes Scanning unit of a position measuring device
JP2000228573A (en) 1999-02-05 2000-08-15 Canon Inc Module substrate structure
JP4786035B2 (en) * 1999-04-13 2011-10-05 浜松ホトニクス株式会社 Semiconductor device
JP3880278B2 (en) * 2000-03-10 2007-02-14 オリンパス株式会社 Solid-state imaging device and manufacturing method thereof
US6571466B1 (en) 2000-03-27 2003-06-03 Amkor Technology, Inc. Flip chip image sensor package fabrication method
US6201305B1 (en) 2000-06-09 2001-03-13 Amkor Technology, Inc. Making solder ball mounting pads on substrates
JP2002009265A (en) 2000-06-21 2002-01-11 Sony Corp Solid-state image pickup device
KR100343432B1 (en) 2000-07-24 2002-07-11 한신혁 Semiconductor package and package method
JP3696132B2 (en) 2001-07-10 2005-09-14 株式会社東芝 Active matrix substrate and manufacturing method thereof
JP2003078120A (en) 2001-08-31 2003-03-14 Seiko Precision Inc Solid-state imaging device
US6580174B2 (en) 2001-09-28 2003-06-17 Intel Corporation Vented vias for via in pad technology yield improvements
JP2003124259A (en) * 2001-10-15 2003-04-25 Seiko Epson Corp Mounting structure of electronic part, electronic part module and mounting method of electronic part
JP3773177B2 (en) * 2001-11-30 2006-05-10 松下電器産業株式会社 Solid-state imaging device and manufacturing method thereof
JP3787765B2 (en) 2001-11-30 2006-06-21 松下電器産業株式会社 Solid-state imaging device and manufacturing method thereof
JP3891133B2 (en) * 2003-03-26 2007-03-14 セイコーエプソン株式会社 Electronic component manufacturing method and electronic component mounting method
JP4271625B2 (en) 2004-06-30 2009-06-03 株式会社フジクラ Semiconductor package and manufacturing method thereof

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0544294A2 (en) * 1991-11-27 1993-06-02 Nec Corporation Method of bonding circuit boards
EP0821408A2 (en) * 1996-07-25 1998-01-28 Sharp Kabushiki Kaisha A structure of mounting a semiconductor element onto a substrate and a mounting method thereof
JPH1126922A (en) * 1997-07-02 1999-01-29 Matsushita Electric Ind Co Ltd Method for mounting chip
DE19848834A1 (en) * 1997-10-24 1999-07-01 Seiko Epson Corp Applying integrated circuit flip-chip to substrate
US6204163B1 (en) * 1998-04-13 2001-03-20 Harris Corporation Integrated circuit package for flip chip with alignment preform feature and method of forming same
EP1154457A1 (en) * 1999-01-21 2001-11-14 Hamamatsu Photonics K.K. Electron tube
US6410415B1 (en) * 1999-03-23 2002-06-25 Polymer Flip Chip Corporation Flip chip mounting technique
US20020115278A1 (en) * 1999-11-24 2002-08-22 Wakahiro Kawai Method of mounting a semiconductor chip, circuit board for flip-chip connection and method of manufacturing the same, electromagnetic wave readable data carrier and method of manufacturing the same, and electronic component module for an electromagnetic wave readable data carrier
EP1223612A1 (en) * 2000-05-12 2002-07-17 Matsushita Electric Industrial Co., Ltd. Semiconductor device mounting circuit board, method of producing the same, and method of producing mounting structure using the same
US20020084532A1 (en) * 2000-12-29 2002-07-04 Sudipto Neogi IC package pressure release apparatus and method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2005031872A1 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8053852B2 (en) 2005-02-17 2011-11-08 Semiconductor Components Industries, Llc Light sensor receiving light from backside
EP1879230A1 (en) * 2006-07-10 2008-01-16 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method of the same
EP2043153A1 (en) * 2006-07-11 2009-04-01 Hamamatsu Photonics K.K. Wiring board and solid-state imaging device
EP2043153A4 (en) * 2006-07-11 2012-08-15 Hamamatsu Photonics Kk Wiring board and solid-state imaging device

Also Published As

Publication number Publication date
JP2005101315A (en) 2005-04-14
EP1672695A4 (en) 2008-10-01
CN100440520C (en) 2008-12-03
WO2005031872A1 (en) 2005-04-07
CN1853274A (en) 2006-10-25
EP1672695B1 (en) 2014-07-23
US7696595B2 (en) 2010-04-13
US20070272997A1 (en) 2007-11-29
JP4494745B2 (en) 2010-06-30

Similar Documents

Publication Publication Date Title
US8896079B2 (en) Camera module having a light shieldable layer
KR100692481B1 (en) Solid-state imaging device and method for manufacturing the same
KR100731541B1 (en) Solid-state imaging device and method for manufacturing the same
US6232655B1 (en) Semiconductor element having external connection terminals, method of manufacturing the semiconductor element, and semiconductor device equipped with the semiconductor element
US7556975B2 (en) Method for manufacturing backside-illuminated optical sensor
US20060202333A1 (en) Package of a semiconductor device with a flexible wiring substrate and method for the same
EP1672695B1 (en) Semiconductor device and process for manufacturing the same
EP1672694B1 (en) Semiconductor device
US7612442B2 (en) Semiconductor device
JP4271909B2 (en) Solid-state imaging device and manufacturing method thereof
EP1434276A2 (en) Image sensor adapted for reduced component chip scale packaging
CN111211140B (en) Solid-state image pickup device and method of manufacturing the same
JP4799746B2 (en) Radiation detector module
JP2004063765A (en) Solid-state image sensing device and its manufacturing method
US20090212400A1 (en) Semiconductor device and manufacturing method and mounting method thereof
CN220569663U (en) Chip packaging structure
EP3211672B1 (en) Chip-scale package for an optical sensor semiconductor device with filter and method of producing a chip-scale package
CN114651324A (en) Image sensor module and method for manufacturing image sensor module
JP2023133922A (en) Infrared sensor and infrared sensor manufacturing method
CN117038594A (en) Chip packaging structure and chip packaging method

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20060418

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB

DAX Request for extension of the european patent (deleted)
RBV Designated contracting states (corrected)

Designated state(s): DE FR GB

A4 Supplementary search report drawn up and despatched

Effective date: 20080828

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 31/02 20060101ALI20080822BHEP

Ipc: H01L 27/14 20060101AFI20050408BHEP

Ipc: H01L 21/60 20060101ALI20080822BHEP

Ipc: H01L 21/56 20060101ALI20080822BHEP

Ipc: H01L 23/31 20060101ALI20080822BHEP

17Q First examination report despatched

Effective date: 20080929

REG Reference to a national code

Ref country code: DE

Ref legal event code: R079

Ref document number: 602004045523

Country of ref document: DE

Free format text: PREVIOUS MAIN CLASS: H01L0027140000

Ipc: H01L0027146000

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 21/56 20060101ALI20140114BHEP

Ipc: H01L 23/00 20060101ALI20140114BHEP

Ipc: H01L 27/146 20060101AFI20140114BHEP

Ipc: H01L 27/148 20060101ALI20140114BHEP

INTG Intention to grant announced

Effective date: 20140203

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602004045523

Country of ref document: DE

Effective date: 20140904

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602004045523

Country of ref document: DE

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20150424

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 13

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 14

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 15

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230509

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20230803

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20230808

Year of fee payment: 20

Ref country code: DE

Payment date: 20230802

Year of fee payment: 20