EP1665701A4 - Noise shaped interpolator and decimator apparatus and method - Google Patents
Noise shaped interpolator and decimator apparatus and methodInfo
- Publication number
- EP1665701A4 EP1665701A4 EP04780201A EP04780201A EP1665701A4 EP 1665701 A4 EP1665701 A4 EP 1665701A4 EP 04780201 A EP04780201 A EP 04780201A EP 04780201 A EP04780201 A EP 04780201A EP 1665701 A4 EP1665701 A4 EP 1665701A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- frequency
- storage element
- decimator
- delta
- inteφolator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
- H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
- H03H17/0628—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing the input and output signals being derived from two separate clocks, i.e. asynchronous sample rate conversion
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
- G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
- G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
- H03H17/0614—Non-recursive filters using Delta-modulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
- G06F2205/061—Adapt frequency, i.e. clock frequency at one side is adapted to clock frequency, or average clock frequency, at the other side; Not pulse stuffing only
Definitions
- the present invention relates generally radio frequency signals, and specifically for efficient apparatus and methods for radio frequency (RF) signal transmission, reception, and modulation.
- RF radio frequency
- digital sample rate conversion between two different clock rates can be performed without introduction of sample error (phase noise) if the two sample frequencies are related by a rational ratio. This is typically accomplished by interpolating to the lowest frequency that is a multiple of both the source and sink sample rates, and then decimating to the required sink sample rate.
- phase noise will be introduced even if the source and sink sample clocks are ideal.
- jitter on the source and sink clocks result in the introduction of phase noise even if the rates are related rationally, so noise-shaped delta-sigma modulated fractional-N (“Frac-N”) sample rate converters are often the best choice even when the source and sink clocks are rationally related.
- Fractional rate interpolators create an effective interpolation rate that is the average of a series of integer hold values. For example, a fractional interpolation rate of 7.5 could be created by alternating 7 cycle sample-holds with 8 cycle sample-holds.
- delta-sigma modulation is well known in the signal processing arts and are described in, e.g., "Delta-Sigma Data Converters - Theory, Design and Simulation", Norsworthy, et al., IEEE Press, 1997. Both Integer and Fractional-N digital sample rate converters have been described in the literature; see U.S. Patent No. 5,497,152 issued March 5, 1996 and entitled “Digital-to- Digital Conversion Using Non-Uniform Sample Rates” which is incorporated herein by reference in its entirety; and “Sample-Rate Conversion: Algorithms and VLSI Implementation", Diss. ETH No. 10980, Swiss Federal Institute of Technology, Zurich (1995), also incorporated herein by reference in its entirety.
- the inte ⁇ olator uses the elastic storage element to buffer or absorb sample rate variations occurring between two different clock or data domains.
- a low pass filter (LPF) filters the error signal related to the difference between the two domains; this filtered signal acts as an input to the delta-sigma modulator.
- LPF low pass filter
- the modulator output is input to a modulo-N counter, the output of which is used to adjust the sample rate in the asynchronous (e.g., read) domain.
- improved decimator apparatus useful in a communications circuit comprising: an elastic storage element; a filter; and a delta-sigma modulator.
- the decimator uses the elastic storage element to buffer or absorb sample rate variations occurring between two different clock or data domains, akin (but for the decimation function) to the inte ⁇ olator described above.
- a low pass filter (LPF) filters the error signal related to the difference between the two domains; this filtered signal acts as an input to the delta-sigma modulator.
- the modulator output is input to a modulo-N counter, the output of which is used to adjust the sample rate in the asynchronous (e.g., write) domain.
- improved radio frequency apparatus including a fractional oscillator having a modulus update frequency is disclosed.
- the oscillator comprises a delta-sigma phase-locked loop (PLL).
- the radio frequency apparatus utilizes a transmit frequency and receive frequency, and the PLL utilizes a modulus update frequency comprising a multiple or sub-multiple of an offset between the receive frequency and the transmit frequency.
- the modulus update frequency can also be dynamically varied as a function of at least one parameter such as transmitter power, and/or the order of the delta-sigma PLL (where a variable-order device is used).
- a method of suppressing phase noise in a radio frequency device having a transmit frequency and receive frequency comprises: providing a delta-sigma Frac-N phase lock loop (PLL) having a modulus; and updating the modulus at a frequency comprising a multiple or sub- multiple of an offset between the receive frequency and transmit frequency. The updating reduces the presence of phase noise generated by the PLL at the receive frequency.
- PLL phase lock loop
- a method of operating a fractional-N inte ⁇ olator apparatus comprising a delta-sigma modulator, first and second clock domains, and an elastic buffer disposed operatively between the clock domains is disclosed.
- the method comprises: clocking data into the buffer using the first clock domain; generating an error signal related to the difference between the first and second clock domains; filtering the error signal; modulating the filtered error signal; and generating a clock period signal based at least in part on the modulated filtered signal.
- Data is read from the elastic buffer in an asynchronous fashion based at least in part on the clock period signal.
- a method of operating a fractional-N inte ⁇ olation or decimation apparatus comprising a delta-sigma modulator, first and second clock domains, one of the clock domains operating at a speed greater than the other, is disclosed.
- the method comprises asynchronously clocking data out of or into an elastic storage element disposed between the two clock domains based at least in part on a signal generated by the delta-sigma modulator and counter.
- improved radio frequency transceiver apparatus comprises: a baseband processor adapted to process a plurality of baseband data; and a transmitter comprising a delta-sigma modulator fractional-N inte ⁇ olator.
- the transmitter comprises a direct conversion transmitter adapted to convert directly from baseband to carrier frequency, and includes a resonator.
- the l ⁇ ic ⁇ oiaxor comprises an elastic storage element, low-pass filter and modulo counter, the storage element, filter, modulator and counter cooperating to elastically buffer variations in sampling rates between an input domain and output domain of the inte ⁇ olator.
- the inte ⁇ olator and transmitter also cooperate to suppress phase noise within at least one frequency band other than a frequency band used by the transmitter.
- Fig. 1 is a schematic (circuit) diagram of an exemplary embodiment of an inte ⁇ olator circuit according to the present invention.
- Fig. 2 is a circuit diagram of a first exemplary embodiment of the elastic storage device (and associated components) of the inte ⁇ olator of Fig. 1.
- Fig. 3 is a schematic diagram of an exemplary embodiment of a decimator circuit according to the present invention.
- Fig. 4 is a plot of the noise transfer function of an exemplary coder (fifth order) according to the invention, showing the notch at 637.4783 MHz with respect to the sample rate of 1880 MHz.
- Fig. 5 is a graphical representation of a spectrum generated using integer (non- fractional) inte ⁇ olation of the combined inte ⁇ olation and filtering stages.
- Fig. 6 is a graphical representation of a spectrum generated using the fractional sample rate converter, of the combined inte ⁇ olation and filtering stages.
- Fig. 7 is a detail view of the spectrum of Fig. 6, specifically at the notch frequency corresponding to the receive band.
- Fig. 8 is a graphical representation of an exemplary spectrum of the output of an I- coder following the fractional rate interpolator.
- Fig. 9 is a graphical representation of the spectral output of an exemplary I-coder (partial view).
- Fig. 10 is a graphical representation of an exemplary spectrum of the output of the digital transmitter that combines and upconverts the I and Q coders.
- Fig. 11 shows the frequency response for an exemplary bandpass filter/RF resonator/duplexer configuration according to the invention.
- Fig. 12 is an exemplary output spectrum of the exemplary digital transmitter of the invention after the analog bandpass filter and RF resonator and duplexer.
- Fig. 13 is a functional block diagram of an exemplary radio frequency transceiver circuit inco ⁇ orating both the inte ⁇ olator and decimator apparatus of the present invention.
- Fig. 14 is a functional block diagram of another embodiment of a radio frequency transceiver circuit according to the present invention, incorporating a phase-lock loop (PLL) arrangement.
- PLL phase-lock loop
- Fig. 15 is a graphical representation of an exemplary digital transmitter showing the phase noise transfer function of the VCO output of a fractional-N delta-sigma PLL having sin(x)/x sampling nulls occurring at multiples an exemplary receiver frequency offset (e.g., 80 MHz) from the transmitter.
- Fig. 16 is a graphical representation of an exemplary digital transmitter showing the phase noise profile of the VCO output of fractional-N delta-sigma PLL having sin(x)/x sampling nulls occurring at multiples of the receiver frequency offset from the transmitter.
- FIG. 17 is a graphical representation of an exemplary digital transmitter showing the output with a pure carrier, using a fractional-N delta-sigma PLL having sin(x)/x sampling nulls occurring at multiples of the receive frequency offset from the transmitter.
- Fig. 18 is a graphical representation of an exemplary digital transmitter showing the spectral output of the overall digital transmitter prior to analog bandpass filter/duplexer, but with phase noise in accordance with Figures 15, 16, and 17.
- CDMA code division multiple access
- transmission transmission
- transmission transmitting
- processor is meant generally to include all types of data or signal processing devices including, without limitation, digital signal processors (DSPs), reduced instruction set computers (RISC), general-pu ⁇ ose (CISC) processors, microprocessors, gate arrays (e.g., FPGAs), Reconfigurable Compute Fabrics (RCFs), and application-specific integrated circuits (ASICs).
- DSPs digital signal processors
- RISC reduced instruction set computers
- CISC general-pu ⁇ ose
- microprocessors e.g., FPGAs
- RCFs Reconfigurable Compute Fabrics
- ASICs application-specific integrated circuits
- RAM e.g., SRAM, SDRAM, DRAM, SDRAM, EDR-DRAM, DDR
- ROM e.g., PROM
- EPROM EPROM
- EEPROM Electrically erasable programmable read-only memory
- UV-EPROM UV-EPROM
- magnetic bubble memory magnetic bubble memory
- optical memory embedded flash memory, etc.
- the present invention provides, mter alia, an improved inte ⁇ olator and decimator architectures having simplicity as well as increased efficiency. These benefits are largely afforded through the use of one or more "elastic" storage elements (e.g., an asynchronous
- FIFO digital phase lock loop
- PLL digital phase lock loop
- an elastic storage element in the signal path advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator.
- the elastic element(s) e.g., FIFO(s)
- FIFO(s) combined with a delta-sigma modulator and counter creates a noise-shaped frequency-lock loop without additional components, resulting in a much simplified inte ⁇ olator or decimator as compared to prior art solutions. This not only reduces the complexity and cost of any parent device (e.g., wireless handset, etc.) using this architecture, but also increases its robustness and efficiency.
- a noise-shaped frequency-tracking digital sample rate inte ⁇ olator comprises a noise-shaped frequency-tracking digital sample rate inte ⁇ olator, and includes an "elastic" storage element 102 (here, an asynchronous FIFO, shown in Fig. 2, although other types of devices may be used to provide this functionality), a digital low pass filter (LPF) 104 which filters and scales the error signal generated in the circuit 100, a noise shaped delta-sigma modulator 106, and a modulo counter 108 that converts the output of the delta-sigma modulator 106 to a clock period. Data is input and output via two respective ports 105, 107 of the storage element 102.
- the circuit 100 is also provided with an offset input 109 to allow user-selected offsets as described subsequently herein.
- the term “elastic” refers generally to any component or group of components which act to at least partly decouple one domain from one or more others, or provide buffering there between.
- the exemplary embodiment of the inte ⁇ olator circuit uses the elastic storage element to substantially decouple or buffer between two clock domains, thereby allowing some degree of independence in their operation.
- the exemplary elastic storage device 102 comprises a circuit 200 having an asynchronous FIFO (shown in detail in Fig. 2).
- the FIFO 102 comprises a multi-port (dual port) RAM 202 with clocked write 204 and asynchronous read 206 of the type well known in the computer arts, although it will be appreciated that other configurations of storage device may be used, the present invention not being limited to a dual-port or even multi- port RAM.
- a single-port storage device adapted for asynchronous accesses by two or more bus masters may be used, assuming the access rates for each master are sufficiently fast.
- a buffered non-blocking switch fabric of the type well known in the digital processor arts may conceivably be used.
- read and write pointers are built with Gray code counters, with the write counter residing in the source clock domain and the read counter residing in the sink (read) clock domain. Both pointers in the circuit 200 of Fig. 2 are re-clocked into the other domain and a current count of entries is calculated in each domain. The count in the slower domain of the circuit 200 of Fig. 2 may contain anomalies due to skew in the re- clocking, and accordingly is not utilized in the illustrated embodiment of Fig.
- Gray codes also called cyclical or progressive codes
- Gray codes have historically been useful in mechanical encoders since a slight change in location only affects one bit.
- these same codes offer other benefits well understood to one skilled in the art including being hazard-free for logic and other conditions that could give rise to faulty operation of the circuit.
- the use of such Gray codes also have important advantages in power saving designs.
- the re-clocked value could be any of 00, 01, 10, or 1 1, depending on the clock skew and exact relationship between clock and data. Since Gray code is used, the transition is from “01” to "1 1", and the only possibilities are “01” (clock early) or "1 1” (clock late). It will also be appreciated that the above-referenced power savings (reduced switching) may also be realized through the use of Gray codes in, e.g., integrated circuit implementations of the circuits 100, 200. It is recognized that in the illustrated embodiment, the rate of change of the number of entries in the FIFO 102 is the difference between the source sample rate and the sink sample rate.
- the number of entries is the integral of the difference between the source and sink sample rates. This is exactly the signal that is needed as input to the delta-sigma modulator to control the average number of sink clock cycles per source clock cycle (for an interpolator; the opposite is true of a decimator). In practice, this signal is low- pass filtered, and the FIFO 102 is used to absorb short term variations in the ratio of source and sink sample rates. The number of entries in the FIFO 102 sets the range of frequency ratios over which the loop can lock, and an offset can be added to set the midpoint of that range if desired. The order and bit-width of the delta-sigma modulator 106 is chosen to allow the desired noise shaping within the constraints of the sink to source sample ratio.
- An offset may be added to the delta-sigma modulator output to set a minimum sample period.
- the maximum sample period is the offset plus the maximum delta-sigma modulator output (e.g., 2 blt"wldth - 1). In the exemplary configuration, this would be centered around the anticipated source-to-sink sample ratio, although other values may conceivably be used.
- Fig. 3 an exemplary configuration of a noise shaped decimator circuit 300 according to the invention is shown. This decimator is basically the dual of the inte ⁇ olator. In this case, N samples of input data, where N is controlled by the delta-sigma modulator 306, are accumulated and then dumped to the elastic storage element (e.g., FIFO) 302.
- the elastic storage element e.g., FIFO
- Figs. 4-12 an exemplary implementation of a fractional sample rate inte ⁇ olator (part of an exemplary digital radio architecture described by the co- pending U.S. patent applications previously referenced herein) is discussed in detail for pu ⁇ oses of illustration. It will be recognized that the present invention is in no way limited to the details, values, or configuration of the following example.
- the digital samples are being filtered and up- converted from a base-band rate of 1.2288 MHz, to a carrier rate that can vary from 1850 to 1910 MHz. This is done in three stages, where the combined inte ⁇ olation of the first two stages is 192, and the third stage is implemented using the described invention.
- the base- band frequency and range of carrier frequencies when taken with the fixed inte ⁇ olation ratio of 192, imply that the final inte ⁇ olation will be in the range of approximately 7.7 to 8.1.
- the example spectra were generated with a ratio of 1880/(1.2288*192) or about 7.9685.
- the output sample rate is 1880 MHz.
- the receive band is 80 MHz offset above the transmit band.
- the noise-shaping delta- sigma modulator (coder) must suppress noise at around this frequency with a 1.2288 MHz bandwidth.
- the coder effectively runs at 1880 MHz.
- the ratio 647.4783 / 1880 0.33908 approximately, which is the relative normalized frequency we must place a null at in the noise shaping coder for noise suppression.
- Fig. 4 is a plot of the noise transfer function of the coder, showing the notch at 637.4783 MHz approximately.
- Fig. 5 is a spectrum using integer (non-fractional) inte ⁇ olation of the combined inte ⁇ olation and filtering stages.
- Fig. 6 is a spectrum, using the fractional sample rate converter, of the combined inte ⁇ olation and filtering stages.
- Fig. 7 is a focus view of Fig. 6 at the notch frequency location of interest corresponding to the receive band.
- Fig. 5 is a spectrum using integer (non-fractional) inte ⁇ olation of the combined inte ⁇ olation and filtering stages.
- Fig. 6 is a spectrum, using the fractional sample rate converter, of the combined inte ⁇ olation and filtering stages.
- Fig. 8 is a spectrum of the output of the I-coder that follows the fractional rate inte ⁇ olator, and Fig. 9 is a focus view thereof.
- Fig. 10 is a spectrum of the output of the digital transmitter that combines and upconverts the I and Q coders.
- Fig. 11 shows the frequency response of the RF resonator/duplex filter, and
- Fig. 12 is a spectrum of the digital transmitter after the RF resonator/duplexer is applied. The noise in the receive band is not appreciably degraded by the fractional sample rate converter.
- the transceiver 1300 comprises a transmitter section 1301 with baseband processor 1302, a fractional inte ⁇ olator 1304 (such as that described herein), noise shaping coder (NSC) 1310, sample and hold inte ⁇ olator 1312, a digital I/Q quadrature mixer and combiner 1313, and a high-efficiency DAC 1314 (such as that described in co-pending and co-owned U.S. Patent Application Serial No.
- a resonator (not shown) is also utilized in conjunction with the duplexer 1316 to generate the analog output of the transmitter.
- the inte ⁇ olator, NSC, DAC and resonator cooperate to convert the digital in-phase (I) and quadrature (Q) signals obtained from the baseband processor directly to an analog representation at carrier frequency for transmission over an antenna in a highly power-efficient manner.
- the transmitter is further adapted to dislocate quantization noise generated by the transmitter outside of one or more receive bands associated with a related receiver unit of the transmitter.
- the transceiver circuit 1300 of Fig. 13 also includes a receiver section 1320 including the duplexer 1316, analog-to-digital converter (ADC) 1322, fractional decimator 1324 (which includes the fractional noise-shaping decimator described herein), and baseband processor 1326 (which may or may not be the same baseband processor 1302 as described above).
- ADC analog-to-digital converter
- fractional decimator which includes the fractional noise-shaping decimator described herein
- baseband processor 1326 which may or may not be the same baseband processor 1302 as described above.
- the received signals are duplexed and sent to the ADC (via a bandpass filter and low noise amplifier), wherein they are converted to the digital domain.
- the fractional noise-shaping decimator decimates the signal and ultimately (with the aid of other decimation)
- an improved RF device and method of operating the same is disclosed.
- the present invention also optionally includes a means for reducing the sensitivity to phase noise and causing less degradation in the receive band, which may be offset in frequency from the transmit band in a full duplex transceiver.
- a fractional-N phase lock loop PLL
- the receive frequency is typically 80 MHz above the transmit frequency.
- Fig. 14 shows an exemplary embodiment of a PLL-based transceiver apparatus 1400.
- the baseband clocks related to F b are derived from an independent clock source
- the carrier-related clocks related to F c are derived from an independent PLL 1402 with a modulus update frequency control signal, F modu i us 1406.
- the PLL 1402 may be of the type ordinary in the art, such as a Fractional-N synthesis PLL (as shown) or a delta-sigma PLL, or any other structure which provides the aforementioned functionality.
- Fig. 15 is a plot of the phase noise transfer function of the VCO of a fractional-N phase lock loop (PLL) (such as that of Fig. 14) having a modulus update rate of 80 MHz.
- PLL phase lock loop
- Fig. 16 is a plot of the phase noise profile that follows Fig. 15. Fig.
- FIG. 17 is a plot of a pure transmit carrier frequency, i.e., an unmodulated periodic sequence of ⁇ 1,0,-1,0 ⁇ ' , but with jittered sampling edges in accordance with the phase noise profile that follows from Fig. 16.
- the noise at 80 MHz offset in a 1.2288 MHz bandwidth is -168dBm/Hz, where the transmit power is +28dBm.
- Fig. 18 is a plot of the actual modulated sequence having jittered sampling edges in accordance with the phase noise profile that follows from Fig. 16. This plot, Fig. 18, can be compared with that of Fig. 10.
- the noise at 80 MHz offset in a 1.2288 MHz bandwidth is - 149dBm/Hz, as opposed to -153dBm/Hz in the ideal case without jitter or phase noise. It should be noted that if the same duplexer/resonator is applied (as comparing Fig. 10 with Fig. 12), then the receive noise is additionally suppressed by another 40 dB or so using the aforementioned techniques. It will be further recognized that the disclosed techniques for reducing phase noise (e.g., in the receive band(s)) may be used selectively with respect to the other aspects of the present invention.
- the modulus update frequency of the aforementioned fractional-N phase lock loop may be dynamically or selectively varied depending on various factors including the need for further suppression in the receive band, power consumption, etc.
- the fractional-N PLL may also be selectively switched in or out if desired as well, and/or put into a "sleep" mode under certain operating conditions to conserve power.
- Myriad different schemes for selectively utilizing and/or controlling the operation of the fractional-N PLL may be used consistent with the invention, as will be recognized by those of ordinary skill when provided the present disclosure. It can be appreciated that the various circuits of the present invention may be rendered as stand-alone or discrete electronic circuits, as well as integrated circuit (IC) devices.
- IC integrated circuit
- Such integrated circuit devices may include, for example, system-on-chip (SoC) devices which integrate multiple functions or modules onto a single semiconductive die rendered in a sub-micron SiGe process.
- SoC system-on-chip
- the interpolator (and/or decimator) circuits are included with the digitally switched resonator, noise shaping coder, etc. of the direct-conversion architecture referenced above.
- Baseband processing may also optionally be included within this device. This highly integrated approach provides significant benefits in terms of size and compactness, power consumption, and ease of design and implementation.
Abstract
Description
Claims
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US49304103P | 2003-08-05 | 2003-08-05 | |
US49632003P | 2003-08-18 | 2003-08-18 | |
US10/910,917 US7116253B2 (en) | 2003-08-05 | 2004-08-03 | Radio frequency digital-to-analog converter |
PCT/US2004/025323 WO2005015752A2 (en) | 2003-08-05 | 2004-08-04 | Noise shaped interpolator and decimator apparatus and method |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1665701A2 EP1665701A2 (en) | 2006-06-07 |
EP1665701A4 true EP1665701A4 (en) | 2009-04-22 |
Family
ID=34714343
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP04780201A Withdrawn EP1665701A4 (en) | 2003-08-05 | 2004-08-04 | Noise shaped interpolator and decimator apparatus and method |
Country Status (2)
Country | Link |
---|---|
EP (1) | EP1665701A4 (en) |
WO (1) | WO2005015752A2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2903790A1 (en) * | 2006-07-13 | 2008-01-18 | Dolphin Integration Sa | DATA FLOW ADAPTER |
EP2037584A1 (en) | 2007-09-14 | 2009-03-18 | STMicroelectronics N.V. | Method for performing a digital to analog conversion of a digital signal, and corresponding electronic device. |
EP3678294B1 (en) | 2007-09-14 | 2022-02-02 | Telefonaktiebolaget LM Ericsson (publ) | Method for notch filtering a digital signal, and corresponding electronic device |
EP2771973B1 (en) * | 2011-10-25 | 2017-08-30 | Cirrus Logic International Semiconductor Ltd. | Asynchronous sample rate converter |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0512619A1 (en) * | 1991-05-10 | 1992-11-11 | Koninklijke Philips Electronics N.V. | Sampling frequency converter |
US5555524A (en) * | 1995-02-13 | 1996-09-10 | Standard Microsystems Corporation | Semi-synchronous dual port FIFO |
US6005901A (en) * | 1997-02-27 | 1999-12-21 | Advanced Micro Devices | Arrangement for asynchronous decimation using a frequency ratio estimator and method thereof |
US6061410A (en) * | 1997-02-27 | 2000-05-09 | Advanced Micro Devices | Frequency ratio estimation arrangement and method thereof |
US6215423B1 (en) * | 1998-08-26 | 2001-04-10 | Motorola Inc. | Method and system for asynchronous sample rate conversion using a noise-shaped numerically control oscillator |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5475628A (en) * | 1992-09-30 | 1995-12-12 | Analog Devices, Inc. | Asynchronous digital sample rate converter |
US5497152A (en) * | 1993-09-13 | 1996-03-05 | Analog Devices, Inc. | Digital-to-digital conversion using non-uniform sample rates |
DE19820572A1 (en) * | 1998-05-08 | 1999-11-11 | Alcatel Sa | Desynchronisation device for synchronous digital transmission system |
US6740250B2 (en) | 2001-07-13 | 2004-05-25 | Hazard Control Technologies | Fire suppressant having foam stabilizer |
TW517462B (en) * | 2001-12-06 | 2003-01-11 | Realtek Semi Conductor Co Ltd | Oversampling DAC with variable sampling rate |
-
2004
- 2004-08-04 EP EP04780201A patent/EP1665701A4/en not_active Withdrawn
- 2004-08-04 WO PCT/US2004/025323 patent/WO2005015752A2/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0512619A1 (en) * | 1991-05-10 | 1992-11-11 | Koninklijke Philips Electronics N.V. | Sampling frequency converter |
US5555524A (en) * | 1995-02-13 | 1996-09-10 | Standard Microsystems Corporation | Semi-synchronous dual port FIFO |
US6005901A (en) * | 1997-02-27 | 1999-12-21 | Advanced Micro Devices | Arrangement for asynchronous decimation using a frequency ratio estimator and method thereof |
US6061410A (en) * | 1997-02-27 | 2000-05-09 | Advanced Micro Devices | Frequency ratio estimation arrangement and method thereof |
US6215423B1 (en) * | 1998-08-26 | 2001-04-10 | Motorola Inc. | Method and system for asynchronous sample rate conversion using a noise-shaped numerically control oscillator |
Non-Patent Citations (1)
Title |
---|
See also references of WO2005015752A2 * |
Also Published As
Publication number | Publication date |
---|---|
WO2005015752A8 (en) | 2005-07-07 |
EP1665701A2 (en) | 2006-06-07 |
WO2005015752A2 (en) | 2005-02-17 |
WO2005015752A3 (en) | 2005-03-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9325488B2 (en) | Noise shaped interpolator and decimator apparatus and method | |
US8542616B2 (en) | Simultaneous multiple signal reception and transmission using frequency multiplexing and shared processing | |
JP5571209B2 (en) | Efficient hardware transceiver with delta-sigma digital / analog converter | |
US7075384B2 (en) | Delta-sigma modulated fractional-N PLL frequency synthesizer and wireless communication apparatus | |
JP4809017B2 (en) | Frequency synthesizer and operation method thereof | |
TWI286417B (en) | Digital delta sigma modulator and applications thereof | |
JP5662911B2 (en) | High frequency signal processing apparatus and radio communication system | |
US6876874B2 (en) | Process for reducing the electrical consumption of a transmitter/receiver of digital information, in particular a cellular mobile telephone, and corresponding transmitter/receiver | |
US6392493B1 (en) | Fractional-N frequency synthesizer | |
EP1277286B1 (en) | Personal communications device with gps receiver and comon clock source | |
US6066990A (en) | Frequency divider having a prescaler followed by a programmable counter, and a corresponding prescaler and frequency synthesizer | |
US20060045212A1 (en) | Software defined radio system | |
JPWO2007004465A1 (en) | Semiconductor device and radio circuit device using the same | |
WO2005015752A2 (en) | Noise shaped interpolator and decimator apparatus and method | |
US6490440B1 (en) | Digital transmitter circuit and method of operation | |
WO2000001072A1 (en) | System for generating an accurate low-noise periodic signal | |
US10958279B1 (en) | Partitioned digital-to-analog converter system | |
Neubauer et al. | A Digital Receiver Architecture for Bluetooth in 0.25-$\mu $ m CMOS Technology and Beyond | |
Le Guillou et al. | Implementation Aspects of Fractional-N Techniques in Cellular Handsets | |
CN115065361A (en) | Frequency synthesizer architecture for optimizing phase noise | |
Ziboon et al. | Design and Simulation of Sigma-Delta Fractional-N Frequency Synthesizer for WiMAX | |
Märzinger et al. | Fractional-N Phase Locked Loops and It’s Application in the GSM System |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20060306 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR |
|
DAX | Request for extension of the european patent (deleted) | ||
A4 | Supplementary search report drawn up and despatched |
Effective date: 20090325 |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H04L 27/10 20060101AFI20050404BHEP Ipc: G06F 5/06 20060101ALI20090319BHEP Ipc: H03H 17/06 20060101ALI20090319BHEP |
|
17Q | First examination report despatched |
Effective date: 20100129 |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: STMICROELECTRONICS, INC. |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN |
|
18W | Application withdrawn |
Effective date: 20151006 |