EP1665104A2

EP1665104A2 - Method for testing an electric circuit

Info

Publication number: EP1665104A2
Application number: EP04762738A
Authority: EP
Inventors: Peter Baader; Tilmann NEUNHÖFFER
Original assignee: Infineon Technologies AG
Current assignee: Qimonda AG
Priority date: 2003-09-12
Filing date: 2004-08-31
Publication date: 2006-06-07
Also published as: US20060230372A1; CN1849609A; WO2005026994A2; CN100458798C; US7636903B2; JP2007505295A; WO2005026994A3; DE10343344A1; DE10343344B4

Abstract

The invention relates to a method for testing an electric circuit, wherein exhaustive electric circuit modulation is not required yet circuit errors can be recognized in a reliable manner. According to the invention, a marking signal is produced, indicating a predefined circuit state which might occur in specific components of an electric circuit, wherein a transformed network list is formed from an original network list describing the circuit, whereby all electric components at least of one predefined component group, with regard to a respective connection pair, are treated as short-circuited, all network nodes connected by one or several components which are to be treated as short-circuited are respectively combined to form an equivalence category, wherein respectively all states of the associated network nodes are assigned to each equivalence category, it is possible to determine whether and in which components the predefined circuit state can occur by taking into account the equivalence categories. A signal which marks the identified components in the original network list is produced as the marking signal.

Description

description

Method for testing an electrical circuit

Electrical circuits, in particular integrated semiconductor circuits or semiconductor chips, are tested for functionality before they are manufactured in order to avoid the production of defective circuits or chips.

To check a circuit, circuit simulations are usually carried out in which the electrical behavior of the circuit is simulated. Circuit simulations are useful for identifying weak points in the design of the electrical circuit, but they have the disadvantage that the circuit behavior only for a given stimulus vector or a given stimulus set of input voltages and / or other parameters (e.g. Temperature, currents, etc.) is examined. A fault in the electrical circuit can therefore only be found if the respectively used stimulus vector or the used stimulus set of parameters demands the circuit in such a way that a design error contained in the electrical circuit occurs and becomes recognizable.

Another disadvantage of incoming circuit simulations is the relatively high computing time.

The invention is based on the object of specifying a method for checking an electrical circuit in which an in-depth electrical circuit simulation is not required and despite all circuit errors are reliably detected.

This object is achieved according to the invention by a method with the features according to patent claim 1. Beneficial ^'

Embodiments of the invention are specified in the subclaims. According to the invention, a method for generating a marking signal is provided, which indicates which components of an electrical circuit or which circuit areas of the electrical circuit could have a predetermined circuit state defined at least by a voltage potential or a logic state. In the method, a transformed network list is formed from an original network list describing the circuit structure of the electrical circuit, in that all electrical

Components of the electrical circuit of at least one predefined component group or at least one predefined component type are treated as short-circuited with respect to at least one pair of connections. All network nodes connected via one or more of the components to be treated as short-circuited - hereinafter also referred to briefly as "networks" - are each combined to form an equivalence class. An equivalence class is understood to mean a "fictitious" replacement network that includes all associated networks in the further simulation replaced. Each equivalence class is assigned all voltage potentials or logical states that could occur at one of the associated network nodes. Taking into account the equivalence classes formed in this way, it is then determined whether and with which components or with which circuit areas of the electrical circuit the predetermined circuit state can occur. A signal is generated as the marking signal which marks the components or circuit areas identified on the basis of the transformed network list in the original network list and thus makes them identifiable.

A major advantage of the method according to the invention is that it can be carried out very easily because the electrical circuit is checked using a “transformed” or simplified network list. The transformed network list is formed in that individual or multiple network nodes of the network list to an equivalence class. Considered graphically, an equivalence class is a new network or a new network node, which represents the "combined" network nodes or networks of the original network list. The combination of networks in equivalence classes simplifies the original network list, because there are fewer networks or Network nodes must be taken into account in the further test. In other words, the test is therefore carried out on a simplified "equivalent circuit". The essence of the invention is therefore to carry out the test of the electrical circuit using a transformed network list, which is simplified compared to the original network list.

Another essential advantage of the invention is that the transformed network list can be formed with little effort, since according to the invention only a given “rule” is simply applied to the original network list. Such a rule includes all electrical components at least one predetermined To treat component groups or at least one specified component type as short-circuited, this ensures that at least all network nodes which are connected via the correspondingly defined components can be combined to form an equivalence class.

In order to ensure that the marker signal actually defines a fault with a particularly high probability and does not represent a “false alarm”, it is considered advantageous according to a development of the method if, after the marking signal has been formed, it is checked or verified using the original network list, Whether the predefined — for example critical — circuit state can actually occur in the components marked by the marking signal or in the switching regions marked by the marking signal. Such verification can be carried out, for example, by a detailed simulation of the partial areas of the electrical circuit by the marked Part of the electrical circuit is simulated for itself in detail.

If it is established during the verification that the predetermined circuit state does not occur in the components or circuit areas marked by the marking signal, the marking signal is preferably corrected to form a corrected marking signal.

In order to avoid errors in the formation of the marking signal, it is considered advantageous to take so-called “stop nets” into account separately. “Stop nets” are understood to mean those network nodes or connection pins of the electrical circuit which have an electrical voltage potential, a current or a logical state is firmly assigned. Stop networks of this type must be excluded from inclusion in an equivalence class, since the assignment of potentials or states other than the permanently assigned potential or permanently assigned state would be inadmissible in the case of such a "stop network". A "stop network" can be established, for example, by an external connection or outer pin of the electrical circuit can be formed, to which a fixed potential - for example ground potential or supply voltage potential - is applied. In addition, “stop networks” can also be formed, for example, by voltage or current sources present in the electrical circuit, which predefine fixed voltage potentials or currents within the circuit on predetermined networks. Since stop networks are always assigned fixed potentials or states, these must not be included in an equivalence class.

If it is determined during the formation of equivalence classes that a “stop network” is present, the voltage potential, the current or the logical state of each of the “stop networks” is copied into each of the equivalence classes connected to the “stop network” Copy the potential or the state of the "stop network" only in one direction, namely in the direction of the equivalence class. A backward copying from the equivalence class to the "stop network" is excluded.

In order to avoid an electrical simulation of the electrical circuit, it is considered advantageous according to a further development of the method if all electrical components of the electrical circuit are treated component-individually with respect to each connection pair of the component either as short-circuited or as non-conductive. In this further development of the method, only a static "simulation" of the electrical circuit takes place, since the components of the electrical circuit are no longer simulated in detail, but are only treated as short-circuited or nonconductive. In the case of components with only two connections or In the case of components with multiple connections, the connection paths between all possible connection pairs are defined: for example, in the case of a component with three connections (e.g. transistor), AI, A2 and A3 are therefore for the Connections between the connections A1-A2, AI-A3 and A2-A3 each determine whether the connection path should be treated as short-circuited or as non-conductive. With three connections, three determinations are necessary. Accordingly, with a component with four connections (e.g. B. MOS transistor mi t substrate connection, thyristor) AI, A2, A3 and A4 thus determine for the connections between the connections A1-A2, A1-A3, A1-A4, A2-A3, A2-A4 and A3-A4 whether the connection path is short-circuited or should be treated as non-executive. With four connections, six definitions are required.

All transistors of at least one predetermined transistor type are preferably treated as short-circuited with regard to their switching path. Under the term "switching path" is understood the source-drain path in the case of a field effect transistor and the emitter-collector path in the case of a bipolar transistor. This configuration of the method takes into account the fact that the switching paths of transistors can usually be switched through, so that it can be assumed that a potential or state present at one connection of the switching path can also reach the other connection of the switching path. This fact is taken into account by treating the switching path as "short-circuited" when forming equivalence classes.

With regard to the treatment of resistors, it is considered advantageous if all resistors with a resistance value below a predetermined limit value are short-circuited and all resistors with a resistance value above the predetermined limit value are treated as non-conductive. This procedure takes into account the fact that with low-resistance resistors, a potential present at one connection of the resistor will, in a manner of speaking, “virtually unattenuated” or reach the other connection of the resistor unchanged. However, with high-resistance resistors there will be a significant voltage drop, so that a potential present at one connection of the resistor will not easily reach the other connection. In such a case, the resistor can simply be treated as "non-conductive".

Correspondingly, appropriate rules can be set up for any components of the electrical circuit, that is to say also for exotic "devices" or components, which state whether or under what circumstances the connection pairs of the respective components should be treated as short-circuited or as non-conductive.

The method according to the invention for generating the marking signal for such circuit states is preferably used. sets that are particularly critical and represent a circuit fault.

Errors in the circuit design can consist, for example, in that a predetermined limit voltage potential or a predetermined limit current is reached or undershot / exceeded at predetermined network nodes or that a predetermined logic state is reached. The marking signal is preferably generated accordingly when the predetermined limit voltage potential for the specified network nodes and thus for the specified equivalence classes is reached or undershot / exceeded or the corresponding network nodes reach the respectively predetermined logic state.

Incidentally, there may also be an error in the circuit design if a voltage is present at selected components that reaches or falls below or exceeds a limit voltage individually specified for the component. Accordingly, the marking signal is preferably generated when the state specified as critical for the specified components is reached or undershot / exceeded.

Limit voltages and limit states can be specified individually for each component; alternatively, however, it is also possible to specify appropriate limit voltages for all components of a given component type or component class and then to generate the marking signal for all those components of the assigned component type or component class that under / underlie the limit value specified for the component type or component class. exceed.

The method can be carried out particularly simply and therefore advantageously with a data processing system into which the circuit structure of the electrical circuit is entered as an original network list. In addition, the invention is based on the object of specifying a device with which an electrical circuit can be checked without an in-depth circuit simulation being necessary, although circuit errors should be reliably detected despite everything.

This object is achieved according to the invention by a device with the features according to claim 14. Advantageous embodiments of the device according to the invention are specified in the subclaims.

With regard to the advantages of the device according to the invention, reference is made to the above statements in connection with the method according to the invention.

A data carrier is also considered to be according to the invention which is provided with a program which is designed such that a data processing system carries out the method steps according to one of claims 1 to 13 after the program has been installed.

The invention is explained below using five electrical circuits as an example. Show:

FIGS. 1 to 7 show an exemplary embodiment of an electrical circuit without a “stop network”,

FIGS. 8 to 14 show an exemplary embodiment of an electrical circuit with a “stop network”,

FIGS. 15 and 16 show a further exemplary embodiment of an electrical circuit with a “stop network”,

Figure 17 shows another embodiment for an electrical circuit without "Stoppnet" and

Figures 18 and 19 with a third embodiment of an electrical circuit

"Stop net".

In the exemplary embodiment of the invention explained below, the electrical circuit is described with a network list. In principle, the network list can have any data structure. The data structure used here in the context of the exemplary embodiment has the following format:

typedef struct noderec / * data structure of a network in a cell * /

{netPinSetArray pinTypeSet; / * PinTypes of the network or the equivalent networks * / netPinSetArray origPin ypeSet; / * PinTypes in the original netlist * / netPinSetArray eqPinTypeSet; / * temporary for pin types in the equivalence ring * / struct noderec * equivalent; / * Ring chaining of equivalent nodes through short-circuited devices * / equiMasterRefRec * equiMaster; / * List of master networks of equivalent networks in different instantiations * / equiMasterPinTypeRec * equiMasterPin; / * for all equiMasters:

Pin types for equivalent networks * /

} typedef long netPinSetArray [PINSET_SIZE]; / * multiple pin types (such as VDD, IN,

OUT,. , , or different voltage levels can be saved * /

/ * Masternode in the instance instld * / struct equiMasterRefRec

{struct equiMasterRefRec * next; noderec * master; long instld; ;

/ * PinTypes of all equivalent networks of the master in the instance instld * / struct equiMasterPinTypeRec struct equiMasterPinTypeRec * next; netPinSetArray equiPinTypeSet; long instld;

} ^;

With this data structure, each network or network node contains a pointer which is designated by the word "equivalent". This pointer "equivalent" is used for the temporary ring chaining of all equivalent networks, that is to say all networks belonging to an equivalence class. Is an equivalence class a network, a so-called master, is selected in this class. Since the equivalence classes in a cell can differ from instantiation to instantiation, pointers to the respective master of the equivalence class to which the network belongs are saved for each instantiation of a cell in the equiMaster list for each network. The terms "equivalence ring" and "equivalence class" are used synonymously below.

The pin types of each equivalence ring are stored in the variable "equiMasterPin". Each network in the equivalence ring has such a pin type "equiMasterPin".

The pin type of each network is stored in the “origPinTypeSet” variable in the original network list. The “pinType-

Set "contains the pin type of the network that is valid in the current state of the network list, for example depending on which components of the electrical circuit are considered short-circuited or non-conductive.

On the basis of the data structure described for the networks in the network list, two separate recursive runs through the instances are required. The first of these two recursive runs is referred to below as step I and the second of the two recursive runs as step II. Two recursive runs are required because the network properties have to be transported through the hierarchy of the network list.

The steps are first explained in a general abstract form. The figures then show in detail how the steps are used.

In step I, the pin types of the individual networks are first passed "top-down" from top to bottom. Then the "bottom-up" equivalence classes are combined and the pin types are pushed up. In step II, the pin types are first passed "top-down" from top to bottom, this time already taking into account the pin types of the modified network list, ie the equivalence classes or rings of equivalence. Then "bottom-up" the tests with the modified one Network list carried out.

Steps I and II are carried out in detail as follows:

Step I:

Step I involves the recursive call of the functions for creating the equivalences for all instances. The following individual steps are carried out:

1.1. In this step, an instance-by-instance initialization is carried out before the hierarchical descent in top-down order. The pin types of the networks are passed down.

1.2. In this step, an instance-dependent structure of the equivalence classes takes place in a bottom-up order. The network list is supplemented by the concatenation of short-circuited components of the electrical circuit in equivalent rings or equivalent classes. The original network list remains unaffected. Starting from the original network list, only a corresponding reshaping or a corresponding "walk" over the equivalence rings has to be carried out in order to be able to access the modified network list. Alternatively, an independent modified network list can also be generated and stored in a corresponding manner.

1.2.1. For all components of the electrical circuit specified in a given rule file that are treated as short-circuited with respect to one or more connection pairs the related networks or network nodes are made equivalent and concatenated. This can be not only components in a cell, but also a cell itself, in which the associated pins are made equivalent. The term “make equivalent” is understood to mean that all states (potentials, logical states, etc.) of all the other network nodes of the assigned equivalence class are assigned to each network node.

If a network is a stop network on a component to be treated as short-circuited, the network is not included in the equivalence ring. Instead, the pin type of the stop net is copied into the equivalence ring; because the networks in the equivalence ring may accept the respective network properties, but they may not be transported unrestrictedly. By taking "stop nets" into account, the process becomes instance-dependent.

In the following, the * switching path - that is, the source-drain path - is treated as an example in the case of field-effect transistors and the base-emitter path in the case of bipolar transistors is treated as short-circuited. Resistors are considered shorted or non-conductive depending on the size of the resistance value.

1.2.2. In this step, a node is designated as the master for each equivalence class. All pin types of the equivalence ring are entered in this master. Such a network is preferably chosen as the master, which has a connection to a higher cell, for example to an external network or a pin. If there is no such network, any network of the equivalence ring is selected.

1.2.3. In this step, the "equiMasterPin" variable is created for all master networks and the temporary "equiPinTypeSet" variable of the master is assigned. 1.2.4. All networks in the parent cell that are connected via local equivalence rings in the current cell are chained in an equivalence ring. The variable "equiPinTypeSet" of a subnet is transmitted to the connected network in the parent cell.

Step II:

In step II, a recursive run through the hierarchy and a call of the check functions for all instances is carried out. The following individual steps per instance are processed one after the other:

II .1. The pin types of the equivalence classes are passed down into the instances top down.

11.2.1. The equivalence classes are updated by loading the data for the respective instance from the equiMaster list.

11.2.2. All tests are initiated bottom-up in the instance.

The method steps I and II explained in abstract, general form are now explained in detail with reference to the circuit examples shown in the figures.

1 shows two cells A, which are each formed by two transistors connected in series. Cell A on the left in FIG. 1 forms instance 1

(Instl) and cell A on the right in FIG. 1 is instance 2 (Inst2).

As can be seen in FIG. 1, each of the two instances 1 and 2 or the cell A has three networks Netl Net2 and Net3. Each of these networks Netl, Net2 or Net3 has a property that is referred to as El, E2 or E3 is. Such a property can be, for example, a pin type such as “VDD” (equal to supply voltage) or a different voltage, such as 2.8 V, for example.

Cell A is used twice as instance Instl and instance Inst2 in cell B. The cell B also has a transistor 10 which is connected to the networks Net11 and Net13. The four networks Netll, Netl2, Netl3 and Net14 also form connection networks between cells A and C. The cell C has the networks Net21, Net22, Net23 and Net24, which the cell B inserted in the cell C to the cell C. connect.

In FIG. 2, step I can now be seen for the instance Instl of cell A. The step is carried out in a bottom-up order. In this step, all the networks connected to the two transistors in cell A of the instance Instl are combined in an equivalence ring (step 1.2.1), since the two transistors in cell A are treated as short-circuited. The properties of the networks Netl, Net2 and Net3 are distributed to all networks in the equivalence ring. This means that each of the three networks Netl, Net2 and Net3 each have three properties, namely the properties E1, E2, E3.

3 shows how step 1.2.2 is carried out in detail. The two networks Netll and Netl2 are connected in cell B to the equivalence ring of cell A of the instance Instl. Therefore, the two networks Netll and Net12 come in an equivalence ring in cell B. The network properties of the previously formed equivalence ring of cell A of the instance Instl are transmitted from the network Netl to the network Netll; because the Netl network was previously selected as the master according to step 1.2.2. As a result, the network Netll now has the properties E1, E2 and E3. 4 shows the implementation of the corresponding steps for cell A of the instance inst2. This cell is also processed in a bottom-up order.

5 shows step I for cell B. It can be seen that the networks Netll, Net12, Net13 and Net14 are combined in an equivalence ring, as was explained above in connection with step 1.2.1. The network properties of these networks are transmitted to all networks in the ring of cell B.

The result shows that the networks Netl, Net2 and Net3 and the networks Netll, Netl2, Net13 and Netl4 can now each have the three properties E1, E2 and E3.

6 shows step 1.2.4 for cell B. The networks Net21, Net22, Net23 and Net24 are connected by the equivalence ring in cell B. The network properties of the equivalence ring in cell B are transferred from the network Net11, which was selected as the master according to step 1.2.2, to the network Net21. The network Net21 now has the properties E1, E2 and E3.

FIG. 7 shows the result of the equivalence class formation by transferring the network properties. All networks within cell C now have the properties E1, E2 and E3. The transformed network list formed by the equivalence class or by the equivalence rings can now be checked in accordance with test step II. The original net list is still available.

As a result, it can be ascertained that the assignment of network properties to networks shown in FIGS. 1-7 forms a transformed network list which is used for testing purposes and for generating a marking signal which marked the occurrence of a predetermined circuit state, can be used.

In the exemplary embodiment according to FIGS. 1-7, each of the networks of cell C could be assigned every property because none of the networks formed a so-called “stop network”. In connection with FIGS. 8-14, it is now explained how the method for Generation of a marking signal can be carried out, for example, in the case of electrical circuits whose so-called “stop networks” are to be taken into account in their network list.

FIG. 8 shows the same output circuit as in FIG. 1. The circuit according to FIG. 8 differs from the circuit according to FIG. 1 in that the network Net23 is now a "stop network". This means that the network Net23 has a network property, for example an electrical voltage potential, a current or a logical state is permanently assigned. The network Net23 cannot have properties other than the specified property. The network property of the network Net23 is referred to below as "EX". In step I, the network property EX is copied to the networks connected to the “stop network” Net23 via the hierarchy. This is shown in FIG. 8; FIG. 8 shows that the network property EX to the networks connected to the network Net23 Netl3 in cell B and Netl in instance Inst2 is copied from cell A.

9 and FIG. 10, the steps already explained in connection with FIGS. 2 and 3 in the first exemplary embodiment are carried out in a corresponding or identical manner. The stop network Netl3 does not yet play a role at this time. It can thus be seen that the networks Netl, Net2 and Net3 of cell A of the instance Instl are each assigned the network properties E1, E2 and E3. In addition, the Netl network is selected as the master. 11 shows step I for the instance Inst2 of cell A. The networks Net2 and Net3 applied to the lower transistor of the instance Inst2 are combined in an equivalence ring (cf. step 1.2.1). The properties of the networks Net2 and Net3 are distributed in the equivalence ring to the two networks Net2 and Net3. This means that the two networks Net2 and Net3 now have the properties E1, E2, E3 and EX. The Netl network is not included in the equivalence ring because it is a stop network. The network properties of the Netl network (these are the

Properties El and EX) have, however, been copied into the equivalence ring so that they are also present on the two networks Net2 and Net3.

12 shows step 1.2.4 for the instance Inst2 of cell A. The network properties of the equivalence ring of cell A of the instance Inst2 are transmitted from the network Net3, which was selected as master according to step 1.2.2, to the network Netl4. The network Net14 now has the properties E1, E2, E3 and EX. The network properties of the master network Netl are also transferred to Netl3. Since the network Netl3 is a "stop network", this network Netl3 is not included in an equivalence ring; only the network properties of the network Netl3 are transferred to the network Netll.

The result of the equivalence formation and transmission of the network properties is shown in FIG. 13. The networks Net21, Net22 and Net24 of cell C now have the properties E1, E2, E3 and EX. The Net23 stop network, on the other hand, only has the properties El and EX.

The final result of the equivalence formation is shown in FIG. In contrast to the first embodiment - cf. 7 - in particular, in which there was no stop network, there are now three master networks, ie three new equivalence classes or three that are not connected to one another "New" networks. The stop network Net23 and the networks Netl3 and Netl connected to it have not changed their original network properties. Nevertheless, the network Net23 has passed on its EX property to the other networks.

In summary, the method explained in connection with FIGS. 1-14 thus consists in converting an original list into a transformed network list, the original network list remaining unchanged. The existence of the original net list is important because the reference or the "cross reference" to the original net list should be retained when the error is output. The original net list is required, for example, for graphical "rehearsal" or "testing" In addition, the components and networks in which critical circuit states can occur should preferably always be reported in an original network list, since only the original network list is directly related to the actual circuit design.

In the newly formed modified or transformed

Network list, the network properties of the previous networks are adopted. Since several "old" networks are transferred to a "new" network, a new network can assume several different network properties (for example several voltages, several logical states, etc.). By forming the explained equivalence classes, the network properties can be transported or copied across various components of the electrical circuit.

The method described is therefore characterized in that all networks which are connected by components of the electrical circuit to be regarded as short-circuited are combined in equivalence classes. Each equivalence class represents a new logical or electrical network. The equivalence classes are formed across the respective circuit hierarchy. "Stop nets" are taken into account that are not included in the equivalence class be included. Instead, only the pin type of the stop network is copied into the respective equivalence class, which means that the pin types of all connected "stop networks" are known in the equivalence class. The equivalence classes of the subnets are also taken into account. This makes the method instance-dependent and no longer cell-dependent. This means, for example that the same cell in different instances can be wired differently.If these are stop nets that cannot be included in an equivalence class, this is taken into account when transmitting the properties of networks.

An advantage of the method explained is the possibility of quickly transforming a network list according to the requirements in a separate “rule file” or in a separate rule file into another and using this transformed network list for the static check of electrical properties.

If - as described in connection with the examples according to FIGS. 1 and 14 - all components are considered to be short-circuited or non-conductive when carrying out the method, a complete static check of the electrical properties of the electrical circuit can be carried out using the transformed network list. Such a static check of the electrical circuit has a significantly higher speed and a significantly better test coverage than would be possible with a dynamic, detailed electrical simulation of the electrical circuit. Due to the "cross reference" to the original list, it remains possible to assign detected errors to the circuit areas of the circuit concerned. The described method can also be used for hierarchical network lists.

In connection with FIGS. 15 to 19, it will now be explained by way of example how the transformed or modified network list can generate a marker signal.

15 shows five MOS transistors NMOS1, NMOS2, NMOS3, NMOS4 and NMOS5. A switching path connection (ie source or drain connection) of the transistor NMOS5 is connected to a network node or to a network with the designation P2. Another connection of the transistor NMOS5 is connected to a network B, to which a switching path connection of the transistor NMOS4 is also connected. The other switching path connection of the transistor NMOS4 is connected to a switching path connection of the transistor NMOS2 and to a network A. The other switching path connection of the transistor NMOS2 is connected to a switching path connection of the transistor NMOS1 and to a network P1. The other switching path connection of the transistor NMOS1 is electrically connected to a switching path connection of the transistor NMOS3 and to a network C. The other switching path connection of the transistor NMOS3 forms a network D.

An electrical state variable is permanently assigned to the two networks or network nodes P1 and P2, namely the supply voltage VDD to the network P1 and the ground potential VSS to the network P2.

In addition, the five transistors NMOS 1 to NMOS 5 are treated as short-circuited. The fixed assignment of the electrical state variables for the two networks P1 and P2 and the treatment of the transistors NMOS1 to NMOS5 as short-circuited can be achieved, for example, using the following programming instructions:

ercDefines (de f Pins (pin "VSS" = "P2" pin "VDD" = "Pl" shortDevices (

Short "MOS" excludingPinTypes "VSS" "VDD")

)

Because the five transistors NMOS1 to NMOS5 are treated as short-circuited, the voltage potentials VDD and VSS on the two networks Pl and P2 can now be assigned to all those networks which are connected to the networks Pl and P2 via the transistors.

However, it must be taken into account that the two networks P1 and P2 have permanently assigned electrical potentials, namely the potentials VDD and VSS, so that these two networks P1 and P2 are to be understood as so-called “stop networks”.

This means that the potential VSS on the network P2 reaches or is "propagated" to the network B via the transistor NMOS5 to be treated as short-circuited and to the network A via the transistor NMOS4 to be treated as short-circuited and B thus each assigned the potential VSS. In a corresponding manner, the potential VDD from network P1 will reach network A via the transistor NMOS2 to be treated as short-circuited and to network B via transistor NM0S4 to be treated as short-circuited B assigned the two potentials VSS and VDD.

As can be seen in FIG. 16, however, there is no assignment of the potential VDD to the network P2 and likewise no assignment of the potential VSS to the potential P1. This is due to the fact that the two networks P1 and P2 form “stop networks”, to which an electrical state variable is permanently assigned. In the example according to FIGS. 15 and 16, how is Executed above - the potential Pl VDD and the network P2 the potential VSS permanently assigned to the network Pl.

In a corresponding manner, the potential VDD is now assigned to the network C via the transistor NMOS1 treated as short-circuited. The potential VDD can or must also be assigned to the network D, since the transistor NMOS3 is also to be treated as short-circuited.

The result is an assignment of voltage potentials, as shown in FIG. 16. This means that the two networks A and B are each assigned the potentials VSS and VDD and the two networks C and D are each assigned the potential VDD. The two networks P1 and P2 retain the potentials VDD and VSS that are permanently assigned to them, since they are stop networks. So the following applies:

Pl: VDD

P2: VSS

A: VDD, VSS

B: VDD, VSS

C: VDD

D: VDD

Networks C and D on the one hand and networks A and B on the other hand therefore each form an equivalence class.

The electrical circuit according to FIGS. 15 and 16 can now be checked to determine whether a predetermined circuit state, at least defined by an electrical state variable, has been reached. This is to be illustrated using an example in which a marking signal (or test signal) is output for all those nodes which have no connection to the potential VDD or no connection to the potential VSS. A corresponding query in a programming language could be as follows: ercRules (reportNet (pinTypes condition count "VSS""VDD"<= 1 title "No path to VDD or no path to VSS"))

As can be seen in FIG. 16, networks P1, P2, C and D are reported. The networks P1 and P2 are reported because they are stop networks and cannot assume any other potential. Networks C and D are reported because they cannot assume the potential VSS. A test signal is therefore generated.

Another test request could be, for example, that all networks or network nodes that may be at the potential VSS should be output. The corresponding search or A test request in a programming language could be as follows:

ercRules (reportNet (pinTypes condition including "VSS" title, "path to VSS")

The result of this test request would be that networks A and B and P2 can have the potential VSS. As mentioned above, the potential P1 cannot have the potential VSS because it is a stop network. Correspondingly, the two networks C and D cannot have the potential VSS either, since they are only supplied with the potential VDD via the stop network P1. FIG. 17 shows the exemplary embodiment according to FIGS. 15 and 16 in a modified form. In the electrical circuit according to FIG. 17, the potential VDD is also assigned to the network P1 and the potential VSS to the network P2. In contrast to the exemplary embodiment according to FIGS. 15 and 16, however, this is not a fixed assignment, so that the two networks P1 and P2 do not form stop networks. Thus, in addition to the previously assigned potentials VDD and VSS, the two networks P1 and P2 can also be assigned other, other potentials. The definition of the pin assignment or pin types of the networks and short-circuiting can be defined, for example, by the following program lines:

ercDefines (de f Pins (pin "VSS" = "P2" pin "VDD" = "Pl"

shortDevices (

Short "MOS")

If the method explained in connection with FIGS. 15 and 16 is now used here, the VSS assigned to the network P2 will reach the network B via the transistor NMOS5 treated as short-circuited and from there to the network A via the transistor NMOS4 treated as short-circuited , In addition, the potential VSS will be able to reach the network P1 via the transistor NM0S2 treated as short-circuited, since the network P1 no longer forms a stop network. The potential VSS then arrives from the network P1 via the transistor NMOS1 to the network C and from there to the network D via the transistor NMOS3. The potential VSS can thus be applied to all networks P1, P2, A, B, C and D. In a corresponding manner, the potential VDD is now also assigned to the networks A, B, C and D - as already in the exemplary embodiment above - and also via the transistor NMOS5 to the network P2, since the network P2 likewise no longer forms a stop network.

As a result, all networks can have both potentials VSS and VDD. So the following applies:

Pl: VDD, VSS

P2: VDD, VSS

A: VDD, VSS

B: VDD, VSS

C: VDD, VSS

D: VDD, VSS

The networks P1, P2, A, B, C and D thus form an equivalence class.

A fifth electrical circuit is shown in FIGS. 18 and 19, by means of which the implementation of the test or marking method is explained below.

One can see in FIG. 18 a “small” n-channel MOS

Field effect transistor NMOS SMALL, which is connected with its one switching path connection - the source connection - to the network P5. The potential VSS is present at the network P5. The gate of the transistor NMOS SMALL is at P4 with the potential VINT. The other switching path connection - the drain connection - of the NMOS SMALL transistor is connected to a switching path connection - the drain connection - of a "small" p-channel MOS field-effect transistor PMOS SMALL. The other switching path connection - the source - Connection - the transistor PMOS SMALL is connected to a network P2 to which the potential VINT is present. The gate connection of the transistor PMOS SMALL is connected via a resistor R to a switching path connection of a “large” p-channel MOS field-effect transistor transistor PMOS BIG, the other switching path connection of which is connected to the network Pl. The gate connection of the transistor PMOS BIG is connected to a network P3 which is supplied with the potential VSS.

The networks P1, P2, P3, P4 and P5 are stop networks which can only have the potential assigned to them.

All resistors of the electrical circuit that have a resistance value greater than 500 Ω should be regarded as non-conductive, whereas all other resistors with a resistance value less than or equal to 500 Ω should be ideally or losslessly conductive. Accordingly, the resistor R is treated as short-circuited.

The corresponding assignment of the potentials for the networks Pl,

P2, P3, P4 and P5 and the definition of the electrical behavior of the components can be achieved using the following programming rules, for example:

/ * Assignment of pin types and voltages * / ercDefines (defPins (pin "VSS" vol days 0 = "P5" "P3" pin "VINT" vol days 2. 0 = "P2" "P4" pin "VPP" vol days 3 . 0 = "Pl"

)

/ * Definition of the devices via which the voltage is to be transported and the stop networks * / shortDevices (

Short "MOS" BIG Short "MOS" SMALL Short "RES" value = <500 excludingPinTypes "VPP""VINT""VSS")

The circuit shown in FIGS. 18 and 19 is now to be checked to determine whether an excessively high voltage can occur in the small p-channel transistor PMOS SMALL. The p-channel transistor PMOS SMALL is a transistor in which no voltage greater than VINT may be present between the gate connection and the source or drain connection. According to the definition given above, the voltage VINT = 2 volts.

To carry out the test, it must first be determined which network node or which networks the electrical

Switching which potentials or states have to be assigned. To do this, proceed as follows:

First, it is determined that the network P2 is a stop network, so that this network P2 is only that

VINT potential. However, the potential VINT can reach the network A via the transistor PMOS SMALL, which is to be treated as short-circuited with regard to its switching path or its source-drain connection pair. In addition, the potential VSS can also be assigned to network A, since the transistor NMOS SMALL can also be regarded as short-circuited with regard to its switching path or its source-drain connection pair.

The potential VPP on the network P1 passes through the transistor PMOS

BIG, which is to be treated as short-circuited with regard to its switching path or its source-drain connection pair, to the network B. ^' Since the resistor R only has a resistance value of R = 100 Ω, this resistor is short-circuited in accordance with the rule mentioned above to watch; thus the potential VPP can also be assigned to the network C and thus to the gate connection of the transistor PMOS SMALL. An assignment of the potentials, as shown in FIG. 19, is thus formed.

It can thus be ascertained that the potentials VSS and VINT can occur at the network A and thus at the drain connection of the transistor PMOS SMALL and the potential VPP can occur at the network C and thus at the gate connection of the transistor PMOS SMALL.

The electrical circuit is now to be checked to determine whether the “small” p-channel transistor PMOS SMALL has a gate-source voltage or a gate-drain voltage that is greater than VINT look like this:

/ * Test rule * / reportDevice ("MOS" modeis SMALL condition nodeVol days (vol days "GATE" - vol days "SDRAIN"> "VINT") | | nodeVol days (vol days "SDRAIN" - vol days "GATE"> "VINT") title "SMALL MOS, vol tage difference Ga te- Source / Drain / Substrate> VINT")

According to this check, it is checked whether there are “small” MOS field transistors in which a voltage is present between the gate connection and the source or drain connection that exceeds the voltage limit of VINT = 2 V.

The solution to this test request can be seen directly in FIG. 19; because it is shown in FIG. 19 that between the drain connection and the gate connection of the small p-channel transistor PMOS SMALL there is a gate-drain voltage Ugd of Ugd = VPP - VSS = 3 volts and

Ugd = VPP - VINT = 1 volt

can concern.

If the gate connection is supplied with the potential VPP, a voltage difference of Ugd = 3 V> 2 V can form between the gate connection and the drain connection. The specified limit voltage or maximum voltage difference of Ugd = VINT = 2 V is thus clearly exceeded.

The small p-channel transistor PMOS SMALL would be reported as a result of the test request mentioned. The electrical circuit according to FIGS. 18 and 19 is therefore not sufficiently dimensioned. Instead of the small p-channel transistor PMOS SMALL, a "large" p-channel transistor PMOS BIG would have to be used, since with a MOS transistor of the type

"BIG" a voltage difference of VDD between gate and source or gate and drain connection would not be critical.

Instead, the electrical circuit according to FIGS. 18 and 19 could also be modified differently, for example by increasing the resistance value of the resistor R. If the resistance value of the resistor R had a value greater than 500 Ω, the potential VPP would not be "propagated" via this resistor R to the gate connection of the small p-channel transistor PMOS SMALL, so that none on the transistor Overvoltage would occur and the transistor would then not be reported.

The test method described can also take into account other parameters of the electrical circuit. For example, a query as to whether a predetermined limit voltage is exceeded at a transistor can also be carried out can be connected with geometric parameters of the transistor. For example, all those “small” p-channel transistors can be found using the test method described, in which there is a voltage difference between the source connection and the drain connection which is greater than VINT and whose gate length is less than 280 nm. A corresponding test request could be, for example, as follows:

reportDevice ("MOS" modeis P_SMALL condition length <280 && nodeVol days (vol days "SDRAIN"> "vint") && nodeVol days (vol days "SOURCE" - vol days "DRAIN">

"vint") title "Small PMOS, length <280, vol days SOÜRCE-DRAIN> vint")

As a result, a complete check of electrical circuits can be achieved in a very simple manner with the described method, without the need for a complete electrical simulation of the circuit.

Claims

claims

1.Method for generating a marking signal, which indicates which components of an electrical circuit or in which circuit areas of the electrical circuit a predetermined circuit state could occur, at least defined by a voltage potential or a logical state, in which the circuit structure of the electrical circuit original network list describing the device, a transformed network list is formed by treating all electrical components of the electrical circuit of at least one predetermined component group or at least one predetermined component type as short-circuited, at least with respect to one pair of connections, all via one or more of the short-circuits to be treated Components connected network nodes are combined into an equivalence class, with each equivalence class all

Voltage potentials or logical states of the associated network nodes are assigned, taking into account the equivalence classes, it is determined whether and with which components or in which circuit areas of the electrical circuit the predetermined circuit state can occur, and as the marking signal a signal is generated which is based on the transformed network list identified components or circuit areas marked in the original network list.

2. The method according to claim 1, characterized in that it is subsequently verified on the basis of the original network list whether the predetermined circuit state can actually occur in the marked components or in the marked circuit areas.

3. The method according to claim 2, characterized in that the marking signal is corrected with respect to those components and circuit areas to form a corrected marking signal in which the verification shows that the predetermined circuit state is excluded.

4. The method according to any one of the preceding claims, characterized in that - those network nodes or connection pins of the electrical circuit, to which an electrical voltage potential or a logical state is permanently assigned, are excluded from inclusion in an equivalence class.

5. The method according to claim 4, characterized in that the voltage potential or the logic state of each network node with a permanently assigned voltage potential or logic state is copied into each of the equivalence classes respectively connected to the network node.

6. The method according to any one of the preceding claims, characterized in that all the electrical components of the electrical circuit are treated component-individually with respect to each connection pair of the component either as short-circuited or as non-conductive.

7. The method according to any one of the preceding claims, characterized in that all transistors of at least one predetermined transistor type are treated as short-circuited with regard to their switching path.

8. The method according to any one of the preceding claims, characterized in that all resistors with a resistance value below a predetermined limit value are short-circuited and all resistors with a resistance value above the predetermined limit value are treated as non-conductive.

9. The method according to any one of the preceding claims, characterized in that a circuit state critical for the circuit, in particular for several critical switching states, is selected as the predetermined circuit state and the method for the critical circuit state, in particular for several critical switching states, is carried out.

10. The method according to any one of the preceding claims, characterized in that the marking signal is generated for those network nodes or equivalence classes that reach or fall below / exceed a predetermined limit voltage potential or reach a predetermined logical state.

11. The method according to any one of the preceding claims 1 to 9, characterized in that the marking signal is generated for those components in which a voltage is present which reaches or falls below or exceeds a limit voltage individually specified for the component.

12. The method according to any one of the preceding claims 1 to 9, characterized in that the marking signal is generated for those components for which a voltage is present which reaches or falls below or exceeds a predetermined limit voltage for the respective component type.

13. The method according to any one of the preceding claims, characterized in that the method is carried out with the aid of a data processing system, in which the circuit structure of the electrical circuit is entered as an original network list.

14. Device for generating a marking signal, which indicates which components of an electrical circuit or which circuit areas of the electrical circuit a predetermined circuit state, defined at least by a voltage potential or a logical state, could occur with a memory in which an original network list describing the circuit structure of the electrical circuit is stored, and a computer device connected to the memory and configured in such a way that it forms a transformed network list from the original network list by treating all electrical components of the electrical circuit as short-circuited for at least one predefined component group or at least one predefined component type - all via one or more of the network nodes to be treated as short-circuited summarizes an equivalence class, whereby it assigns all voltage potentials or logical states of the associated network nodes to each equivalence class,

- that, taking into account the equivalence classes, it determines whether and with which components or in which circuit areas of the electrical circuit the predetermined circuit state can occur, and - that it generates as the marking signal a signal that identifies the components or circuit areas identified in the 0- riginal netlist marked.

15. Device according to claim 14, characterized in that the computer device is designed such that when the marking signal is generated, it carries out at least one of the method steps according to one of the preceding claims 2 to 13.

16. Data carrier with a program that is designed such that a data processing system after an installation tion of the program carries out the method steps according to one of claims 1 to 13.