JPH0652253A - Method and device for simulating circuit - Google Patents

Abstract

PURPOSE:To simulate a circuit operation corresponding to the state variation of an operation power source without necessitating a precise modeling of element by using a state of the operation power source as input information. CONSTITUTION:In a simulation method for inputting configuration information of an object circuit, storing the specification of a component configurating the circuit and executing a processing in accordance with a prescribed procedure based on the configuration information and storage information, a function model of the circuit is generated 7 from a relation satisfied between input and output signals of the circuit, a simulation model integrating information of an operation power source into the function model of the circuit is generated 11, logical input data 12 and timewise variation data 3 of the operation power source are inputted to the generated model, and while operating the simulation model at an arbitrary time point, the operation of the circuit is simulated. In such a way, a circuit operation by a state of the operation power source can be simulated simply and efficiently, and a pattern of a bus accident can be evaluated in advance from a circuit design diagram.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulation of a circuit operation which is influenced by the state of an operating power supply in addition to an input signal, and in particular, an operation of an electric circuit including a relay sequence circuit, a transistor circuit and a logic circuit. A method and an apparatus thereof.

[0002]

2. Description of the Related Art In designing electric circuits for measurement and control such as relay sequence circuits and transistor circuits, in addition to verifying whether or not the designed circuit achieves the intended function, If there is something wrong with the control power supply, which is the power supply for operating the device, it is also verified whether or not an output that adversely affects the system is generated. When these electric circuits are designed by paying attention to only the functions to be realized by the circuit, the operation at the time of turning on the operating power supply and the operation at the time of loss of the operating power supply may not be considered. As a result, there is a risk that the circuit will output an abnormal signal until the power supply becomes stable. Also, when considering the change at the time of turning on and off of the operating power, the circuit that lost the operating power seems to not generate the output at first glance, but it is guaranteed that the operating power supply instantly outputs the voltage. Only when lost. However, the power supply bus voltage at the time of an actual accident does not instantly become 0, and it attenuates depending on the non-linear element in the circuit, and the electromotive force is generated by the motor etc. due to the influence of the non-linear element and the voltage drop of the power bus There is something to do. In such a case, the circuit may momentarily generate an unexpected output signal, causing the controlled object to operate improperly. By the way, conventionally, the verification at the design stage of electric circuits such as an instrumentation circuit including a relay sequence circuit and a transistor circuit, a control circuit, etc. has been mainly conducted on a desk by an expert.
In the study on the desk, the circuit range that can be considered is limited to a very small one, and the change of the bus voltage assumed at the time of a bus accident is also limited to the typical case where the voltage instantly becomes zero. Therefore, when the system becomes large-scale, verification of these circuits at the design stage exceeds human ability, and a situation in which a defect cannot be found occurs. After a circuit is actually manufactured, a voltage is applied and a test is performed, but it takes a large cost to correct the defective portion found here. In addition, when modifying a system that is always in operation, it is almost impossible to perform a test that covers the entire operating unit. In LSI design, the entire problematic circuit is described in terms of electrical characteristics at the element level, and the transient response is analyzed by performing circuit simulation. Recent researches in the field of LSI include “Development of functional simulation model of CMOS memory” (Hayashi et al.
-A No. 12 1774-1785 p), a circuit simulator that solves nonlinear simultaneous equations by a numerical solution method has proposed a simulation model with a description of a function level one step further.
Accurate understanding of circuit impedance is essential. The operation at the time of loss of the operating power supply in the electric circuit such as the instrumentation circuit including the relay sequence circuit and the transistor circuit, and the control circuit, and the operation at the time of turning on can be regarded as the transient response like the LSI. In order to simulate a bus accident by circuit simulation, not only the relay sequence circuit and the transistor circuit, but all the elements connected to the bus are correctly modeled, and
It is necessary to consider the type of cable used in the circuit and the line capacity depending on the wiring length. Unlike the semiconductor LSI, the circuit in question has an extremely wide range of circuits to be electrically coupled. Moreover, the wiring uses many kinds of cables, and the wiring length sometimes reaches several hundred meters. As a practical matter, it is almost impossible to accurately calculate these at the design stage.

[0003]

In consideration of the above points,
In order to verify the logical operation of electrical circuits such as instrumentation circuits such as relay sequence circuits and transistor circuits, control circuits, etc. at the design stage, the circuit operation at the time of power supply abnormality is simulated based on the information in the design drawing. Methods and equipment are needed. An object of the present invention is to provide a circuit simulation method and apparatus for simulating the operation of a circuit associated with a change in the state of the operating power source, without requiring strict modeling of elements, using the state of the operating power source as input information. Especially.

[0004]

The above object is achieved by simulating the behavior of the circuit by using the change data of the power source connected to the circuit to be simulated and the logic data input to the circuit. . In addition, a functional model of the circuit is generated from the relationship established between the input / output signals of the target circuit, a simulation model in which the information of the operating power supply is incorporated into the functional model of the circuit is generated, and a logical input is made to the generated model. This is achieved by inputting data and time-varying data of an operating power supply and simulating the behavior of the circuit while operating a simulation model at an arbitrary time point.

[0005]

The functional model of the circuit is a model composed of devices that operate as logic elements when the operating power supply is normal, and an ideal logic gate derived from the connection relationship between these devices. By using the functional model of this circuit,
For devices that do not correspond to logic elements such as resistors and diodes included in a large number of relay sequences or transistor circuits, modeling of the electrical characteristics required for general circuit simulation is unnecessary, and the effects of nonlinear elements on the logic operation are eliminated. By replacing and with the delay time due to the time constant and the like, it is possible to model with only simple logical operations. The model obtained by this is simulated by referring to the state of the power supply bus voltage and rewriting the model according to whether or not normal operation of the circuit is possible. It is possible to simulate the behavior of an electric circuit that cannot operate uniformly.

[0006]

EXAMPLE A first example of the present invention will be described below. FIG. 1 shows an embodiment of the configuration of the simulation apparatus according to the present invention. This simulation device (1) receives the circuit data (2), the logic input data (12) for the circuit, and the bus voltage aging data (3) as inputs, and simulates the aging of the circuit output value at the time of a power bus accident, The result is displayed (4a) or printed (4b)
Output. In order to interpret the sequence diagram, the simulation device (1) uses a knowledge base (5) regarding the operation of each circuit element as a logic element and what equipment the symbol in the circuit indicates, and the impedance in the sequence diagram. A circuit element specification database (6) for selecting an appropriate default value when the specification of the element such as a value is missing is held in advance. The outline of the simulation process is shown in FIG. For a drawing to be simulated, a functional model is generated from the relationship between input signals, and information on the operating power supply of each element is incorporated into this to generate a model for simulation. The logic input data and the operating power supply information are given to this to perform simulation.

Here, a simulation of a relay sequence circuit will be described as an example. The outline of the processing of the functional model generation means (7) of the circuit is shown in FIG. The model generation means (7) interprets the operation as a logic circuit from the given circuit data and generates a functional model of the circuit. There are only two kinds of signal values that can be taken by the logic circuit, that is, a logic value 0 or 1. In the processing, first, a judgment is made based on the knowledge base (5), and a circuit element whose operation as a logic element is always interpreted as 0 is removed (processing 21). Further, the element which is always interpreted as 1 is erased from the circuit and the terminals on both sides are short-circuited (process 22). With respect to the remaining elements in this way, an equivalent logic gate circuit is generated from the connection relationship with those logic operations (process 23). Further, in order to consider the circuit operation in millisecond units, a delay element corresponding to the delay time when the contact of each relay operates is inserted in the connection line corresponding to each contact between the logic gates ( Process 24) is a functional model of the circuit in a state where the operating power supply is normal. For example, given a sequence diagram as shown in FIG. 4, if the resistor (31) does not have an extremely large resistance value written from the interpretation rule stored in the knowledge base (5), Always interpreted as 1. Therefore, the resistor (31) itself is removed from the circuit and the terminals on both sides are shorted to replace the mere wiring. Condenser (32), Lamp (33)
Is also removed from the circuit as always 0, but both ends are left open. In this way, the paths from all the relay coils X, XX, Y on the simplified sequence diagram to the power bus (34 to 37) are searched for, and the contacts C1,
According to the connection relationship with C2 and C3, an equivalent logic gate circuit, for example, the circuit of FIG. 5 is converted.

Further, with the data of the same sequence circuit as input, the relay operation / bus voltage relationship table generating means (8) generates information relating the availability of the relay operation and the bus voltage. FIG. 6 shows an outline of the processing of the relationship table generating means (8). In the relation table generation, first, an element that performs a logical operation such as a relay coil is selected from the sequence diagram (process 51). For each of them, the bus bar that supplies the operating power is identified (process 52), the path from the coil to the bus bar is searched, and the impedance of the device on the path is calculated (process 53). Here, assuming that the resistance of the relay contact can be ignored, only the impedances of other relay coils and resistors provided especially for voltage division are considered. The voltage required for the operation of the relay is retrieved from the specification database (6) (process 54). Process the bus voltage Vth required to apply a voltage at which the relay can operate 5
Calculated from the values obtained in steps 3 and 54 (process 55), a relay id, which is an identifier assigned to each circuit element, and a busbar i, which is an identifier of a power source busbar to which the relay coil is connected.
Along with d, it is registered in the relationship table (process 56). For example, as shown in FIG. 7, for the relay Y (61) that is one of the relay ids, the identifier Bus-No-2 (62) of the 24V bus to which the relay is connected is calculated as the minimum required voltage. The value 20V (63) is registered in the table.

The model change information setting means (9) based on the bus voltage adds information for rewriting the circuit model due to the bus voltage change from the information in the relation table. From this information and the functional model, the logic simulation model generation unit (11) generates a simulation model considering the change over time of the bus voltage. The outline of the processing here is shown in FIG.
FIG. 9 shows an example of the simulation model to which the rewriting information is added. First, for all the relays registered in the relation table, a changeover switch (81) is provided between the gate corresponding to the coil and the gate to which the output signal propagates.
Is inserted (process 71). In the initial state, the changeover switch connects the gate corresponding to the relay and the propagation destination of the output signal thereof. The other terminal of the changeover switch is connected to the gate (82) which always outputs 0 (process 72). After inserting the changeover switch, for each power supply bus used in the circuit, generate a switch changeover signal according to the voltage change over the limit value of the operable power supply voltage of each relay registered in the relation table A signal generation source (83a, 83b) for generating is generated (process 73). The generated signal source and the changeover switch are wired according to the relation table (process 74). Naturally, the operating power supply is obtained from the same bus, and the changeover switch added to the relay having the same limit value of the operating power supply voltage is wired from the same signal generation source.

Based on the simulation model generated in this way, logic input data (1
The simulation is executed by inputting 2) and bus voltage change data (3). The simulation is executed in the logic simulation execution unit (10). Input signal of the original sequence circuit (84 to 86)
As the input data corresponding to the above, logic input data such as a condition when an output should not be generated at the time of a bus accident is selected in consideration of the intended logic of this circuit and is input from a key board or the like. The outline of the processing of the logic simulation execution unit (10) is shown in FIG. For example, in the case of the model of FIG. 9, first, the signals of the preselected combination are set to the input terminals (84 to 86) (process 91). Next, the signal source (83
a, 83b) read the time-dependent change data (process 9)
2). An example of time-dependent change data is shown in FIG. If the power bus is healthy (101), the signal source does not generate a signal through the simulation. On the other hand, when the bus voltage changes due to the accident (102), the voltage transitions across the limit values 80V and 60V set in the relation table.
The model will be switched to 0 ms, 15 ms, 100 ms, and 140 ms. Here, it is assumed that both the 100V bus and the 24V bus are sound as the initial state of the power bus. If the bus bar is healthy, it has no input terminal and is always 0.
Since the 0 output gates that continue to output are all disconnected from the circuit, the 0 output gates are ignored and the setting value of the input terminal is propagated in the circuit to determine the initial value of each gate (process 93). After the initial setting is completed, the behavior of the circuit is simulated. The time management during the execution of the simulation follows the time wheel. Changes in the signal value that occur at any point in the circuit are registered in the time wheel in chronological order, and the state of the signal in the circuit is changed each time the signal value change is registered in the process of advancing the time wheel. It is a thing. Here, first advance the time of the simulator from time 0 to where the propagation signal is registered in the time wheel,
During that time, if the bus voltage transits across the limit value (Processing 9)
4) Switch the corresponding switch. When the simulation is performed with the voltage change in FIG. 11, first, the switch (87) corresponding to 80 V is switched at time 10 ms (process 95), and the signal 0 is registered as an input signal to XX-1 at 10 ms on the time wheel. (Process 9
6). This signal is processed in the next step and registered as an input for X (process 97). Since XX-1 is a delay element, its output signal is registered in the time wheel at a time obtained by adding a time corresponding to the operation delay of the contact to 10 ms. Now, assuming that the operation delay of the relays X and XX is 20 ms, the registration to the time wheel is 30 ms. next,
Since the unprocessed signal is registered in the time wheel,
The process returns to (process 94) again (process 98). In this way, the model switching due to the change in the bus voltage and the change in the signal value in the circuit are calculated in chronological order, and if there is no signal to be propagated finally, the simulation ends. here,
In the circuit of FIG. 4, consider a simulation in the case where the contacts C1 and C2 are open and C3 is closed, and a power failure accident of 100 V bus is assumed. The output of relay X before the bus accident is zero. In general, when considering a pattern of instantaneous blackout to 0V as in the case of desk examination, the relay X loses its operating power immediately after the accident and does not generate an output. However, in the simulation assuming the state change of FIG. 11 by the method according to the present invention, the relay X becomes operable by the operating power supply voltage which reaches 60V or more by temporary recovery 100 ms after the occurrence of the bus line accident, and the operating power supply The contact of the relay XX, which has been restored due to the loss of the current, has the result that the relay X is excited and continues to be excited until 140 ms after the operating voltage is lost again. Now, it is assumed that the output signal of the relay X is the input signal of another circuit S (not shown) which is not affected by the accident. From a desk study, it can be determined that the circuit S side is not affected because the output 0 does not change due to a power failure. However, in reality, assuming a state change of the operating power supply as shown in FIG. 11, a pulse signal may be input to the circuit S for 40 ms, which may cause an operation outside the design. it can.

FIG. 12 shows a display example of the simulation result. The simulation result is displayed on the CRT screen together with the target relay circuit and a graph showing the change over time in the bus voltage. In the simulation target relay circuit (150), the 100V bus that is in an unsteady state is displayed in a different color, for example, from a healthy 24V bus. Data of time-dependent change of input bus voltage (151)
Displays the entire waveform in advance, and displays it by changing the color and the brightness in the time range in which the simulation is completed as the time progresses on the simulator. In synchronism with this graph of the time-dependent change in bus voltage, the coil of the relay or its contact that is inoperable at that time is displayed in a different color from that of a healthy device, and the output of the circuit is displayed. The value graph is also displayed in synchronization. This display may be displayed in parallel during the execution of the simulation, but it is easy to see by collecting the information necessary for the display in the course of the simulation, and editing and displaying at an appropriate speed after the completion of the simulation. In the above embodiments, the effect of wiring is simulated as 0 and the limit value of the operating voltage of each relay is calculated. However, some line impedance may be added as a default value to the calculation conditions. You may add it interactively if you can grasp the stray capacitance etc. by the cable used. Further, the logical simulation model can be easily realized as hardware. If the model is realized by hardware and simulation is performed, a faster simulation device can be realized.

Next, a second embodiment of the present invention will be described.
FIG. 13 shows an embodiment in which a symbolic simulation (111) is used as a logic simulation method. The generation of the logical simulation model and the setting of the relationship table between the operating power supply voltage and the operable range of the relay are the same as those in the first embodiment. By introducing the symbol into the simulation, it is not necessary to prepare analog data or data in which the exact change time is recorded as the time-dependent change data of the power source bus voltage, and instead, a model waveform of the rough change of the bus voltage with time (112). , And the change time and voltage value can be expressed by variables. For example, in FIG.
Instead of the data (102) specified in
Type, initial voltage V ₀ 105 V or higher, minimum voltage drop V ₁₄
0 V or less, maximum value V ₂ 70 V or more ”or“ time t ₀ <
For t ₁ <t ₂ <t ₃ , the voltage value V (t) at time t is
V (t ₀ )> 105V, V (t ₀ )> V (t ₂ )> V
(T ₁ )> V (t ₃ ), V (t ₃ ) = 0 ”, and the like. Further, in the first embodiment, the logical input data designated by the user from the keyboard or the like can be generated from the circuit data as a symbol string. For example, in the case of the circuit of FIG. 4, the logic input data generation unit (114) sets the logic output of the circuit to 0, for example, because the condition for exciting the relay X is {(C1∧C2) ∨¬C3}. Set the logic input data {C1, C2, C3} to the negation of the excitation condition {(¬
From C1∨¬C2) ∧C3}, {0,0,1}, {0,
, 1, 1}, {1, 0, 1} and so on. The generated logical input data may be simulated in each case, or may be simulated only in the data selected by the user. FIG. 14 shows an outline of the symbol simulation processing here. Process of setting input signal string to each input terminal (Process 1
21) is the same as that of the first embodiment, but instead of time series data of the bus voltage, variables are automatically assigned from the waveform model of each bus voltage at the time when the limit value of the relay operation changes. , Is set to the terminal of each bus as the switch switching time (processing 122). The order relation of these variables can be determined in advance for one bus terminal. Next, the initial state of the circuit is determined from the input signal sequence (process 123) and the simulation is started. In the simulation, in addition to the variables such as V ₀ and t ₀ used when designating the waveform of the bus voltage, a hypothesis is generated regarding the order relation of the variables respectively assigned at the times when the limit value of the relay operation changes. 124). There are many hypotheses that can be considered as combinations of variables, but here, based on a predetermined order relation such as the condition of t ₀ <t ₁ <t ₂ <t ₃ that is determined from the bus voltage change model. Limits the number of hypotheses generated. After the hypothesis is generated, as in the first embodiment, the switch is switched (process 126) according to the change in the bus voltage (process 125), the 0 signal is generated by the switching (process 127), and the propagation of other signals (process 125). Process 12
8) is calculated. These processes are repeated until there are no unprocessed signals (process 129). When the simulation under a certain hypothesis is completed, another simulation is performed according to another hypothesis (process 130), and simulation is performed for all hypotheses. And then exit. The simulation result (113) obtained here includes variables, and the hypothesis regarding the voltage and the voltage change time assumed prior to the simulation, for example, whether V ₁ is 60 V or more, whether the temporary voltage recovery is the relay contact point or not. Different circuit operations are obtained depending on conditions such as whether the operation delay time lasts longer than the operation delay time. The results are analyzed through the input / output terminal (115) according to the condition desired by the user, for example, the condition that the output changes due to the voltage change is selected, and the information is presented. . In the example above, the voltage of 60V or more is 20m due to the temporary recovery of the bus voltage.
If it continues for s or more, the analysis result such that the relay X outputs 1 is presented. By using this device, it is possible to determine from the circuit design diagram the conditions for a busbar accident that require some measure.

Next, a third embodiment of the present invention will be described.
FIG. 15 shows an embodiment for a transistor circuit according to the present invention. The simulation device (201) includes circuit data (202) and logic input data (2
12) and the power supply voltage temporal change data (203) are input, and the temporal change of the circuit output value of the power supply in an unstable state is simulated, and the result is output to the display (204a) or the print (204b). The simulation apparatus (201) interprets a transistor circuit by using a knowledge base (205) regarding the operation of each circuit element as a logic element and what kind of equipment the symbol in the circuit indicates, and the impedance in the sequence diagram. A circuit element specification database (6) for selecting an appropriate default value when the specification of the element such as a value is not entered is held in advance.

FIG. 16 shows an outline of the processing of the circuit functional model generation means (207). The model generation means (207) interprets the operation as a logic circuit from the given circuit data, for example, the transistor circuit of FIG. 17, and generates a functional model of the circuit. There are only two kinds of signal values that can be taken by the logic circuit, that is, a logic value 0 or 1. In the processing, first, a judgment is made based on the knowledge base (205), and a circuit element whose operation as a logic element is always interpreted as 0 is removed (processing 211). In addition, elements such as an amplifier that are always interpreted as 1 are erased from the circuit and the terminals on both sides are short-circuited (process 21).
2). With respect to the remaining elements in this way, an equivalent logic gate circuit is generated from the connection relationship with those logic operations (process 213). Further, in order to consider the circuit operation for a minute time, a delay element corresponding to the line delay between the transistors operating as logic elements is inserted in the connection line between the logic gates (process 214), and the operating power supply is changed. A functional model of the circuit in a normal state. Further, by inputting the data of the same transistor circuit, the operation-power supply voltage relationship table generation means (208) generates information relating the availability of operation of the logic element and the power supply terminal voltage. FIG. 18 shows an outline of the processing of the relationship table generating means (208). In the relation table generation, first, a transistor connected so as to perform a logical operation is selected from the circuit (process 221). For each of them, the operation power supply terminal and the route from the terminal are identified (process 222), and the impedance of the circuit element and wiring on the route is calculated (process 223). here,
Assuming that the resistance of the transistor itself as a logic element can be ignored, only the impedances of other wirings and resistors are considered. The voltage required for operation is retrieved from the specification database (206) (process 224). Terminal voltage Vth required to apply a voltage at which a transistor can operate
Is calculated from the values obtained in (Process 223) and (Process 224) (Process 225), and the relation table together with the power supply terminal id which is the identifier of the power supply terminal connected to the transistor id which is the identifier given to each circuit element. (Process 226). For example, as shown in FIG. 19, a transistor 03 (231) which is one of the transistor ids
, The identifier of the power supply terminal to be connected Bus-No
-2 (232), the value 3V (233) calculated as the minimum required voltage is registered in the table. The model change information setting means (209) based on the power supply voltage adds information for rewriting the circuit model due to the terminal voltage change from the information in the relation table. From this information and the functional model, the logic simulation model generation unit (211) generates a simulation model considering the temporal change of the terminal voltage. The outline of the processing here is shown in FIG. First, for all the transistors registered in the relationship table, a changeover switch is inserted between the gate corresponding to the output terminal and the gate to which the output signal propagates (Process 24).
1). In the initial state, the changeover switch connects the gate corresponding to the relay and the propagation destination of the output signal thereof. The other terminal of the changeover switch is connected to the gate that always outputs 0 (process 242). After inserting the changeover switch, for each of the power supply terminals used in the circuit, generate a signal generation source that generates a switch changeover signal according to the voltage change across the limit value of the operating power supply voltage registered in the relationship table. Yes (Process 24
3). The generated signal source and the changeover switch are wired according to the relation table (process 244). Naturally, the operating power source is obtained from the same terminal, and the changeover switch added to the logic gate corresponding to the transistor having the same operating power source voltage limit value is wired from the same signal generating source. Based on the simulation model generated in this way, logic input data (21
2) and terminal voltage change data (203) are input as a simulation. For the input signal of the original circuit, consider the target logic of this circuit, and select the logic input data such as the condition when the output should not be generated under the non-steady state of the operating power supply Enter from. The processing of the logic simulation execution unit (210) and the display of the simulation result are the same as those in the first embodiment.

It goes without saying that the method of using symbolic simulation as the method of logic simulation described in the second embodiment of the present invention can be applied to the third embodiment for a transistor circuit. Further, although the voltage source has been described as the operation power source of the target circuit, a current source may be used in a transistor circuit or the like.

[0016]

According to the present invention, a target circuit is modeled and change data and logic data of a power supply connected to this circuit are used without describing the electrical characteristics of the components throughout the circuit. This makes it possible to simulate circuit operation depending on the state of the operating power supply. This makes it possible to simulate circuit operation based on the operating power supply state more easily and efficiently than circuit simulation using electrical operation, and it is also possible to make detailed examinations regarding abnormal operating power supply at the design stage before actual production. Become. Further, by using this, it becomes possible to evaluate in advance from the circuit design drawing the pattern of busbar accidents that have a significant effect on the system, which is very effective in improving the reliability of the system. In addition, by providing the circuit element specification database, it is possible to provide a simulation result of a certain quality by selecting an appropriate default value without requiring the user to make detailed specifications.

[Brief description of drawings]

FIG. 1 is a configuration of a first embodiment of the present invention.

[Fig. 2] Outline of simulation processing

FIG. 3 is a processing flow of a functional model of a circuit

FIG. 4 is an example of a relay sequence circuit.

FIG. 5 is an example of a functional model of a circuit.

FIG. 6 is a processing flow of generating a relationship table between a relay and a bus.

FIG. 7 is an example of a relationship table between a relay and a bus.

FIG. 8: Process flow of model change information setting

FIG. 9 is an example of a logical simulation model after setting model change information.

FIG. 10: Process flow of logic simulation

FIG. 11 is an example of time-dependent data of bus voltage.

FIG. 12: Display example of simulation results

FIG. 13 is a configuration of a second embodiment of the present invention.

FIG. 14 is a processing flow of symbol simulation according to the second embodiment.

FIG. 15 is a configuration of a third embodiment of the present invention.

FIG. 16: Process flow of functional model of circuit

FIG. 17 is a transistor circuit targeted in the third embodiment of the present invention.

FIG. 18 is a processing flow of generating a relation table between a transistor and a power supply terminal voltage.

FIG. 19 is an example of a relation table between a transistor and a power supply terminal voltage.

FIG. 20: Model change information setting process flow

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Simulation device 2 Circuit data input means 3 Bus voltage change data 4a, 4b Simulation result output means 5 Knowledge base on circuit element operation 6 Circuit element specification database 7 Circuit functional model generation means 8 Relay operation / bus voltage relation table generation means 9 Model change information setting means 10 Logic simulation execution unit 11 Logic simulation model generation unit 12 Logic input data

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukihiro Oda 5-2-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Omika factory

Claims (10)

[Claims] 1. A circuit simulation method characterized by simulating the behavior of the circuit by using change data of a power supply connected to a circuit to be simulated and logic data input to the circuit. 2. A simulation method for inputting configuration information of a target circuit, storing specifications of components constituting the circuit, and performing processing according to a predetermined procedure based on the configuration information and the stored information. Then, a functional model of the circuit is generated from the relationship established between the input and output signals of the circuit, a simulation model in which the information of the operating power supply is incorporated into the functional model of the circuit is generated, and the logical input data is added to the generated model. And a method of simulating the operation of the circuit by inputting time-varying data of the operating power supply. 3. A simulation method for inputting configuration information of a target circuit, storing specifications of components constituting the circuit, and performing processing according to a predetermined procedure based on the configuration information and the stored information. Therefore, a model for simulating the operation of the circuit is generated, the temporal change of the operating power supplied to the circuit is expressed by using a variable, logical input data for the circuit is generated, and the assumption is made. The operation of the circuit is input, the operation of the circuit is simulated based on the temporal change of the power supply expressed using variables, the generated model and the logic input data, and the operation of the circuit is simulated. A method for simulating a circuit, in which the temporal change of the operating power supply is obtained from the operation result of the circuit assumed as the result of the simulation. 4. A model for simulating the operation of a target circuit is generated by generating a functional model of the circuit from the relationship established between the input and output signals of the circuit, and operating power supply to the functional model of the circuit. A method for simulating a circuit, which is characterized by incorporating and generating the information of. 5. A means for storing change data of a power supply connected to a circuit to be simulated, and a simulator for simulating the behavior of the circuit using the change data of the power supply and the logic data input to the circuit.
A circuit simulation device comprising: a display unit for displaying a result of the simulation. 6. A means for inputting configuration information of a target circuit, logic input data for the circuit and time change data of an operating power supply, and means for storing specifications of constituent elements constituting the circuit. And means for generating a model for simulating the operation of the circuit, and logic input data and time-varying data of the operating power supply are input to the generated model to simulate the operation of the circuit. -A circuit simulation device comprising: 7. The means for generating a model for simulating the operation of a target circuit according to claim 6, wherein the means for generating a functional model of the circuit is based on the relationship established between the input and output signals of the circuit. And a circuit simulation device including means for incorporating information on an operating power supply into a functional model of the circuit. 8. A means for inputting configuration information of a target circuit, a means for storing specifications of components constituting the circuit, and a model for simulating the operation of the circuit. Means, means for expressing a temporal change of the operating power supply supplied to the circuit by using variables, means for generating logical input data for the circuit, means for inputting expected operation of the circuit, and variables Means for simulating the operation of the circuit based on the temporal change of the power supply expressed by using, the generated model and the logic input data,
A circuit simulation device comprising: means for obtaining a temporal change of an operating power supply based on a simulation result of the operation of the circuit and an assumed operation of the circuit. 9. The circuit simulation according to claim 5, wherein the target circuit is a relay sequence circuit or a transistor circuit.
Device. 10. The circuit simulation device according to claim 5, wherein the operating power supply of the target circuit is a voltage source or a current source.