EP1658619A2 - Hub module for connecting one or more memory devices - Google Patents

Hub module for connecting one or more memory devices

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Publication number
EP1658619A2
EP1658619A2 EP04763796A EP04763796A EP1658619A2 EP 1658619 A2 EP1658619 A2 EP 1658619A2 EP 04763796 A EP04763796 A EP 04763796A EP 04763796 A EP04763796 A EP 04763796A EP 1658619 A2 EP1658619 A2 EP 1658619A2
Authority
EP
European Patent Office
Prior art keywords
address
memory
memory area
hub module
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04763796A
Other languages
German (de)
French (fr)
Inventor
Peter Pöchmüller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
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Infineon Technologies AG
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Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1658619A2 publication Critical patent/EP1658619A2/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Definitions

  • Hub module for connecting one or more memory modules
  • the invention relates to a hub module for connecting one or more memory modules for use in a memory module.
  • Memory chips are often used in personal computers to store data to be processed in the personal computer.
  • the memory modules are combined to form memory modules to meet the requirements for high memory capacity.
  • Address and data bus is provided to which the memory modules are connected, i.e. each of the memory modules is connected to the common address and data bus.
  • the maximum clock frequency with which address data and user data can be transmitted is limited due to the line and input capacities of the corresponding inputs for the address and data bus on the memory modules and the reflection of the signals at branches.
  • the frequencies with which data must be transmitted via the address and data bus can be very high, especially when using double data rate technology (DDR).
  • DDR double data rate technology
  • a possible alternative address and data bus concept is to provide a so-called hub module between a memory controller in the personal computer and the memory modules, which is used to control one or more memory modules.
  • the hub device is connected to the memory controller, which is responsible for storing and retrieving Controls data, connects.
  • the hub module has an input for the address and data bus in order to receive address data and user data and possibly to transfer user data to the memory controller.
  • the hub module also has an output via which the address and user data are output. The output for the address and user data can be connected to an input of another subsequent hub module, to which in turn memory modules are connected.
  • the hub module has an address decoder unit that receives the pending address and, depending on the address, either addresses one of the connected memory modules or applies the pending address to the address output so that it can be forwarded to the next hub module.
  • the user data on the data bus are either continued or written to the connected memory modules.
  • memory modules cannot be manufactured without errors. Errors that occur are repaired in several steps, both in a wafer repair step and possibly in a back-end repair step at the device level. Nevertheless, it can happen that further previously undetected errors can occur in the repaired memory modules (e.g. memory cell degradation after prolonged operation). These errors can lead to the computer system no longer functioning stably or to errors when running software.
  • a hub module for connecting one or more memory modules, each with at least one memory area.
  • the hub module has an address input for connection to an address bus in order to receive an address of a memory area to be addressed, and an address output for connection to a further address bus.
  • An address decoder unit is provided in order to address a memory area of one of the connected memory modules with an address present at the address input or to apply the address present to the address output.
  • the address decoder unit has a redundancy unit in order to address a redundant memory area instead of the addressed memory area in the event of a detected error in a memory area of the one or more connected memory modules.
  • a redundancy unit is therefore provided in the hub module according to the invention in order to address a redundantly provided memory area instead of a regular memory area in the event of an error. This enables that after the complete manufacture and after the testing of the memory chips and their repair in the wafer repair step and the back-end repair step, the memory chips can also be operated if an error occurs in the memory chips. If, for example, one or more memory areas in the memory modules in a memory module fail due to errors, it is subsequently possible to change the memory module without manipulating the relevant memory module or the memory controller used so that it can continue to be operated in the computer system. This is possible borrowed by providing the hub module with a redundancy unit that enables the error to be repaired.
  • the address decoder unit has an error address input in order to receive an error address.
  • the address decoder unit comprises a comparator unit in order to compare the error address with the address present and to address a further redundant memory area instead of the addressed memory area when an identity is found between the error address and the address present.
  • an error address memory can preferably be provided in order to store the error address and to make it available to the address decoder unit.
  • the redundant memory area can be provided in the connected memory modules, or an additional memory module can be provided in which the redundant memory area is included.
  • the hub module can include the redundant memory area. This makes it possible to provide a repair option for a memory module in a simple manner, to which only a hub module with a redundant memory area is made available. The memory modules or the memory controller do not have to be changed for this.
  • a memory module with a hub module and connected memory modules is provided.
  • FIG. 1 is a block diagram of a memory system with memory modules with hub modules according to the invention according to a first embodiment of the invention
  • FIG. 2 shows a memory system with memory modules with hub modules according to the invention in accordance with a second embodiment.
  • 1 shows a storage system, for example for a computer system.
  • the memory system has a memory controller 1 to which an address bus 2 with a number of n address lines is connected.
  • the memory controller 1 is able to control memory modules using, for example, a DDR memory protocol.
  • the address lines are applied to an input of a memory module 3.
  • the memory module 3 has a hub module 4 to which one or more memory modules 5 are connected.
  • the memory modules are preferably DDR memory modules, in particular DDR DRAM memory modules.
  • the address input of the memory module 3 is connected to an address input of the hub module 4.
  • the hub module 4 has an address output, which is connected to a further address bus 6 via the address output of the memory module 3.
  • the further address bus 6 is connected to an address input of a further memory module.
  • the hub module has an address decoder unit 7 which checks the addresses present on the address bus 2 and, depending on the address applied, addresses the corresponding connected memory module 5 via a respective memory module interface 8 or forwards the current address to the further address bus 6. The address is then received by the further address bus 6 from the address decoder unit of the hub module of the next memory module and there either used for addressing one of the connected memory modules 5 or forwarded to a further address bus via the address output.
  • a common memory module interface 8 can also be provided, which is connected to all of the connected memory modules 5 via a module-internal address and data bus.
  • Memory module interfaces 8 that are separated from one another have the advantage that the memory modules 5 essentially Chen can be addressed in parallel or at a higher speed, while the wiring effort can be reduced with a jointly executed memory chip interface.
  • the address decoder unit 7 of the hub module 4 also has a redundancy unit 9 which is used to carry out an address mapping, i.e. to internally replace a pending address that addresses a faulty memory area with another address, so that the faulty memory area is replaced by a redundant memory area.
  • the addresses for the defective memory areas are stored in the redundancy unit and each of these is assigned a further redundant memory area with which the defective memory area is to be replaced.
  • the error addresses are determined by testing the memory modules at the memory module level and either using a test function integrated in the hub module or an external test function.
  • the error addresses can be stored in the error address memory 10 with the aid of laser or electrical feet on the hub chip or from an external source such as e.g.
  • an EPROM can be provided on the hub chip.
  • the memory areas of the memory modules 5 are divided into a first regular memory area part and a second redundant memory area part. How the division takes place is arbitrary and is essentially determined by the address decoding unit 7 of the hub module 4. In this way, redundant memory areas can be provided in each of the redundant memory areas 5. Alternatively, it can also be provided that redundant memory areas are provided in only one of the connected memory modules 5 to replace the faulty memory areas of all connected memory modules 5.
  • the regular and the redundant memory areas in the sense of this invention do not correspond to the regular memory areas and the redundant memory areas in a memory. as they occur during the wafer repair process and the back-end repair process.
  • the regular and redundant memory areas in one of the memory modules 5 merely represent a logical organization of the memory areas in the memory modules 5 that have been tested as functional. Both regular and redundant memory areas in the sense of the invention correspond to the memory areas in the respective memory modules 5 that have been tested as error-free.
  • the redundancy unit 9 can comprise an error address memory 10 or can be connected to an error address memory 10 likewise provided in the hub module 4 or externally.
  • the fault address memory 10 is used to store fault addresses which indicate which of the addresses present must be assigned to a redundant memory area, since the regular memory area at the address present is faulty.
  • the redundancy unit 9 preferably has a comparator unit (not shown) which compares the address present with the error addresses stored in the error address memory 10 and, depending on the detection or non-detection of an error, the corresponding regular memory area or redundant memory area addressed in accordance with the address of the connected memory modules 5 addressed.
  • FIG. 2 shows a further embodiment of a lifting module according to the invention.
  • the hub module 20 has redundant memory areas 21 which are integrated in the hub module 20. This makes it possible to avoid providing additional memory modules 5 with redundant memory areas that have to be connected to the hub modules 20. Since the failure rate of memory areas after testing the memory modules 5 is usually very low, it is possible to provide redundant memory areas 21 in the hub module 20, so that the redundant memory areas can be accessed more quickly. rich 21 is possible.
  • the additional redundant memory areas 21 can be provided in the address decoding unit 7 or elsewhere in the hub module 20.
  • the additional redundant memory areas 21 can be created to transmit the user data via a multiplexer (not shown) with the data bus (not shown) connected to the memory module 3 if an address is present on the address bus 2 that is provided by a redundant memory area to be replaced.

Abstract

The invention relates to a hub module for connecting one or more memory devices. Said module comprises an address input for connection to an address bus, in order to receive an address of the memory area to be addressed, an address output for connection to an additional address bus, an address decoder unit for addressing one of the connected memory devices using an address available at the address input, or for supplying said available address to the address output. The invention is characterised in that the address decoder unit has a redundancy unit, which, if an error has been identified in a memory area of the one or more connected memory devices, permits a redundant memory area to be addressed instead of the addressed memory area.

Description

Beschreibungdescription
Hub-Baustein zum Anschließen von einem oder mehreren SpeicherbausteinenHub module for connecting one or more memory modules
Die Erfindung betrifft einen Hub-Baustein zum Anschließen von einem oder mehreren Speicherbausteinen zur Verwendung in einem Speichermodul .The invention relates to a hub module for connecting one or more memory modules for use in a memory module.
Speicherbausteine werden häufig in Personalcomputern eingesetzt, um in dem Personalcomputer zu verarbeitende Daten zu speichern. Die Speicherbausteine sind dazu zu Speichermodulen zusammen gefasst, um den Anforderungen nach hoher Speicherkapazität gerecht zu werden. Um die Speicherkapazität von meh- reren Speichermodulen zu nutzen, ist üblicherweise einMemory chips are often used in personal computers to store data to be processed in the personal computer. The memory modules are combined to form memory modules to meet the requirements for high memory capacity. To use the memory capacity of several memory modules, is usually one
Adress- und Datenbus vorgesehen, an dem die Speichermodule angeschlossen sind, d.h. jedes der Speichermodule steht mit dem gemeinsamen Adress- und Datenbus in Verbindung. Aufgrund der Leitungs- und Eingangskapazitäten der entsprechenden Ein- gänge für den Adress- und Datenbus an den Speichermodulen sowie Reflexion der Signale an Abzweigungen ist die maximale Taktfrequenz, mit der Adressdaten und Nutzdaten übertragen werden können, begrenzt.Address and data bus is provided to which the memory modules are connected, i.e. each of the memory modules is connected to the common address and data bus. The maximum clock frequency with which address data and user data can be transmitted is limited due to the line and input capacities of the corresponding inputs for the address and data bus on the memory modules and the reflection of the signals at branches.
Insbesondere bei Nutzung der Double-Data-Rate-Technologie (DDR) können die Frequenzen, mit denen Daten über den Adress- und Datenbus übertragen werden müssen, sehr hoch sein. Für eine künftige DDR-III- oder andere hochperformante Interface- Technologie bietet es sich daher an, die Speichermodule nicht an einem gemeinsamen Adress- und Datenbus zu betreiben.The frequencies with which data must be transmitted via the address and data bus can be very high, especially when using double data rate technology (DDR). For a future DDR-III or other high-performance interface technology, it is therefore advisable not to operate the memory modules on a common address and data bus.
Ein mögliches alternatives Adress- und Datenbuskonzept besteht darin, einen sogenannten Hub-Baustein zwischen einem Speichercontroller in dem Personalcomputer und den Speicher- bausteinen vorzusehen, der zum Ansteuern von einem oder mehreren Speicherbausteinen verwendet wird. Der Hub-Baustein ist mit dem Speichercontroller, der das Speichern und Abrufen von Daten steuert, verbunden. Der Hub-Baustein weist einen Eingang für den Adress- und Datenbus auf, um Adressdaten und Nutzdaten zu empfangen und evtl. Nutzdaten zum Speichercontroller zu übertragen. Der Hub-Baustein weist weiterhin einen Ausgang auf, über den die Adress- und Nutzdaten ausgegeben werden. Der Ausgang für die Adress- und Nutzdaten kann mit einem Eingang eines weiteren nachfolgenden Hub-Bausteins, an den wiederum Speicherbausteine angeschlossen sind, verbunden werden.A possible alternative address and data bus concept is to provide a so-called hub module between a memory controller in the personal computer and the memory modules, which is used to control one or more memory modules. The hub device is connected to the memory controller, which is responsible for storing and retrieving Controls data, connects. The hub module has an input for the address and data bus in order to receive address data and user data and possibly to transfer user data to the memory controller. The hub module also has an output via which the address and user data are output. The output for the address and user data can be connected to an input of another subsequent hub module, to which in turn memory modules are connected.
Der Hub-Baustein weist eine Adressdecodereinheit auf, die die anliegende Adresse empfängt und abhängig von der Adresse entweder einen der angeschlossenen Speicherbausteine adressiert oder die anliegende Adresse an den Adressausgang anlegt, so dass sie an den nächsten Hub-Baustein weitergeleitet werden kann. Entsprechend werden die auf dem Datenbus anliegenden Nutzdaten entweder weitergeführt oder in die angeschlossenen Speicherbausteine geschrieben.The hub module has an address decoder unit that receives the pending address and, depending on the address, either addresses one of the connected memory modules or applies the pending address to the address output so that it can be forwarded to the next hub module. Correspondingly, the user data on the data bus are either continued or written to the connected memory modules.
Aufgrund der Herstellungstechnologie können Speicherbausteine nicht fehlerfrei hergestellt werden. Auftretende Fehler werden in mehreren Schritten sowohl in einem Wafer- Reparaturschritt als auch eventuell in einem Back-End- Reparaturschritt auf Bausteinebene repariert. Trotzdem kann es vorkommen, dass in den so reparierten Speicherbausteinen weitere zuvor unerkannte Fehler auftreten können (z.B. Speicherzellendegradation nach längerem Betrieb) . Diese Fehler können dazu führen, dass das ComputerSystem nicht mehr stabil funktioniert oder dass Fehler beim Ausführen einer Software auftreten können.Due to the manufacturing technology, memory modules cannot be manufactured without errors. Errors that occur are repaired in several steps, both in a wafer repair step and possibly in a back-end repair step at the device level. Nevertheless, it can happen that further previously undetected errors can occur in the repaired memory modules (e.g. memory cell degradation after prolonged operation). These errors can lead to the computer system no longer functioning stably or to errors when running software.
Es ist Aufgabe der vorliegenden Erfindung, einen Hub-Baustein zur Verfügung zu stellen, der es ermöglicht, dass ein Computersystem trotz Auftreten von Fehlern in den verwendeten Speicherbausteinen betrieben werden kann. Diese Aufgabe wird durch den Hub-Baustein nach Anspruch 1 gelöst.It is an object of the present invention to provide a hub module which enables a computer system to be operated despite errors occurring in the memory modules used. This object is achieved by the hub module according to claim 1.
Weitere vorteilhafte Ausgestaltungen der Erfindung sind in den abhängigen Ansprüchen angegeben.Further advantageous embodiments of the invention are specified in the dependent claims.
Erfindungsgemäß ist ein Hub-Baustein zum Anschließen von einem oder mehreren Speicherbausteinen mit jeweils mindestens einem Speicherbereich vorgesehen. Der Hub-Baustein weist ei- nen Adress-Eingang zum Anschließen an einen Adressbus, um eine Adresse eines zu adressierenden Speicherbereiches zu empfangen, und einen Adressausgang zum Anschließen an einen weiteren Adressbus auf. Es ist eine Adressdecodereinheit vorgesehen, um mit einer an dem Adresseingang anliegenden Adresse einen Speicherbereich eines der angeschlossenen Speicherbausteine zu adressieren oder die anliegende Adresse an den Adressausgang anzulegen. Die Adressdecodereinheit weist eine Redundanzeinheit auf, um bei einem erkannten Fehler in einem Speicherbereich der einen oder mehreren angeschlossenen Spei- cherbausteine anstelle des adressierten Speicherbereichs einen redundanten Speicherbereich zu adressieren.According to the invention, a hub module is provided for connecting one or more memory modules, each with at least one memory area. The hub module has an address input for connection to an address bus in order to receive an address of a memory area to be addressed, and an address output for connection to a further address bus. An address decoder unit is provided in order to address a memory area of one of the connected memory modules with an address present at the address input or to apply the address present to the address output. The address decoder unit has a redundancy unit in order to address a redundant memory area instead of the addressed memory area in the event of a detected error in a memory area of the one or more connected memory modules.
In dem erfindungsgemäßen Hub-Baustein ist also eine Redundanzeinheit vorgesehen, um bei einem aufgetretenen Fehler an- stelle eines regulären Speicherbereiches ein redundant vorgesehener Speicherbereich zu adressieren. Dies ermöglicht es, dass nach der vollständigen Herstellung und nach dem Testen der Speicherbausteine sowie dessen Reparatur in dem Wafer- Reparaturschritt und dem Back-End-Reparaturschritt ein Betreiben der Speicherbausteine auch möglich ist, wenn ein Fehler in den Speicherbausteinen auftritt. Fällt beispielsweise ein oder mehrere Speicherbereiche in den Speicherbausteinen in einem Speichermodul aufgrund von Fehlern aus, so ist es damit nachträglich möglich, ohne Manipulation des betreffenden Speicherbausteins bzw. des verwendeten Speichercontrollers das Speichermodul so zu ändern, dass es weiterhin in dem ComputerSystem betrieben werden kann. Dies ist mög- lieh, indem der Hub-Baustein mit einer Redundanzeinheit vorgesehen wird, die die Reparatur des Fehlers ermöglicht.A redundancy unit is therefore provided in the hub module according to the invention in order to address a redundantly provided memory area instead of a regular memory area in the event of an error. This enables that after the complete manufacture and after the testing of the memory chips and their repair in the wafer repair step and the back-end repair step, the memory chips can also be operated if an error occurs in the memory chips. If, for example, one or more memory areas in the memory modules in a memory module fail due to errors, it is subsequently possible to change the memory module without manipulating the relevant memory module or the memory controller used so that it can continue to be operated in the computer system. This is possible borrowed by providing the hub module with a redundancy unit that enables the error to be repaired.
Es kann vorgesehen sein, dass die Adressdecodereinheit einen Fehleradresseingang aufweist, um eine Fehleradresse zu empfangen. Die Adressdecodereinheit umfasst eine Vergleichereinheit, um die Fehleradresse mit der anliegenden Adresse zu vergleichen und bei Feststellen einer Identität zwischen der Fehleradresse und der anliegenden Adresse anstelle des adres- sierten Speicherbereichs einen weiteren redundanten Speicherbereich zu adressieren. Dazu kann vorzugsweise ein Fehleradressenspeicher vorgesehen sein, um die Fehleradresse zu speichern und der Adressdecodereinheit zur Verfügung zu stellen.It can be provided that the address decoder unit has an error address input in order to receive an error address. The address decoder unit comprises a comparator unit in order to compare the error address with the address present and to address a further redundant memory area instead of the addressed memory area when an identity is found between the error address and the address present. For this purpose, an error address memory can preferably be provided in order to store the error address and to make it available to the address decoder unit.
Der redundante Speicherbereich kann in den angeschlossenen Speicherbausteinen vorgesehen sein, bzw. es kann ein zusätzlicher Speicherbaustein vorgesehen sein, in dem der redundante Speicherbereich umfasst ist. Alternativ kann der Hub- Baustein den redundanten Speicherbereich umfassen. Dies er- möglicht, auf einfache Weise eine Reparaturmöglichkeit für ein Speichermodul vorzusehen, dem lediglich ein Hub-Baustein mit redundantem Speicherbereich zur Verfügung gestellt wird. Die Speicherbausteine bzw. der Speichercontroller müssen dafür nicht geändert werden. Gemäß einem weiteren Aspekt der vorliegenden Erfindung ist ein Speichermodul mit einem Hub- Baustein und angeschlossenen Speicherbausteine vorgesehen.The redundant memory area can be provided in the connected memory modules, or an additional memory module can be provided in which the redundant memory area is included. Alternatively, the hub module can include the redundant memory area. This makes it possible to provide a repair option for a memory module in a simple manner, to which only a hub module with a redundant memory area is made available. The memory modules or the memory controller do not have to be changed for this. According to a further aspect of the present invention, a memory module with a hub module and connected memory modules is provided.
Bevorzugte Ausfuhrungsformen der Erfindung werden im folgenden anhand der beigefügten Zeichnungen näher erläutert. Es zeigen:Preferred embodiments of the invention are explained below with reference to the accompanying drawings. Show it:
Figur 1 ein Blockschaltbild eines Speichersystems mit Speichermodulen mit erfindungsgemäßen Hub-Bausteinen gemäß einer ersten Ausfuhrungsform der Erfindung; und Figur 2 ein Speichersystem mit Speichermodulen mit erfin- dungsgemäßen Hub-Bausteinen gemäß einer zweiten Ausfuhrungs- form. In Figur 1 ist ein Speichersystem z.B. für ein Computersystem dargestellt. Das Speichersystem weist einen Speichercontroller 1 auf, an den ein Adressbus 2 mit einer Anzahl n Adress- leitungen angeschlossen ist. Der Speichercontroller 1 ist in der Lage, Speicherbausteine mit Hilfe z.B. eines DDR- Speicherprotokolls anzusteuern. Die Adressleitungen sind an einen Eingang eines Speichermoduls 3 angelegt. Das Speichermodul 3 weist einen Hub-Baustein 4 auf, an dem ein oder mehrere Speicherbausteine 5 angeschlossen sind. Die Speicherbau- steine sind vorzugsweise DDR-Speicherbausteine, insbesondere DDR-DRAM-Speicherbausteine. Der Adresseingang des Speichermoduls 3 ist mit einem Adresseingang des Hub-Bausteins 4 verbunden. Der Hub-Baustein 4 weist einen Adressausgang auf, der über den Adressausgang des Speichermoduls 3 mit einem weite- ren Adressbus 6 verbunden ist. Der weitere Adressbus 6 ist mit einem Adresseingang eines weiteren Speichermoduls verbunden.Figure 1 is a block diagram of a memory system with memory modules with hub modules according to the invention according to a first embodiment of the invention; and FIG. 2 shows a memory system with memory modules with hub modules according to the invention in accordance with a second embodiment. 1 shows a storage system, for example for a computer system. The memory system has a memory controller 1 to which an address bus 2 with a number of n address lines is connected. The memory controller 1 is able to control memory modules using, for example, a DDR memory protocol. The address lines are applied to an input of a memory module 3. The memory module 3 has a hub module 4 to which one or more memory modules 5 are connected. The memory modules are preferably DDR memory modules, in particular DDR DRAM memory modules. The address input of the memory module 3 is connected to an address input of the hub module 4. The hub module 4 has an address output, which is connected to a further address bus 6 via the address output of the memory module 3. The further address bus 6 is connected to an address input of a further memory module.
Der Hub-Baustein weist eine Adressdecodereinheit 7 auf, die die an dem Adressbus 2 anliegenden Adressen überprüft und je nach angelegter Adresse den entsprechenden angeschlossenen Speicherbaustein 5 über eine jeweilige Speicherbausteinschnittstelle 8 adressiert oder die anliegende Adresse an den weiteren Adressbus 6 weiterreicht . Von dem weiteren Adressbus 6 wird die Adresse dann von der Adressdecodereinheit des Hub- Bausteins des nächsten Speichermoduls empfangen und dort auf die gleiche Weise entweder zum Adressieren eines der angeschlossenen Speicherbausteine 5 verwendet oder über den Adressausgang an einen weiteren Adressbus weitergeleitet.The hub module has an address decoder unit 7 which checks the addresses present on the address bus 2 and, depending on the address applied, addresses the corresponding connected memory module 5 via a respective memory module interface 8 or forwards the current address to the further address bus 6. The address is then received by the further address bus 6 from the address decoder unit of the hub module of the next memory module and there either used for addressing one of the connected memory modules 5 or forwarded to a further address bus via the address output.
Anstatt für jeden der angeschlossenen Speicherbausteine 5 eine einzelne Speicherbausteinschnittstelle 8 vorzusehen, kann auch eine gemeinsame Speicherbausteinschnittstelle 8 vorgesehen sein, die über einen modulinternen Adress- und Datenbus mit allen der angeschlossenen Speicherbausteine 5 verbunden ist. Voneinander getrennte Speicherbausteinschnittstellen 8 haben den Vorteil, dass die Speicherbausteine 5 im wesentli- chen parallel oder mit höherer Geschwindigkeit angesprochen werden können, während bei einer gemeinsam ausgeführten Speicherbausteinschnittstelle der Verdrahtungsaufwand reduziert werden kann.Instead of providing an individual memory module interface 8 for each of the connected memory modules 5, a common memory module interface 8 can also be provided, which is connected to all of the connected memory modules 5 via a module-internal address and data bus. Memory module interfaces 8 that are separated from one another have the advantage that the memory modules 5 essentially Chen can be addressed in parallel or at a higher speed, while the wiring effort can be reduced with a jointly executed memory chip interface.
Die Adressdecodereinheit 7 des Hub-Bausteins 4 weist weiterhin eine Redundanzeinheit 9 auf, die dazu dient, ein Adress- mapping vorzunehmen, d.h. eine anliegende Adresse, die einen fehlerhaften Speicherbereich adressiert, intern durch eine andere Adresse zu ersetzen, so dass der fehlerhafte Speicherbereich durch einen redundanten Speicherbereich ersetzt wird. Dazu sind in der Redundanzeinheit die Adressen für die fehlerhaften Speicherbereiche gespeichert und diesen jeweils ein weiterer redundanter Speicherbereich zugeordnet, mit dem der fehlerhafte Speicherbereich ersetzt werden soll. Die Fehleradressen werden durch einen Test der Speicherbausteine auf Speichermodulebene ermittelt und entweder durch eine in dem Hub-Baustein integrierte Testfunktion oder eine externe Testfunktion ermittelt. Die Fehleradressen können in dem Fehler- adressspeicher 10 mit Hilfe von Laser- oder elektrischen Fu- ses auf dem Hub-Chip oder von einer externen Quelle wie z.B. einem EPROM auf dem Hub-Chip vorgesehen sein. Die Speicherbereiche der Speicherbausteine 5 sind in einen ersten regulären Speicherbereichsteil und einen zweiten redundanten Speicher- bereichsteil aufgeteilt. Wie die Aufteilung erfolgt, ist beliebig und wird im Wesentlichen durch die Adressdecodierein- heit 7 des Hub-Bausteins 4 bestimmt. So können redundante Speicherbereiche in jedem der redundanten Speicherbereiche 5 vorgesehen sein. Es kann alternativ auch vorgesehen sein, dass in nur einem der angeschlossenen Speicherbausteine 5 redundante Speicherbereiche zum Ersetzen der fehlerhaften Speicherbereiche aller angeschlossenen Speicherbausteine 5 vorgesehen ist.The address decoder unit 7 of the hub module 4 also has a redundancy unit 9 which is used to carry out an address mapping, i.e. to internally replace a pending address that addresses a faulty memory area with another address, so that the faulty memory area is replaced by a redundant memory area. For this purpose, the addresses for the defective memory areas are stored in the redundancy unit and each of these is assigned a further redundant memory area with which the defective memory area is to be replaced. The error addresses are determined by testing the memory modules at the memory module level and either using a test function integrated in the hub module or an external test function. The error addresses can be stored in the error address memory 10 with the aid of laser or electrical feet on the hub chip or from an external source such as e.g. an EPROM can be provided on the hub chip. The memory areas of the memory modules 5 are divided into a first regular memory area part and a second redundant memory area part. How the division takes place is arbitrary and is essentially determined by the address decoding unit 7 of the hub module 4. In this way, redundant memory areas can be provided in each of the redundant memory areas 5. Alternatively, it can also be provided that redundant memory areas are provided in only one of the connected memory modules 5 to replace the faulty memory areas of all connected memory modules 5.
Die regulären und die redundanten Speicherbereiche im Sinne dieser Erfindung entsprechen nicht den regulären Speicherbereichen und den redundanten Speicherbereichen in einem Spei- cherbaustein, wie sie während des Wafer-Reparaturverfahrens und des Back-End-Reparaturverfahrens auftreten. Die regulären und redundanten Speicherbereiche in einem der Speicherbausteine 5 stellen lediglich eine logische Organisation der als funktionsfähig getesteten Speicherbereiche in den Speicherbausteinen 5 dar. Sowohl reguläre als auch redundante Speicherbereiche im Sinne der Erfindung entsprechen den als fehlerfrei getesteten Speicherbereichen in den jeweiligen Speicherbausteinen 5.The regular and the redundant memory areas in the sense of this invention do not correspond to the regular memory areas and the redundant memory areas in a memory. as they occur during the wafer repair process and the back-end repair process. The regular and redundant memory areas in one of the memory modules 5 merely represent a logical organization of the memory areas in the memory modules 5 that have been tested as functional. Both regular and redundant memory areas in the sense of the invention correspond to the memory areas in the respective memory modules 5 that have been tested as error-free.
Die Redundanzeinheit 9 kann einen Fehleradressspeicher 10 umfassen oder mit einem ebenfalls in dem Hub-Baustein 4 oder extern vorgesehenen Fehleradressspeicher 10 verbunden sein. Der Fehleradressspeicher 10 dient zum Speichern von Fehlerad- ressen, die angeben, welche der anliegenden Adressen einem redundanten Speicherbereich zugeordnet werden müssen, da der reguläre Speicherbereich an der anliegenden Adresse fehlerhaft ist. Die Redundanzeinheit 9 weist dazu vorzugsweise eine Vergleicher-einheit (nicht gezeigt) auf, die die anliegende Adresse mit den im Fehleradressspeicher 10 gespeicherten Fehleradressen vergleicht und abhängig von einem Erkennen oder Nichterkennen eines Fehlers den entsprechenden gemäß der Adresse adressierten regulären Speicherbereich oder redundanten Speicherbereich in einem der angeschlossenen Speicherbaustei- ne 5 adressiert.The redundancy unit 9 can comprise an error address memory 10 or can be connected to an error address memory 10 likewise provided in the hub module 4 or externally. The fault address memory 10 is used to store fault addresses which indicate which of the addresses present must be assigned to a redundant memory area, since the regular memory area at the address present is faulty. For this purpose, the redundancy unit 9 preferably has a comparator unit (not shown) which compares the address present with the error addresses stored in the error address memory 10 and, depending on the detection or non-detection of an error, the corresponding regular memory area or redundant memory area addressed in accordance with the address of the connected memory modules 5 addressed.
In Figur 2 ist eine weitere Ausfuhrungsform eines erfindungsgemäßen Hub-Bausteins dargestellt. Der Hub-Baustein 20 weist zusätzlich zur Redundanzeinheit 9 redundante Speicherbereiche 21 auf, die in den Hub-Baustein 20 integriert sind. Dadurch kann vermieden werden, zusätzliche Speicherbausteine 5 mit redundanten Speicherbereichen vorzusehen, die an den Hub- Bausteinen 20 angeschlossen werden müssen. Da üblicherweise die Ausfallrate von Speicherbereichen nach dem Testen der Speicherbausteine 5 sehr gering ist, ist es möglich, redundante Speicherbereiche 21 in dem Hub-Baustein 20 vorzusehen, so dass ein schneller Zugriff auf die redundanten Speicherbe- reiche 21 möglich ist. Die zusätzlichen redundanten Speicherbereiche 21 können in der Adressdecodiereinheit 7 oder an anderer Stelle in dem Hub-Baustein 20 vorgesehen sein.FIG. 2 shows a further embodiment of a lifting module according to the invention. In addition to the redundancy unit 9, the hub module 20 has redundant memory areas 21 which are integrated in the hub module 20. This makes it possible to avoid providing additional memory modules 5 with redundant memory areas that have to be connected to the hub modules 20. Since the failure rate of memory areas after testing the memory modules 5 is usually very low, it is possible to provide redundant memory areas 21 in the hub module 20, so that the redundant memory areas can be accessed more quickly. rich 21 is possible. The additional redundant memory areas 21 can be provided in the address decoding unit 7 or elsewhere in the hub module 20.
Die zusätzlichen redundanten Speicherbereiche 21 können zum Übertragen der Nutzdaten über einen (nicht gezeigten) Multi- plexer mit dem an dem Speichermodul 3 angeschlossenen Datenbus (nicht gezeigt) angelegt werden, wenn an dem Adressbus 2 eine Adresse anliegt, die durch einen redundanten Speicherbe- reich ersetzt werden soll. The additional redundant memory areas 21 can be created to transmit the user data via a multiplexer (not shown) with the data bus (not shown) connected to the memory module 3 if an address is present on the address bus 2 that is provided by a redundant memory area to be replaced.

Claims

Patentansprüche claims
1. Hub-Baustein (4) zum Anschließen von einem oder mehreren Speicherbausteinen (5) , mit einem Adresseingang zum Anschließen an einen Adressbus, um eine Adresse des zu adressierenden Speicherbereiches zu empfangen, und mit einem Adressausgang zum Anschließen an einen weiteren Adressbus, mit einer Adressdecodereinheit (7) , um mit einer an dem Ad- resseingang anliegenden Adresse einen der angeschlossenen1. Hub module (4) for connecting one or more memory modules (5), with an address input for connection to an address bus to receive an address of the memory area to be addressed, and with an address output for connection to another address bus, with an address decoder unit (7) in order to use one of the connected ones with an address present at the address input
Speicherbausteine (5) zu adressieren oder die anliegende Adresse an den Adressausgang anzulegen, dadurch gekennzeichnet, dass die Adressdecodereinheit (7) eine Redundanzeinheit (9) auf- weist, um bei einem erkannten Fehler in einem Speicherbereich der einen oder der mehreren angeschlossenen Speicherbausteine (5) anstelle des adressierten Speicherbereiches einen redundanten Speicherbereich zu adressieren.Addressing memory modules (5) or applying the pending address to the address output, characterized in that the address decoder unit (7) has a redundancy unit (9), in order to detect one of the one or more connected memory modules (5 ) to address a redundant memory area instead of the addressed memory area.
2. Hub-Baustein (4) nach Anspruch 1, dadurch gekennzeichnet, dass die Adressdecodereinheit (7) einen Fehleradresseingang aufweist, um eine Fehleradresse zu empfangen, wobei die Adressdecodereinheit (7) eine Vergleichereinheit umfasst, um die Fehleradresse mit der anliegenden Adresse zu vergleichen, und bei Feststellen einer Identität zwischen der Fehleradresse und der anliegenden Adresse anstelle des adressierten Speicherbereiches einen weiteren redundanten Speicherbereich zu adressieren.2. Hub module (4) according to claim 1, characterized in that the address decoder unit (7) has an error address input in order to receive an error address, the address decoder unit (7) comprising a comparator unit in order to compare the error address with the address present , and when determining an identity between the error address and the pending address instead of the addressed memory area to address a further redundant memory area.
3. Hub-Baustein (4) nach Anspruch 2, dadurch gekennzeichnet, dass ein Fehleradressenspeicher (10) vorgesehen ist, um die Fehleradresse zu speichern und der Adressdecodereinheit (7) zur Verfügung zu stellen.3. Hub module (4) according to claim 2, characterized in that an error address memory (10) is provided to store the error address and the address decoder unit (7) available.
4. Hub-Baustein (4) nach Anspruch 2 oder 3, dadurch gekennzeichnet, dass der redundante Speicherbereich in den ange- schlossenen Speicherbausteinen (5) vorgesehen ist.4. Hub module (4) according to claim 2 or 3, characterized in that the redundant memory area is provided in the connected memory modules (5).
5. Hub-Baustein (4) nach Anspruch 2 oder 3, dadurch gekennzeichnet, dass der Hub-Baustein (4) den redundanten Speicherbereich umfasst . 5. Hub module (4) according to claim 2 or 3, characterized in that the hub module (4) comprises the redundant memory area.
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