EP1652233A1 - Couches empilables contenant des modules a grille matricielle a billes - Google Patents

Couches empilables contenant des modules a grille matricielle a billes

Info

Publication number
EP1652233A1
EP1652233A1 EP03818224A EP03818224A EP1652233A1 EP 1652233 A1 EP1652233 A1 EP 1652233A1 EP 03818224 A EP03818224 A EP 03818224A EP 03818224 A EP03818224 A EP 03818224A EP 1652233 A1 EP1652233 A1 EP 1652233A1
Authority
EP
European Patent Office
Prior art keywords
access
layers
layer
package
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03818224A
Other languages
German (de)
English (en)
Other versions
EP1652233A4 (fr
Inventor
Floyd K. Eide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nytell Software LLC
Original Assignee
Irvine Sensors Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Irvine Sensors Corp filed Critical Irvine Sensors Corp
Priority claimed from PCT/US2003/024706 external-priority patent/WO2005018000A1/fr
Publication of EP1652233A1 publication Critical patent/EP1652233A1/fr
Publication of EP1652233A4 publication Critical patent/EP1652233A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to the dense packaging of electronic circuitry and specifically to the stacking of ball grid array (BGA) integrated circuit packages.
  • the invention is also suitable for the stacking of fine ball grid array (FBGA) integrated circuit packages, micro-ball grid array packages and for bump-bonded bare die to form stackable layers which can be combined to form multi-layer electronic modules.
  • FBGA fine ball grid array
  • the present invention relates to the stacking of layers containing integrated circuit chips (ICs), thereby obtaining high-density electronic circuitry.
  • the goal of the present invention is to combine high circuit density with reasonable cost.
  • a unique aspect of this invention is that it provides a low cost method of stacking commercially available ICs in BGA packages while allowing the independent routing of several non-common I/O (input/output) signals from upper-level layers to lower layers or to the bottom of the stack. Cost reduction is accomplished by utilizing relatively low cost interposer boards to reroute leads to an access plane and by the ability to stack prepackaged and pre-tested off-the-shelf BGA packages.
  • None of the background art addresses the need for compact, dense memory stacks that take advantage of the high speed and small outline of a BGA package that are both low cost and highly reliable. It is therefore an object of the invention to provide a stackable layer formed from a BGA package that can be assembled at a relatively low cost and which is structurally and thermally sound. It is a further object of the invention to provide a stack of BGA layers that can provide high electronic density in a very small volume and which is compatible with a conventional BGA footprint on a printed circuit board. It is yet a further object of the invention to provide a low-cost method for manufacturing a stackable layer incorporating a BGA package and a method for manufacturing a stack of such layers.
  • the present invention provides stackable layers which may be interconnected to form a high-density electronic module.
  • This application further discloses a stack of layers electrically interconnected in the vertical direction, suitable for mounting onto a PCB (printed circuit board) or other electronic device.
  • This application further discloses a method for starting with standard BGA packages and manufacturing a stacked IC- containing package using interposer interconnections which are routed in the vertical direction along one or more access planes.
  • the invention generally consists of BGA packaged die that are electrically interconnected to conductive traces on an interposer board formed from a dielectric material.
  • the interposer board serves to reroute electronic signals from the BGA to the periphery, or access edge, of the interposer.
  • the interposer may have a single layer or multiple layers of conductive traces much like conventional printed circuit board technology.
  • the BGA package is solder-reflowed to the interposer and under-filled with an epoxy to form a stackable layer. The formed individual layers may then be aligned and bonded to form a multi-layer structure which includes at least one access plane.
  • the conductive traces that terminate at the access edges are lapped and exposed, then rerouted to the desired locations to allow the interconnection of several non-common signals (e.g., chip enable and/or data lines) from an upper layer to a lower layer of a stack of layers.
  • non-common signals e.g., chip enable and/or data lines
  • FIGS. 1A and 1 B are a perspective view of ball grid array integrated circuit chip package illustrating, respectively, the top of the package and the ball grid array on the underside thereof;
  • FIG. 2 plan view of an interposer board with exemplar conductive traces, access leads and solder ball pads formed thereon;
  • FIG. 3 is a front sectional view of a ball grid array package and interposer board showing the conductive traces, solder balls and solder ball pads;
  • FIG. 4 is a side sectional view of a ball grid array package and interposer board after the elements have been soldered together and under-filled, creating a stackable layer;
  • FIG. 5 is a side sectional view of a stack of layers that have been under-filled and bonded and connected a bottom interposer board;
  • FIG. 6 shows a side view of stack of layers illustrating an access plane with access leads exposed after lapping
  • FIG. 7 shows a side view of stack of layers illustrating an access plane with access lead interconnections between access leads on different layers.
  • FIGS. 1A and 1B show the top and underside, respectively, of a conventional ball grid array (BGA) packaged memory device 1 which includes solder balls 5 for electrical communication of signals and power into and out of the BGA package.
  • BGA ball grid array
  • Conventional BGA memory packages in fine grid array or micro grid array are readily available from a variety of commercial sources such as MICRON TECHNOLOGIES, INC. or SAMSUNG CORP.
  • FIG. 2 illustrates an interposer board 10 made of a dielectric material such as BT Resin from Mitsubishi and includes conductive traces 15.
  • Conductive traces 15 include solder ball pads 20 for the receiving of solder balls 5.
  • Conductive traces lead to and terminate at an access edge 25 on the interposer board to form access leads 30.
  • Conductive traces made of copper or other conductive material are formed on the interposer board in a manner similar to that used in printed circuit board manufacturing.
  • the conductive traces are patterned on the interposer board using conventional photolithography techniques so as to form solder ball pads 20 for the receiving and electrical connection of solder balls 5.
  • the interposer board may include a single layer of conductive traces 15 or, in an alternative embodiment, multiple layers of conductive traces (not shown).
  • solder balls 5 of BGA package 1 are aligned and electrically connected to solder ball pads 20 as is shown in FIG. 3.
  • An alternative embodiment includes the use of fine grid BGA packages or even bare die that include ball bonds or that are adapted to be received by the solder ball pads.
  • solder reflow process controls are critical during soldering, particularly when utilizing fine pitch ball grid array packages.
  • Solder reflow process controls such as those set forth in "MICRON TECHNOLOGY INC. Technical Note TN-00-11 SMT BGA Assembly Design Recommendations" provide guidance for BGA reflow solder processes.
  • a stackable BGA layer 35 is formed as is illustrated in FIG. 4.
  • the layer is then preferably under-filled with a suitable under-fill material 36 such as EPOTEK U-300 to provide structural stability and to minimize temperature-related stresses due to CTE mismatch of the interposer board and BGA package. It is preferable to provide sufficient under-fill so as to extend slightly beyond the edge of the BGA package and interposer board as the under-fill eliminates voids along the access edge 25 which will be utilized as discussed further below.
  • a suitable under-fill material 36 such as EPOTEK U-300 to provide structural stability and to minimize temperature-related stresses due to CTE mismatch of the interposer board and BGA package. It is preferable to provide sufficient under-fill so as to extend slightly beyond the edge of the BGA package and interposer board as the under-fill eliminates voids along the access edge 25 which will be utilized as discussed further below.
  • multiple layers 35 may be bonded together using a suitable adhesive or epoxy 37 such as EPOTEK 353 to form a three-dimensional stack 40 of layers 35, forming at least one access plane 45.
  • a suitable adhesive or epoxy 37 such as EPOTEK 353
  • Mechanical assembly of multiple layers consists generally of aligning two or more layers 35 in a suitable fixture and bonding together using the appropriate adhesive.
  • access leads 30, i.e., access plane 45 are ground and lapped to expose the access leads as is illustrated in
  • FIG. 7 shows how access leads 30 may be rerouted between layers as desired by using conventional photolithography and plating techniques to create conductive interconnecting traces 50.
  • the entire access plane 45 may be metalized or coated with conductive material and the desired access leads isolated or interconnected by selectively removing conductive material using laser ablation, saw-cutting, etching or similar process. It is important that access plane be very planar with no voids to ensure the integrity of the layer interconnects.
  • the stack is preferably encapsulated with a suitable encapsulant to protect interconnecting traces 50.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)

Abstract

Selon l'invention, des couches (35) pouvant être empilées en modules multicouches tridimensionnels sont formées par interconnexion d'un module électronique à grille matricielle à billes (1) et d'une couche d'interposition (10) permettant le routage de signaux électroniques vers un plan d'accès (45). Les couches (35) sont remplies par le dessous et peuvent être liées ensemble de façon à former un empilement (40) de couches (35). Les conducteurs (30) sur le plan d'accès (45) sont interconnectés entre les couches (35), d'où la formation d'un module électronique à haute densité.
EP03818224A 2003-08-08 2003-08-08 Couches empilables contenant des modules a grille matricielle a billes Withdrawn EP1652233A4 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2003/024706 WO2005018000A1 (fr) 2002-02-07 2003-08-08 Couches empilables contenant des modules a grille matricielle a billes

Publications (2)

Publication Number Publication Date
EP1652233A1 true EP1652233A1 (fr) 2006-05-03
EP1652233A4 EP1652233A4 (fr) 2009-11-25

Family

ID=34885493

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03818224A Withdrawn EP1652233A4 (fr) 2003-08-08 2003-08-08 Couches empilables contenant des modules a grille matricielle a billes

Country Status (3)

Country Link
EP (1) EP1652233A4 (fr)
JP (1) JP2007521631A (fr)
AU (1) AU2003261429A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7676912B2 (en) * 2007-09-05 2010-03-16 Headway Technologies, Inc. Method of manufacturing electronic component package

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998031738A1 (fr) * 1997-01-17 1998-07-23 Loctite Corporation Compositions de resines thermodurcissables
US20020094603A1 (en) * 2000-06-21 2002-07-18 Isaak Harlan R. Three-dimensional memory stacking using anisotropic epoxy interconnections
US20030043650A1 (en) * 2001-09-03 2003-03-06 Mitsubishi Denki Kabushiki Kaisha Multilayered memory device
WO2003038861A2 (fr) * 2001-10-30 2003-05-08 Irvine Sensors Corporation Couches empilables encapsulant des microcircuits, avec couches d'interconnexion en chevauchement et procede de fabrication

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998031738A1 (fr) * 1997-01-17 1998-07-23 Loctite Corporation Compositions de resines thermodurcissables
US20020094603A1 (en) * 2000-06-21 2002-07-18 Isaak Harlan R. Three-dimensional memory stacking using anisotropic epoxy interconnections
US20030043650A1 (en) * 2001-09-03 2003-03-06 Mitsubishi Denki Kabushiki Kaisha Multilayered memory device
WO2003038861A2 (fr) * 2001-10-30 2003-05-08 Irvine Sensors Corporation Couches empilables encapsulant des microcircuits, avec couches d'interconnexion en chevauchement et procede de fabrication

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2005018000A1 *

Also Published As

Publication number Publication date
EP1652233A4 (fr) 2009-11-25
JP2007521631A (ja) 2007-08-02
AU2003261429A1 (en) 2005-03-07

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