EP1627456A1 - Method and arrangement for monitoring a power output stage - Google Patents

Method and arrangement for monitoring a power output stage

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Publication number
EP1627456A1
EP1627456A1 EP04730554A EP04730554A EP1627456A1 EP 1627456 A1 EP1627456 A1 EP 1627456A1 EP 04730554 A EP04730554 A EP 04730554A EP 04730554 A EP04730554 A EP 04730554A EP 1627456 A1 EP1627456 A1 EP 1627456A1
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EP
European Patent Office
Prior art keywords
pulse width
power output
semiconductor switches
output
output stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04730554A
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German (de)
French (fr)
Inventor
Frank Sader
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
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Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP1627456A1 publication Critical patent/EP1627456A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/08—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for dynamo-electric motors
    • H02H7/0833—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for dynamo-electric motors for electric motors with control arrangements
    • H02H7/0844—Fail safe control, e.g. by comparing control signal and controlled current, isolating motor on commutation error
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P29/00—Arrangements for regulating or controlling electric motors, appropriate for both AC and DC motors
    • H02P29/02—Providing protection against overload without automatic interruption of supply

Definitions

  • the invention relates to a method and an arrangement for monitoring a power output stage, the power output stage having at least one half bridge consisting of a series connection of two semiconductor switches and supplied with operating voltage, the semiconductor switches being controllable alternately in a conductive state and a non-conductive state by pulse-width-modulated pulses and wherein the connection point of the semiconductor switches of the at least one half bridge forms an output.
  • DC or EC motors are used to generate the support, which are controlled via an H-bridge or a B6-bridge by applying pulse-width-modulated pulses to the half-bridges.
  • the semiconductor switching elements usually OSFETs, are controlled by a control device (microcontroller or digital signal processor). Continuous monitoring of the effective voltages present at the output is required for fault detection.
  • the object of the present invention is to reliably monitor a power output stage with as little effort as possible, so that errors which can lead in particular to a dangerous state are identified.
  • the task is solved in the method according to the invention in that the respective pulse width of signals present at the output is compared with a respective target pulse width and that the power output stage is recognized as error-free if deviations do not go beyond a predetermined amount.
  • One advantage of the invention is that the entire circuit can be monitored in a simple manner from the outputs of the control device via control circuits (driver modules) and semiconductor switches of the bridges. Since the monitoring does not require any integrating elements, which were required, for example, when measuring the mean value of the output voltages, the evaluation can be carried out quickly and with only small tolerance fields and thus with high accuracy. This in turn means increased security.
  • the comparison is carried out in a processor which also generates the pulses to be supplied to the semiconductor switches.
  • the target pulse width and the pulse width of the output signals are evaluated in several periods during the comparison.
  • the comparison is made when the pulse widths are constant over a time required to measure the pulse width of the output signals.
  • the computing effort for the comparison and evaluation can be placed in a time in which the other programs of the control device are less active.
  • the comparison is made when the pulse widths change in a known manner over a time required to measure the pulse width of the output signals.
  • the object is achieved in that the signal at the at least one output can be fed to an input of a comparison device which is designed to compare the pulse width of the signal with the pulse width of the pulses.
  • the comparison device is part of a control device which generates the pulses which can be supplied to control inputs of the semiconductor switches via control circuits. This measure also increases the security of error detection.
  • a level adjustment circuit is arranged.
  • Figure 1 is a circuit diagram of an embodiment
  • Figure 2 diagrams of signals in the embodiment of Figure 1 and
  • FIG. 3 e circuit diagram of a further exemplary embodiment.
  • two MOSFETs Hu, Lu; Hv, Lv; Hw, Lw each have a half bridge 7, 8, 9 with outputs 10, 11, 12, to which one of the windings 13, 14, 15 of a brushless, permanently excited synchronous motor is connected in star connection.
  • the operating voltage ü is supplied to an input 16.
  • the arrangement further comprises a control device 20, which is known as such in connection with power output stages, is formed by a microcomputer or a digital signal processor and as such does not need to be explained in more detail in order to understand the invention.
  • Outputs of the control device 20 are connected to a control circuit 21, which generates control signals Au, Av, Aw for the MOSFETs Hu to Lw.
  • the control device 20 also has inputs to which voltages generated by a voltage divider 23, 2, 4, 25 can be supplied.
  • the voltage dividers have significantly higher resistance values than the windings 13,
  • the pulses supplied to the control circuit 21 by the control device 20 are generally derived from clock pulses which have a significantly higher frequency than the repetition frequency of the control pulses.
  • the control device is therefore also certain how many clock pulses the respective pulse is wide. If the number of clock pulses is paid from the leading edge to the trailing edge of the signal Su, Sv and Sw to be tested in the exemplary embodiment according to FIG. 1, this can easily be compared. Any tolerances caused by switching times of the control circuit 21 and the semiconductor switches will be taken into account.
  • FIG. 2 shows the control of the semiconductor switches, which form the three phases u, V, W, in such a way that the respective upper semiconductor switch is conductive at a level H, while the lower semiconductor switch m is controlled at a level L, the conductive state.
  • the three signals Su, Sv and Sw are shown schematically. Three periods are shown in each case, the duration of which is, for example, 50 as, which corresponds to a frequency of 20 kHz. Since this frequency is substantially greater than that of the rotating field, the width modulation forming the rotating field cannot be seen from FIG. 2. 2 represents a snapshot, so to speak, in which the interval of level H is greatest in phase U and smallest in phase W, while the interval of level L is smallest in phase U and in phase W is greatest.
  • the pulse widths Au, Su, Av, Sv, Aw, Sw are essentially the same.
  • Deviations including a complete failure of an impulse, are interpreted as a defect.
  • a separate comparison device 28 is provided, which, as in the first exemplary embodiment, is supplied with the output signals Su, Sv and Sw via voltage dividers and, on the other hand, with control signals generated by the control device.
  • the comparison device 28 for example a hard-wired circuit or a programmable device, such as a microprocessor.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Protection Of Static Devices (AREA)
  • Control Of Voltage And Current In General (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)

Abstract

The invention relates to a method and arrangement for monitoring a power output stage, whereby the power output stage has at least one half bridge, comprising a series circuit of two semiconductor switches supplied with an operating voltage. The semiconductor switches may be alternately controlled in a conducting state and a non-conducting state, by means of pulse-width modulated pulses and the connection point of the semiconductor switch of the at least one half bridge forms an output. According to the invention, each pulse width of the signals at the output is compared with a relevant set pulse width and the power output stage is recognised as fault-free when deviations do not exceed a given magnitude.

Description

Beschreibungdescription
Verfahren und Anordnung zur Überwachung einer LeistungsendstufeMethod and arrangement for monitoring a power output stage
Die Erfindung betrifft ein Verfahren und eine Anordnung zur Überwachung einer Leistungsendstufe, wobei die Leistungsendstufe mindestens eine aus einer Reihenschaltung zweier Halbleiterschalter bestehende und mit Betriebsspannung beauf- schlagte Halbbrücke aufweist, wobei die Halbleiterschalter durch pulsbreitenmodulierte Impulse abwechselnd m einen leitenden Zustand und einen nichtleitenden Zustand steuerbar sind und wobei der Verbindungspunkt der Halbleiterschalter der mindestens einen Halbbrücke einen Ausgang bildet.The invention relates to a method and an arrangement for monitoring a power output stage, the power output stage having at least one half bridge consisting of a series connection of two semiconductor switches and supplied with operating voltage, the semiconductor switches being controllable alternately in a conductive state and a non-conductive state by pulse-width-modulated pulses and wherein the connection point of the semiconductor switches of the at least one half bridge forms an output.
Insbesondere für sicherheitsrelevante Anwendungen in Kraftfahrzeugen, beispielsweise für eine elektrisch unterstutzte Lenkung, ist es erforderlich, jeden Fehler, der zu einem gefährlichen Zustand fuhren kann, zu erkennen. Im Falle elekt- risch unterstützter Lenkanlagen werden zur Erzeugung der Unterstützung DC- oder EC-Motoren eingesetzt, die ber eine H- Brucke bzw. eine B6-Brucke durch Anlegen von pulsbreitenmodu- lierten Impulsen an die Halbbrücken gesteuert werden. Die Halbleiterschaltelemente, meist OSFETs, werden von einer Steuereinrichtung (Mikrocontroller oder digitaler Signalprozessor) angesteuert. Zur Fehlererkennung ist eine durchgangige Überwachung der am Ausgang anliegenden Effektivspannungen erforderlich. Aufgabe der vorliegenden Erfindung ist es, eine Leistungsendstufe mit möglichst geringem Aufwand zuverl ssig zu überwachen, so dass Fehler, die insbesondere zu einem gefährlichen Zustand fuhren können, erkannt werden. In particular for safety-relevant applications in motor vehicles, for example for electrically assisted steering, it is necessary to recognize every fault that can lead to a dangerous state. In the case of electrically assisted steering systems, DC or EC motors are used to generate the support, which are controlled via an H-bridge or a B6-bridge by applying pulse-width-modulated pulses to the half-bridges. The semiconductor switching elements, usually OSFETs, are controlled by a control device (microcontroller or digital signal processor). Continuous monitoring of the effective voltages present at the output is required for fault detection. The object of the present invention is to reliably monitor a power output stage with as little effort as possible, so that errors which can lead in particular to a dangerous state are identified.
D e Aufgabe wird bei dem erfmdungsgemaßen Verfahren dadurch gelost, dass die jeweilige Pulsbreite von am Ausgang anstehenden Signalen mit einer jeweiligen Soll-Pulsbreite verglichen wird und dass die Leistungsendstufe als fehlerfrei er- kannt wird, wenn Abweichungen nicht über ein vorgegebenes Maß hinausgehen.The task is solved in the method according to the invention in that the respective pulse width of signals present at the output is compared with a respective target pulse width and that the power output stage is recognized as error-free if deviations do not go beyond a predetermined amount.
Ein Vorteil der Erfindung ist, dass die Überwachung der gesamten Schaltung von den Ausgangen der Steuereinrichtung über Ansteuerschaltungen (Treiberbausteine) und Halbleiterschalter der Brücken m einfacher Weise möglich ist. Da die Überwachung ohne integrierende Elemente auskommt, die beispielsweise bei einer Mittelwertmessung der Ausgangsspannungen erforderlich waren, ist die Auswertung schnell und mit nur gerin- gen Toleranzfeldern und somit mit hoher Genauigkeit möglich. Diese bedeutet wiederum eine erhöhte Sicherheit.One advantage of the invention is that the entire circuit can be monitored in a simple manner from the outputs of the control device via control circuits (driver modules) and semiconductor switches of the bridges. Since the monitoring does not require any integrating elements, which were required, for example, when measuring the mean value of the output voltages, the evaluation can be carried out quickly and with only small tolerance fields and thus with high accuracy. This in turn means increased security.
Vorzugsweise ist bei dem erfmdungsgemaßen Verfahren vorgesehen, dass der Vergleich m einem Prozessor erfolgt, der auch die den Halbleiterschaltern zuzuführenden Impulse erzeugt.It is preferably provided in the method according to the invention that the comparison is carried out in a processor which also generates the pulses to be supplied to the semiconductor switches.
Hierdurch wird eine besonders einfache und zuverlässige Hardware-Losung möglich. Bei manchen Prozessoren ist bereits ein sogenannter gated counter vorhanden, mit dem die verschiedenen Pulsbreiten bestimmt werden können. Die übrigen Verfah- rensschritte können leicht mit einer geringen Erweiterung des ohnehin in der Steuereinrichtung vorhandenen Programms durchgeführt werden.This makes a particularly simple and reliable hardware solution possible. Some processors already have a so-called gated counter with which the various pulse widths can be determined. The remaining process steps can easily be carried out with a slight expansion of the program which is already present in the control device.
Die in Steuereinrichtungen dieser Art verwendete Technik lasst in der Regel keine höheren Spannungen als 5V zu. Deshalb ist bei einer Weiterbildung des erfmdungsgemaßen Verfahrens vorgesehen, dass d e Signale an dem mindestens einen The technology used in control devices of this type generally does not allow voltages higher than 5V. Therefore, in a further development of the method according to the invention, it is provided that the signals on the at least one
Ausgang bezuglich des Pegels an den Prozessor angepasst werden.Output with regard to the level to be adapted to the processor.
um bei der Überwachung statistische Schwankungen auszuschlie- ßen, kann gemäß einer Weiterbildung vorgesehen sein, dass bei dem Vergleich die Soll-Pulsbreite und die Pulsbreite der Aus- gangssignale eweils mehrerer Perioden ausgewertet werden.In order to exclude statistical fluctuations during monitoring, it can be provided according to a further development that the target pulse width and the pulse width of the output signals are evaluated in several periods during the comparison.
Eine andere Weiterbildung besteht darin, dass der Vergleich erfolgt, wenn die Pulsbreiten über eine zur Messung der Pulsbreite der Ausgangssignale erforderliche Zeit konstant sind. Dadurch kann der Rechenaufwand für den Vergleich und die Auswertung in eine Zeit gelegt werden, in welcher die übrigen Programme dei Steuereinrichtung weniger aktiv sind. Dies kann auch dadurch erreicht werden, dass der Vergleich erfolgt, wenn sich die Pulsbreiten über eine zur Messung der Pulsbreite der Ausgangssignale erforderliche Zeit in bekannter Weise andern. Bei einer erfmdungsgemaßen Anordnung wird die Aufgabe dadurch gelost, dass das Signal an dem mindestens einen Ausgang einem Eingang einer Vergleichseinrichtung zufuhrbar ist, die zum Vergleich der Pulsbreite des Signals mit der Pulsbreite der Impulse ausgebildet ist. Ein besonders einfacher Ver- gleich ist bei der erfmdungsgemaßen Anordnung dadurch möglich, dass die Vergleichseinrichtung Teil einer Steuereinrichtung ist, welche die Impulse erzeugt, welche über Ansteuerschaltungen Steueremgangen der Halbleiterschalter zufuhrbar sind. Ferner wird durch diese Maßnahme die Sicherheit der Fehlererkennung erhöht .Another development is that the comparison is made when the pulse widths are constant over a time required to measure the pulse width of the output signals. As a result, the computing effort for the comparison and evaluation can be placed in a time in which the other programs of the control device are less active. This can also be achieved in that the comparison is made when the pulse widths change in a known manner over a time required to measure the pulse width of the output signals. In an arrangement according to the invention, the object is achieved in that the signal at the at least one output can be fed to an input of a comparison device which is designed to compare the pulse width of the signal with the pulse width of the pulses. A particularly simple comparison is possible in the arrangement according to the invention in that the comparison device is part of a control device which generates the pulses which can be supplied to control inputs of the semiconductor switches via control circuits. This measure also increases the security of error detection.
Auch bei der erfmdungsgemaßen Anordnung kann vorgesehen sein, dass zwischen dem mindestens einen Ausgang und dem Ein- In the arrangement according to the invention it can also be provided that between the at least one output and the input
gang der Steuereinrichtung eine Pegelanpassungsschaltung angeordnet ist.gear of the control device, a level adjustment circuit is arranged.
Die Erfindung lasst zahlreiche Ausfuhrungsformen zu. Eine da- von ist schematisch in der Zeichnung anhand mehrerer Figuren dargestellt und nachfolgend beschrieben. Es zeigt:The invention permits numerous embodiments. One of these is shown schematically in the drawing using several figures and is described below. It shows:
Figur 1 ein Schaltbild eines Ausfuhrungsbeispiels, Figur 2 Diagramme von Signalen bei dem Ausfuhrungsbeispiel nach Figur 1 undFigure 1 is a circuit diagram of an embodiment, Figure 2 diagrams of signals in the embodiment of Figure 1 and
Figur 3 e Schaltbild eines weiteren Ausfuhrungsbeispiels. Bei den dargestellten Ausfuhrungsbeispielen bilden je zwei MOSFETs Hu, Lu; Hv, Lv; Hw, Lw jeweils eine Halbbrücke 7, 8, 9 mit Ausgangen 10, 11, 12, an die jeweils eine der in Sternschaltung ausgeführten Wicklungen 13, 14, 15 eines burstenlo- sen permanent erregten Synchronmotors angeschlossen ist. Ei- nem Eingang 16 wird die Betriebsspannung üb zugeführt.Figure 3 e circuit diagram of a further exemplary embodiment. In the illustrated exemplary embodiments, two MOSFETs Hu, Lu; Hv, Lv; Hw, Lw each have a half bridge 7, 8, 9 with outputs 10, 11, 12, to which one of the windings 13, 14, 15 of a brushless, permanently excited synchronous motor is connected in star connection. The operating voltage ü is supplied to an input 16.
Die Anordnung umfasst ferner eine Steuereinrichtung 20, die als solche im Zusammenhang mit Leistungsendstufen bekannt ist, von einem Mikrocomputer oder einem digitalen Signalpro- zessor gebildet wird und als solche zum Verständnis der Erfindung nicht naher erläutert zu werden braucht. Ausgange der Steuereinrichtung 20 sind mit einer AnsteuerSchaltung 21 verbunden, welche Steuersignale Au, Av, Aw für die MOSFETs Hu bis Lw erzeugt. Die Steuereinrichtung 20 weist ferner Emgan- ge auf, denen von jeweils einem Spannungsteiler 23, 24, 25 erzeugte Spannungen zufuhrbar sind. Die Spannungsteiler weisen wesentlich höhere Widerstandswerte als die Wicklungen 13, The arrangement further comprises a control device 20, which is known as such in connection with power output stages, is formed by a microcomputer or a digital signal processor and as such does not need to be explained in more detail in order to understand the invention. Outputs of the control device 20 are connected to a control circuit 21, which generates control signals Au, Av, Aw for the MOSFETs Hu to Lw. The control device 20 also has inputs to which voltages generated by a voltage divider 23, 2, 4, 25 can be supplied. The voltage dividers have significantly higher resistance values than the windings 13,
14, 15 auf, um den Wirkungsgrad der Endstufe im Betrieb nicht zu verschlechtern.14, 15 in order not to deteriorate the efficiency of the output stage in operation.
Die der Ansteuerεchaltung 21 von der Steuereinrichtung 20 zu- geführten Impulse werden in der Regel aus Taktimpulsen abgeleitet, die eine wesentlich höhere Frequenz als die Wiederholfrequenz der AnSteuerimpulse aufweisen. Daher steht der Steuereinrichtung auch fest, wie viele Taktimpulse der jeweilige Impuls breit ist. Wird bei dem Ausfuhrungsbeispiel nach Fig. 1 von der Vorderflanke bis Ruckflanke des jeweils zu prüfenden Signals Su, Sv und Sw die Zahl der Taktimpulse gezahlt, so kann diese ohne weiteres verglichen werden. Dabei wird man eventuelle Toleranzen, die durch Schaltzeiten der AnsteuerSchaltung 21 und der Halbleiterschalter bedingt sind, berücksichtigen.The pulses supplied to the control circuit 21 by the control device 20 are generally derived from clock pulses which have a significantly higher frequency than the repetition frequency of the control pulses. The control device is therefore also certain how many clock pulses the respective pulse is wide. If the number of clock pulses is paid from the leading edge to the trailing edge of the signal Su, Sv and Sw to be tested in the exemplary embodiment according to FIG. 1, this can easily be compared. Any tolerances caused by switching times of the control circuit 21 and the semiconductor switches will be taken into account.
Fig. 2 zeigt die Ansteuerung der Halbleiterschalter, welche die drei Phasen u, V, W bilden, derart, dass bei einem Pegel H der jeweils obere Halbleiterschalter leitend st, wahrend bei einem Pegel L der untere Halbleiterschalter m den leitenden Zustand gesteuert wird. Außerdem sind die drei Signale Su, Sv und Sw schematisch dargestellt. Es sind jeweils drei Perioden dargestellt, deren Dauer, beispielsweise 50 as betragt, was einer Frequenz von 20 kHz entspricht. Da diese Frequenz wesentlich großer als diejenige des Drehfeldes ist, ist aus Fig. 2 die das Drehfeld bildende Breitenmodulation nicht erkennbar. Fig. 2 stellt sozusagen eine Momentaufnahme dar, bei welcher das Intervall des Pegels H in der Phase U am größten und in der Phase W am kleinsten ist, wahrend das In- tervall des Pegels L in der Phase ü am kleinsten und in der Phase W am größten ist . Bei ordnungsgemäßem Betrieb sind die Pulsbreiten Au, Su, Av, Sv, Aw, Sw im Wesentlichen gleich. 2 shows the control of the semiconductor switches, which form the three phases u, V, W, in such a way that the respective upper semiconductor switch is conductive at a level H, while the lower semiconductor switch m is controlled at a level L, the conductive state. In addition, the three signals Su, Sv and Sw are shown schematically. Three periods are shown in each case, the duration of which is, for example, 50 as, which corresponds to a frequency of 20 kHz. Since this frequency is substantially greater than that of the rotating field, the width modulation forming the rotating field cannot be seen from FIG. 2. 2 represents a snapshot, so to speak, in which the interval of level H is greatest in phase U and smallest in phase W, while the interval of level L is smallest in phase U and in phase W is greatest. When properly operated, the pulse widths Au, Su, Av, Sv, Aw, Sw are essentially the same.
Abweichungen, worunter auch ein vollständiger Ausfall eines Impulses zu verstehen ist, werden als Defekt interpretiert.Deviations, including a complete failure of an impulse, are interpreted as a defect.
Bei dem Ausführungsbeispiel nach Fig. 3 ist eine separate Vergleichseinrichtung 28 vorgesehen, der einerseits - wie bei dem ersten Ausführungsbeispiel - über Spannungsteiler die Ausgangssignale Su, Sv und Sw und andererseits von der Steuereinrichtung erzeugte AnsteuerSignale zugeführt werden. Für die Vergleichseinrichtung 28 stehen verschiedene Technologien zur Verfügung, beispielsweise eine festverdrahtete Schaltung oder eine programmierbare Einrichtung, wie beispielsweise ein Mikroprozessor. In the exemplary embodiment according to FIG. 3, a separate comparison device 28 is provided, which, as in the first exemplary embodiment, is supplied with the output signals Su, Sv and Sw via voltage dividers and, on the other hand, with control signals generated by the control device. Various technologies are available for the comparison device 28, for example a hard-wired circuit or a programmable device, such as a microprocessor.

Claims

Patentansprüche claims
1. Verfahren zur Überwachung einer Leistungsendstufe, wobei die Leistungsendstufe mindestens eine aus einer Reihen- Schaltung zweier Halbleiterschalter bestehende und mit Betriebsspannung beaufschlagte Halbbrücke aufweist, wobei die Halbleiterschalter durch pulsbreitenmodulierte Impulse abwechselnd in einen leitenden Zustand und einen nichtleitenden Zustand steuerbar sind und wobei der Verbindungs- punkt der Halbleiterschalter der mindestens einen Halbbrücke einen Ausgang bildet, dadurch geke nnzeichnet , dass die jeweilige Pulsbreite von am Ausgang anstehenden Signalen mit einer jeweiligen Soll- Pulsbreite verglichen wird und dass die Leistungsendstufe als fehlerfrei erkannt wird, wenn Abweichungen nicht über ein vorgegebenes Maß hinausgehen.1. A method for monitoring a power output stage, the power output stage having at least one half-bridge consisting of a series connection of two semiconductor switches and supplied with operating voltage, the semiconductor switches being controllable alternately into a conductive state and a non-conductive state by pulse-width-modulated pulses, and wherein the connection point of the semiconductor switch of the at least one half-bridge forms an output, characterized in that the respective pulse width of signals present at the output is compared with a respective target pulse width and that the power output stage is recognized as error-free if deviations do not exceed a predetermined amount.
2. Verfahren nach Anspruch 1, dadurch gekennz ei chnet , dass der Vergleich in einem Prozessor erfolgt, der auch die den Halbleiterschaltern zuzuführenden Impulse erzeugt.2. The method according to claim 1, characterized in that the comparison is carried out in a processor which also generates the pulses to be supplied to the semiconductor switches.
3. Verfahren nach Anspruch 2, dadurch gekennz ei chn et , dass die Signale an dem mindestens einen Ausgang bezüglich des Pegels an den Prozessor angepasst werden .3. The method according to claim 2, characterized in that the signals at the at least one output are adapted to the level of the processor.
4. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekenn z ei chnet , dass bei dem Vergleich die Soll-Pulsbreite und die Pulsbreite der Ausgangssignale jeweils mehrerer Perioden ausgewertet werden. 4. The method according to any one of the preceding claims, characterized in that the target pulse width and the pulse width of the output signals of several periods are evaluated in the comparison.
5. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennz ei chnet , dass der Vergleich erfolgt, wenn die Pulsbreiten über eine zur Messung der Pulsbreite der Ausgangssignale erforderliche Zeit kon- stant sind.5. The method according to any one of the preceding claims, characterized in that the comparison is carried out when the pulse widths are constant over a time required to measure the pulse width of the output signals.
6. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennz ei chn et , dass der Vergleich erfolgt, wenn sich die Pulsbreiten über eine zur Messung der Pulsbreite der Ausgangssignale erforderliche Zeit m bekannter Weise andern.6. The method according to any one of the preceding claims, characterized in that the comparison is carried out when the pulse widths change over a time m known to measure the pulse width of the output signals.
7. Anordnung zur Überwachung einer Leistungsendstufe, wobei die Leistungsendstufe mindestens eine aus einer Reihen- Schaltung zweier Halbleiterschalter (Hu, Lu; Hv, Lv; Hw, Lw) bestehende und mit Betriebsspannung beaufschlagte Halbbrücke (7, 8, 9) aufweist, wobei die Halbleiterschalter (Hu, Lu; Hv, Lv; Hw, Lw) durch pulsbreitenmodulierte Impulse abwechselnd in einen leitenden zustand und einen nichtleitenden Zustand steuerbar sind und wobei der Verbindungspunkt der Halbleiterschalter (Hu, Lu; Hv, Lv; Hw, Lw) der mindestens einen Halbbrücke (7, 8, 9) einen Ausgang (10, 11, 12) bildet, dadurch gekennz ei chnet , dass das Signal an dem mindestens einen Ausgang (10, 11, 12) einem Eingang einer Vergleichseinrichtung (20) zufuhrbar ist, die zum Vergleich der Pulsbreite des Signals mit der Pulsbreite der Impulse ausgebildet ist. 7. Arrangement for monitoring a power output stage, the power output stage having at least one half-bridge (7, 8, 9) consisting of a series connection of two semiconductor switches (Hu, Lu; Hv, Lv; Hw, Lw) and being supplied with operating voltage, the Semiconductor switches (Hu, Lu; Hv, Lv; Hw, Lw) can be controlled alternately into a conductive state and a non-conductive state by pulse-width-modulated pulses, and the connection point of the semiconductor switches (Hu, Lu; Hv, Lv; Hw, Lw) of the at least one Half bridge (7, 8, 9) forms an output (10, 11, 12), characterized in that the signal at the at least one output (10, 11, 12) can be fed to an input of a comparison device (20) which is designed to compare the pulse width of the signal with the pulse width of the pulses.
8. Anordnung nach Anspruch 7, dadu rc h gekennz ei chn et , dass die Vergleichseinrichtung Teil einer Steuereinrichtung (20) ist, welche die Impulse erzeugt, welche über Ansteuerschaltungen (21) Steuereingan- 8. Arrangement according to claim 7, so that the comparison device is part of a control device (20) which generates the pulses which control inputs via control circuits (21)
gen der Halbleiterschalter (Hu, Lu; Hv, Lv; Hw, Lw) zuführbar sind.gene of the semiconductor switch (Hu, Lu; Hv, Lv; Hw, Lw) can be fed.
9. Anordnung nach einem der Ansprüche 7 oder 8, d a d u r c h g e k e n n z e i c h n e t , dass zwischen dem mindestens einen Ausgang (10, 11, 12) und dem Eingang der Steuereinrichtung (20) eine Pegelanpassungsschaltung (23, 24, 25) angeordnet ist. 9. Arrangement according to one of claims 7 or 8, so that a level adjustment circuit (23, 24, 25) is arranged between the at least one output (10, 11, 12) and the input of the control device (20).
EP04730554A 2003-05-23 2004-04-30 Method and arrangement for monitoring a power output stage Withdrawn EP1627456A1 (en)

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DE10323908A DE10323908A1 (en) 2003-05-23 2003-05-23 Method and arrangement for monitoring a power output stage
PCT/EP2004/050666 WO2004105206A1 (en) 2003-05-23 2004-04-30 Method and arrangement for monitoring a power output stage

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US20070035976A1 (en) 2007-02-15
CN100583585C (en) 2010-01-20
WO2004105206A1 (en) 2004-12-02
CN1795599A (en) 2006-06-28
JP2006526381A (en) 2006-11-16
WO2004105206A8 (en) 2005-01-20
DE10323908A1 (en) 2004-12-23

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