EP1588500A1

EP1588500A1 - Receiver system and method for reduced swing differential clock

Info

Publication number: EP1588500A1
Application number: EP03710827A
Authority: EP
Inventors: Louis Lu-Chen Hsu; Karl Selander; Michael Sorna; Steven J. Zier
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 2003-01-31
Filing date: 2003-01-31
Publication date: 2005-10-26
Also published as: CN1714517A; AU2003214978A1; WO2004070968A1

Abstract

A high-speed receiver is disclosed herein which is sampled by a reduced swing clock, capable of receiving reduced swing differential input signals. In the disclosed method, a pair of differential input signals (DIN), (DIP) are sampled with a reduced swing clock. The method includes a precharge phase (P1), at which time the clock is low, in which voltages are differentiated at a pair of nodes (X), (Y) based on values of a pair of differential input signals (DIN), (DIP), which are preferably non return to zero reduced swing signals. The differentiated voltages cause at least one regenerated data signal output (DON), or (DOP) to begin transitioning during the precharge phase (P1) in response to a change in the pair of differential input signals.

Description

RECEIVER SYSTEM AND METHOD FOR REDUCED SWING DIFFERENTIAL CLOCK

Technical Field

The present invention relates to digital communications and more specifically to a system and method of sampling differential input signals with a reduced swing clock.

Background Art

Integrated circuits which include Complementary Metal Oxide Semiconductor (CMOS) receivers and drivers are commonly used in high speed data bus systems. In one example, described in US patent 5,355,391 , a bus input receiver includes a two-stage buffered sample amplifier. In such receiver, a small swing data signal present on the bus is sampled and amplified to a full swing signal within a single clock cycle. A rail to rail differential clock, i.e. a rail to rail clock having two complementary signals, samples the incoming data signals. Unfortunately, a rail to rail clock creates jitter noise which adversely affects both the switching speed and the jitter of the output signals, especially in systems designed to amplify small swing signals. Such jitter noise can result from the necessity that rail to rail clocks be used with a local clock buffer having strong drive strength. At transmission speeds of interest now, such clock buffers have been the source of intolerably high switching noise in output signals, prominent among which is jitter noise caused by mismatch of devices in the buffer.

Therefore, it would be desirable for an integrated circuit CMOS receiver to operate with a reduced swing clock rather than a rail to rail clock. However, receivers having conventional sense amplifiers cannot operate with clocks which do not swing from rail to rail, becoming ineffective or totally failing at high switching frequencies. In such receivers, when clock swing is reduced, the Vgs overdrive of p-type field effect transistor (PFET) precharge devices is reduced, resulting in an inadequately slow precharge rate, causing the receiver to fail at current speeds of interest.

Accordingly, a new CMOS receiver is needed which is capable of operating with a reduced swing clock at current speeds of interest.

Disclosure of the Invention

In the system and method of the invention, a new high-speed receiver is provided which is sampled by a reduced swing clock. The receiver is preferably capable of receiving reduced swing differential input signals. The receiver can achieve high data rate with low system jitter noise. In a preferred embodiment of the system, power and circuit area are conserved by the sharing of common circuitry needed for biasing during the precharge phase.

Accordingly, a method is provided in an integrated circuit, for sampling a pair of differential input signals with a reduced swing clock. The method includes a precharge phase (P1), at which time the clock (CLK) is low, in which voltages are differentiated at a pair of nodes (X), (Y) based on values of a pair of differential input signals (DIN), (DIP). The differentiated voltages cause at least one regenerated data signal output (DON), or (DOP) to begin transitioning during the precharge phase (P1) in response to a change in the pair of differential input signals.

According to a preferred aspect of the invention, differential input signals have reduced signal swing. The differential input signals may further be of the non return to zero (NRZ) type. In addition, the reduced swing clock is preferably of the non return to zero (NRZ) type. According to another aspect of the invention, a pair of differential input signals are applied to respective inputs of a pair of active devices, wherein, during the precharge phase the voltages are differentiated at the pair of nodes by a pair of active input devices coupled to the pair of nodes, and the pair of active input devices are controlled by the differential input signals. In such aspect, the active input devices are preferably coupled to sink a greater amount of current from one of the nodes during the precharge phase based on values of the differential input signals. In addition, the active devices are both preferably coupled to a first potential, wherein the first potential is raised during the precharge phase, thereby raising the voltages on each of the pair of nodes. The first potential is further preferably coupled through a device to a common node potential, wherein the common node potential, in turn, is raised during the precharge phase.

According to another aspect of the invention, the regenerated data signal is output as a pair of differential outputs. The differential outputs are preferably rail-to-rail signals.

According to another aspect of the invention, current flow is preferably increased between said common potential and ground during the precharge phase.

According to yet another aspect of the invention, a method is provided for further sampling a second pair of differential input signals with the reduced swing differential clock in the same clock cycle in which the first pair of differential input signals is sampled. In such aspect, the inverted clock is applied as a clock input for sampling the second pair of differential input signals. During a precharge phase when the inverted clock is low, the voltages at a pair of second nodes are differentiated based on values of the second pair of differential input signals. The differentiated second voltages then cause at least one second regenerated data signal output to begin transitioning during the precharge phase in response to change in the second pair of differential input signals.

According to yet another aspect of the invention, a method is provided for demultiplexing data on a pair of differential input signals with a reduced rate, reduced swing clock. The method includes generating a number "n" of clock phase offset, reduced duty cycle clocks for each cycle of a common clock. Each of the generated clocks is applied as a clock input to a respective sample latch for sampling the high-speed differential input signals. During a precharge phase when a respective clock is low, the voltages on a pair of nodes in a respective sample latch are differentiated based on values of the differential input signals. The respective differentiated voltages, in turn, cause at least one respective regenerated data signal output of the respective sample latch to begin transitioning during the precharge phase in response to change in the pair of differential input signals.

According to other aspects of the invention, systems are provided which perform the disclosed methods of the invention.

Brief Description of The Drawings

Figures 1 A and 1 B are block and schematic diagrams illustrating a first embodiment of the invention.

Figure 2 is a timing diagram illustrating operation according to a first method embodiment of the invention.

Figures 3A and 3B are block and schematic diagrams illustrating a second embodiment of the invention. Figures 4A, 4B and 4C are block and schematic diagrams illustrating a third embodiment of the invention.

Figure 5 is a diagram illustrating clock inputs provided to the third embodiment of the invention.

Modes for Carrying Out the Invention

Overcoming the aforementioned problems of the background art, in the following, systems and methods are disclosed for an integrated high speed data receiver capable of operating with a reduced swing clock, rather than a rail to rail clock.

Figures 1A and 1 B respectively illustrate, in block form, and schematically, a first system embodiment of the invention. As illustrated in Figure 1A, a system embodiment of the invention functions as a sample latch of a receiver unit in an integrated circuit for sampling a pair of differential input signals DIN and DIP with a reduced swing clock. The reduced swing clock is preferably a differential clock including a clock (CLK) and a complementary clock (bCLK) which is 180 degrees out of phase with the clock (CLK). From the sample latch 110 is output a pair of differential data signals DON and DOP regenerated from the differential inputs DIN and DIP. The invention is particularly suited to the sampling of differential input signals DIN and DIP having low signal swing (as compared to rail-to-rail signals which swing from ground to the voltage supply Vdd of the latch) and which are further of the non return to zero type. The use of low swing differential signals can assist in achieving higher data transfer rates because less amplification is needed per cycle and jitter is reduced. However, the invention does not require the differential input signals to be as such to operate. The signal swing of the differential clock input to the receiver is "reduced" in the sense that it does not swing from rail to rail in each cycle, but rather, swings between nonzero upper and lower levels with a smaller swing than rail to rail. The lower value of the clock is able to turn on the PFET precharge devices in the sample latch system but without overdriving them, the clock quickly turning off the PFET precharge devices again. For example, in a sample latch having a voltage source Vdd of 1.3 V, the signal swing of the clock can be, for example, between 1.3 V and 0.6 V rather than the full rail to rail swing from 1.3 V to 0.0 V.

The sample latch 110 is a type of sense amplifier of a receiver unit which employs an advantageous precharge scheme which increases signal sensing speed. In this sample latch 110, signal sensing speed is increased by rapidly precharging internal nodes during the first half clock cycle (precharge phase), such that at least one of the regenerated data signals DON, DOP begins transitioning prior to the clock peaking at the beginning of the second half clock cycle (sensing phase).

With reference to Figure 1 B, sample latch 110 contains a pair of cross- coupled CMOS inverters formed by devices n1 , p1 , n2 and p2, the CMOS inverters having outputs DON and DOP. In the drawings and description of the invention herein, devices which are denoted by the letter "n" and a number, for example "n1 ", represent NFETs (n-type MOS field effect transistors), while those denoted by the letter "p" and a number, for example "p1" represent PFETs (p-type MOS field effect transistors). Also included in sample latch 110 are a set of precharge devices p3, p4, p5, p6 and p7, and at nodes X and Y, a pair of active input devices n3 and n4, respectively, to which differential inputs DIN and DIP are applied, respectively. An additional device n5 is coupled to active input devices n3 and n4 at node Vc. Sample latch 110 is coupled at a common node potential (Vcom) of device n5 to a precharge circuit 120. The precharge circuit 120 includes a pull-up circuit 122 and a biasing circuit 124, both of which are coupled to the sample latch 110 at the common node potential Vcom. The biasing circuit 124 preferably includes an NFET device n7 in which the source is tied to

Vcom, the drain tied to ground, and the gate tied to a constant bias voltage. The purpose of the precharge circuit is to help raise the voltages on the nodes X and Y within the sample latch 110 during the precharge phase to a point at which their voltages begin to differentiate based on the values of the differential input signals DIN and DIP provided thereto. The cross-coupled

CMOS inverters are linked to the nodes X and Y in such a way that the outputs of the sample latch DON and DOP move with the voltages of nodes X and Y. That way, at the end of the precharge phase, while the clock is still nearing its peak for the subsequent sensing phase, at least one of the regenerated output signals DON and DOP already begins transitioning when there is a change in the differential input signals.

The precharge circuit 122 is arranged to conduct current during the precharge phase when the clock (CLK) is low and a complementary clock (bCLK) is high. As a consequence, the common node potential Vcom rises during the precharge phase, as does the potential at Vc, which follows it by virtue of device n5 having its drain tied to the common node potential, and device n5 being partially conductive as CLK rises from the bottom of its swing towards the end of the precharge phase. Precharge circuit 122 includes an active device n6, preferably an NFET having a gate tied to bCLK, and coupled to the voltage source Vdd through a resistive device r1.

Differential input signals DIN and DIP arriving from transmission lines, preferably after boosting by an analog preamplifier, are input to a pair of active devices n3 and n4, which have their drains tied together at node Vc. These differential input signals DIN and DIP arrive by the middle of the precharge phase in order to permit the sample latch 110 to begin differentiating the outputs DON and DOP while the clock is still low (i.e. while the clock is still transitioning and before it peaks at the beginning of the sensing phase).

During the precharge phase, PFET devices p3, p4, p5, p6 and p7 are turned on. Devices p4 and p6 provide current flow to nodes X and Y, which then flows differentially through active devices n3 and n4, as controlled by the values of the differential inputs DIN and DIP. Devices p4 and pβ are critical, since they help pull up the voltage levels of both nodes X and Y to a higher level, at which differences in voltages between the nodes can be amplified.

Equalization device p7 is a preferred feature, but not a requirement of the invention. Device p7 is preferred to help raise the voltages at both nodes X and Y early during the precharge phase. When the inputs DIN and DIP reverse states (change polarities) from one cycle to the next, device p7 helps to more quickly precharge the nodes X and Y to voltages which can then be differentiated based on the states of inputs DIN and DIP then present. Thereafter, as the clock rises towards the end of the precharge cycle, the action of device p7 progressively diminishes until it turns off. Then, the voltages at nodes X and Y become differentiated based on the then existing states of the differential inputs DIN and DIP.

The operation of the first embodiment of the invention will now be described, with reference to the timing diagram of Figure 2. The timing of the waveforms in all of graphs A) through E) are drawn to the same scale and are simultaneous. The waveforms in graph (A) represent differential inputs DIN and DIP to the sample latch 110, each of which preferably has reduced swing and is of the non return to zero type (in the example swinging between 0.85 V and 1.3 V). Graph (B) shows a reduced swing non return to zero differential clock consisting of the waveforms CLK, and its complement bCLK. The timing of all other waveforms shown in Figure 2 is controlled by CLK and bCLK, except for the differential inputs DIN and DIP. CLK and bCLK preferably swing between 0.6 V and 1.3 V. Graphs C) and D) represent voltages at internal nodes of X and Y, Vc and Vcom, respectively. In graph E), DON and DOP represent the differential outputs of the sample latch 110.

The cycles of the differential clock in graph B) are divided into precharge phases P1 , P2 and P3, and sensing phases SO, S1 and S2. During the precharge phases, CLK goes low and bCLK goes high, which in turn activates precharge devices p3, p4, p5, p6, and p7 at which time internal nodes X and Y begin to rise from their lows. During the middle of the precharge phase all devices including optional equalization device p7 are their most fully activated, such that nodes X and Y have both risen substantially, and exhibit nearly the same voltages, due to the operation of optional equalization device p7. Thus, for example, by the middle of precharge phase P1 , internal nodes X and Y have risen off their lows to about half of their final values.

The differential inputs DIN and DIP are timed such that they reach their peak values prior to the end of the precharge cycle. While the differential inputs DIN and DIP exhibit a voltage difference of about 0.45 V when they stay the same in polarity from one cycle to the next (representing a differential peak-to-peak signal difference of 0.9 V), because of intersymbol interference

(ISI), the voltage difference between DIN and DIP is much less when they reverse state (change polarity), especially when the state reversal is followed by a second state reversal in the next cycle. This is the situation shown in Figure 2 graph A) at time to. At such time, the peak-to-peak signal difference between DIN and DIP is reduced to a small signal about one quarter to one half of the peak-to-peak signal difference that exists when DIN and DIP stay the same from one cycle to the next. During the latter half of the precharge phase, as CLK rises off its low, the early arrival of the differential inputs DIN and DIP begin differentiating the voltages at internal nodes X and Y. These node voltages, in turn, begin driving the CMOS inverter pairs n1 , p1 , and n2, p2 of the sample latch 110 to their final values before the end of the precharge phase when CLK reaches its peak. Thus, during the latter half of precharge phase P1 , with DIN showing a change in state from low to high, and DIP showing the opposite, device n3 is turned on more fully than device n4, which is beginning to turn off. In consequence, the nodes X and Y begin to differentiate, with Y going higher than X.

Meanwhile, during the precharge phase, the high state of bCLK turns on device n6 which causes the node potential at Vcom to rise, and Vc as well, which follows the rise in voltage Vcom through device n5 (which at that time appears as a resistive element). As shown in precharge phase P1 , the increase in Vc at time to boosts the voltages at both nodes X and Y at that time, allowing them to differentiate. Then, the voltages on these nodes begins to fall again, as Vc and Vcom fall and n5 more fully turns on. By the time CLK rises to 1.0 V, at time t1 , thus marking the beginning of the sensing phase, nodes X and Y show a substantial voltage difference (Δ V1). By virtue of the early signal differentiation at nodes X and Y, before the precharge phase P1 has ended, output signal DON has already begun transitioning off its low towards its final value high, and the output signal DOP has begun transitioning off its high towards its final value low. Once these signals have completed transitioning, the sample latch 110 then holds these outputs through sensing phase S1.

During the subsequent precharge phase P2, the process repeats again, except this time the differential inputs DIN and DIP remain at the same states (same polarities) from one cycle to the next. Consequently, the unchanged inputs DIN and DIP allow a longer time for active input devices n3 and n4 to differentiate the node voltages, and therefore the voltages at nodes X and Y become more differentiated. Once again, the boosted voltage Vc during the precharge phase helps differentiate the voltages at nodes X and Y as they peak and begin to fall again. This time, node X has the higher voltage as the CLK leaves the precharge phase (time t2) because of the higher DIP signal at device n4. As a result, nodes X and Y are differentiated by a voltage (Δ V2) at time t2. This, in turn, causes the outputs DON and DOP to begin transitioning between states before the end of precharge phase P2. Accordingly, prior to the middle of the sensing phase S2, the outputs DON and DOP are fully differentiated.

In the foregoing manner, the sense amplifier 110, having a low swing differential clock input and a pair of differential inputs DIN and DIP, is able to produce fully differentiated outputs DON and DOP. Moreover, the differential inputs need not be rail to rail, and can also be non return to zero, as utilized in the preferred embodiment described here. The voltage boosting operation of the precharge circuit 120 and the charging of internal nodes X and Y in the early portion of the precharge phase enable such operation of the sense amplifier 120.

Figures 3A and 3B respectively illustrate, in block form, and schematically, a second system embodiment of the invention. As illustrated in

Figure 3A, in this embodiment, a pair of sample latches 310 and 311 are arranged to share one precharge circuit 320 so that power and chip area can be conserved. The first sample latch 310 is sampled by the CLK signal, while the second sample latch 311 is sampled by the complementary clock, bCLK.

As further illustrated in Figure 3B, each of the sample latches 310 and

311 contains a pair of cross-coupled CMOS inverters. Each sample latch 310, 311 is coupled to the same precharge circuit 320 which has a transistor n36, preferably an NFET arranged as for diode operation, having its gate tied to the source, the NFET being coupled to a voltage supply Vdd through a resistive element r31. Both sample latches 310 and 311 are connected together to transistor n36 and to a biasing device n37 at a common potential (VCOM). The biasing device is preferably an n-type field effect transistor (NFET) having its source coupled to the common potential Vcom, and its drain tied to ground. The gate of the biasing device n37 is tied to a constant bias voltage (CBIAS).

The operation of the dual sample latch of a receiver unit is as follows: when the first sample latch 310 is in a sensing phase at which time CLK is high, the second sample latch 311 , which receives the complementary clock, bCLK, in place of CLK, is in a precharge phase, because bCLK is low at that time. The low bCLK input makes device n52 more resistive at that time, such that the voltage Vc2 of sample latch 311 rises. This in turn helps to boost the voltages at nodes X2 and Y2 of sample latch 311 so they are precharged and then differentiated during the latter half of the precharge phase according to values of the differential inputs DIN2 and DIP2 presented thereto.

At the same time as the above operations occur in sample latch 311 which is in the precharge phase, sample latch 310 is in the sensing phase. During such time, the biasing device n37 does not boost the voltage level of

Vc1 in sample latch 310, because device n51 is turned on at that time, making the voltage at Vc1 nearly equal to that at Vcom. At such time, the sensing operation is completed in sample latch 310 and data outputs DON1 and DOP1 reach their final values and are held until the precharge phase of the next cycle. Thereafter, sample latch 310 enters the precharge phase of the next cycle, during which time sample latch 311 performs sensing and holds its outputs DON2 and DOP2 until the precharge phase of its next cycle. Comparing the second embodiment of the invention (Figures 3A-3B) to the first embodiment (Figures 1A-1 B), it will be understood that power and chip area are conserved in the second embodiment, since both sample latches 310 and 311 share just one precharge circuit 320, rather than each sample latch having its own precharge circuit 120 which has the same number of devices and arrangement as that of precharge circuit 320.

Figure 4A is a block and schematic diagram illustrating a third embodiment of the invention. In this embodiment, a pair of incoming differential data inputs DIN_N, and DIN_P are sampled by an arrangement of six sample latches 410, 411 , 510, 511 , 610 and 611. The sample latches are arranged to sample and hold data according to six clock signals CLK0 through CLK5, all derived from a common clock CLKA through a clock generator circuit 450. These clock signals are all non return to zero signals having reduced signal swing, as described above relative to Figures 1A, 1 B and 2, and are arranged to sample differential data inputs which are preferably non return to zero and have reduced signal swing, as well. As will be understood, the six sample latches 410 through 611 are arranged to demultiplex the data arriving on differential inputs DIN and DIP, each sample latch producing outputs, e.g. DON0 and DOP0 for sample latch 410, at a rate which is one sixth of the data switching rate of DIN and DIP. Outputs of each sample latch, e.g. DON0 and DOP0 of sample latch 410, are further latched by a master-slave flip-flop, e.g. FFO, as rail to rail signals, and then provided to a buffer, e.g. BUF0, to drive a data output signal, e.g. DOUT_0, to its destination.

In this embodiment, similar to the embodiment illustrated in Figures 3A and 3B, each pair of sample latches shares a common precharge circuit. For example, as illustrated schematically in Figure 4B, the pair of sample latches

410, 411 shares a precharge circuit 420. Interconnection of each sample latch 410, 411 to differential inputs DIN and DIP and differential clock signals CLK0 and CLK3 are shown in Figure 4B. Referring to Figure 4A again, a current bias distribution circuit 430, preferably including a band-gap reference, a bias generator, and a current mirror device, is coupled to the node potential Vcom to each of the precharge phase circuits 420, 520 and 620 used by sample latches 410 through 411. Such circuit 430, used by all six sample latches, then takes the place of device n37 (Figure 3A). In such case, the precharge circuit 420a, attached to each pair of sample latches, e.g. 410, 411 , has the construction as shown in Figure 4C.

Waveforms of the clock signals CLK0 through CLK5 are illustrated in Figure 5. All of the clock signals swing between the same reduced swing low and high levels L and H and have the same period T. As apparent from Figure 5, the signals CLK0 and CLK3 are complementary; as are CLK1 and CLK4, and CLK2 and CLK5. Each clock signal CLK0 through CLK5 is offset from every other clock signal, being separated in phase from each other by one sixth of the period T. The clock pair CLK1 and CLK4 are input to sample latch pair 510, 511 , while the clock pair CLK2 and CLK5 are input to sample latch pair 610, 611 , in the manner analogous to that shown in Figure 4B.

Referring again to Figure 4A, the operation of the system is described. A pair of differential data signals DIN_N and DIN_P, arriving from a transmission line, are amplified by an analog pre-amplifier 460 and provided to each of the six sample latches 410 through 611. Each of the six sample latches 410 through 611 then samples the data from differential inputs DIN and DIP in turn, according to the phase (e.g. CLK0, etc. ) of the clock provided thereto, and provides sample outputs, e.g. DON0, DOP0 to the flip- flop, e.g. FFO attached thereto, which is then driven onto a line by a buffer, e.g. BUFO, as a signal, e.g. DOUT_0. For example, sample latch 410 senses the incoming data on DIN and DIP and holds valid data during phase SO, while sample latch 510 does the same during phase S1 , and sample latch 610 does the same during phase S2. Thereafter, sample latch 411 senses the incoming data on DIN and DIP and holds valid data during phase S3, while sample latch 511 does the same during phase S4, and sample latch 611 does the same during phase S5. It will be understood that data output lines DOUT_0 through DOUT 5 are driven in the same order as the sample latches to which they are coupled.

From the foregoing description of the preferred embodiments it will be apparent that the present invention provides a system and method of sampling a data signal with a reduced signal swing clock. Such invention has applicability to the reception of high speed data while reducing system noise due to clock jitter, thereby leading to improved signal to noise margins, increased switching speed of signals which can be received, and potentially lower power consumption.

While the invention has been described herein in accordance with certain preferred embodiments thereof, those skilled in the art will recognize the many modifications and enhancements which can be made without departing from the true scope and spirit of the present invention, limited only by the claims appended below.

Industrial Applicability

The invention is applicable to methods and systems of digital communications.

Claims

ClaimsWhat is claimed is:

1. In an integrated circuit, a method of sampling a pair of differential input signals with a reduced swing clock, comprising:

during a precharge phase when said clock is low, differentiating voltages at a pair of nodes based on values of a pair of differential input signals;

said differentiated voltages causing at least one regenerated data signal output to begin transitioning during said precharge phase in response to change in said pair of differential input signals.

2. The method of claim 1 wherein said differential input signals have reduced signal swing.

3. The method of claim 2 wherein said differential input signals further are of the non return to zero (NRZ) type.

4. The method of claim 1 wherein said reduced swing clock is of the non return to zero (NRZ) type.

5. The method of claim 3 further comprising: applying said pair of differential input signals to respective inputs of a pair of active input devices; wherein, during said precharge phase said voltages are differentiated at said pair of nodes by a pair of active input devices coupled to said pair of nodes, said pair of active devices being controlled by said differential input signals.

6. The method of claim 5 wherein said active input devices are coupled to sink a greater amount of current from one of said nodes during said precharge phase based on values of said differential input signals.

7. The method of claim 6 wherein said active input devices are both coupled to a first potential, said first potential being raised during said precharge phase, thereby raising said voltages on said nodes.

8. The method of claim 7 wherein said first potential is coupled through a device to a common node potential, said common node potential, in turn, being raised during said precharge phase.

9. The method of claim 1 wherein said regenerated data signal is output as a pair of differential outputs.

10. The method of claim 9 wherein said differential outputs are rail-to-rail signals.

11. The method of claim 1 further comprising increasing current from said common node potential to ground during said precharge phase.

12. The method of any of claims 1-11 wherein said pair of differential input signals are sampled in a first sample latch of a receiver, said method further including sampling a second pair of differential input signals in a second sample latch of said receiver in the same cycle of said clock in which said first pair of differential input signals is sampled, comprising: applying a complementary clock, having reduced swing and being complementary to said clock, as a clock input to said second sample latch for sampling said second pair of differential input signals; during a precharge phase when said complementary clock is low, differentiating second voltages at a pair of second nodes of said second sample latch, based on values of said second pair of differential input signals; said differentiated second voltages causing at least one second regenerated data signal output of said second sample latch to begin transitioning during said precharge phase in response to change in said second pair of differential input signals.

13. The method of any of claims 1-11 for demultiplexing data on a pair of differential input signals with a reduced rate, reduced swing clock, including: generating a number "n" of clock phase offset, reduced duty cycle, reduced swing clocks for each cycle of a common clock; applying each of said number "n" of said reduced swing clocks as a respective clock input to a respective sample latch of a number "n" of sample latches; during a precharge phase when said respective clock input is low, differentiating voltages at a pair of nodes of said respective sample latch based on values of said pair of differential input signals; said differentiated voltages causing at least one regenerated data signal output of said respective sample latch to begin transitioning during said precharge phase in response to change in said pair of differential input signals.

14. A system, having at least one sample latch, for sampling a pair of differential input signals according to the method of any of claims 1 through 13.

15. The system according to any of claims 1 through 13 comprising a transistor coupled to control current between said first potential and said common node potential of said at least one sample latch in response to said clock input.

16. The system of claim 15 further comprising a transistor coupled to control current between said common node potential and ground.

17. The system of claim 15 wherein each said sample latch further comprises a pair of precharge devices coupled to control current between a voltage source and said nodes of each said sample latch.

18. The system of claim 17 further comprising an equalization device coupled to control current between said nodes.