CN1714517A - Receiver system and method for reduced swing differential clock - Google Patents
Receiver system and method for reduced swing differential clock Download PDFInfo
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- CN1714517A CN1714517A CN03825622.3A CN03825622A CN1714517A CN 1714517 A CN1714517 A CN 1714517A CN 03825622 A CN03825622 A CN 03825622A CN 1714517 A CN1714517 A CN 1714517A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0292—Arrangements specific to the receiver end
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
- H03K3/356139—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
Abstract
A high-speed receiver is disclosed herein which is sampled by a reduced swing clock, capable of receiving reduced swing differential input signals. In the disclosed method, a pair of differential input signals (DIN) and (DIP) are sampled with a reduced swing clock. The method includes a precharge phase (P1), at which time the clock is low, in which voltages are differentiated at a pair of nodes (X), (Y) based on values of a pair of differential input signals (DIN), (DIP), which are preferably non return to zero reduced swing signals. The differentiated voltages cause at least one regenerated data signal output (DON), or (DOP) to begin transitioning during the precharge phase (P1) in response to a change in the pair of differential input signals.
Description
Technical field
The present invention relates to digital communication, relate more particularly to use the system and method for the differential input signal of clock sampling that has reduced the amplitude of oscillation.
Background technology
The integrated circuit that comprises complementary metal oxide semiconductors (CMOS) (CMOS) receiver and driver is generally used for the high speed data bus system.In an example, the bus input sink of describing in US patent 5,355,391 comprises the level 2 buffering sampling amplifier.In this receiver, the little amplitude of oscillation data-signal that presents on the bus is sampled and is enlarged into the full swing signal in the single clock cycle.Rail-to-rail differential clock promptly has the rail-to-rail clock of two complementary signals, the data-signal of sampling input.Unfortunately, rail-to-rail clock causes jittering noise, and it influences the shake of conversion speed and output signal unfriendly, especially in designing with the system of amplifying little amplitude of oscillation signal.This jittering noise can be caused with the necessity that the local clock buffer with strong actuating force uses by rail-to-rail clock.Under the present transmission speed of being concerned about, this clock buffer has become the root of insupportable high conversion noise in the output signal, and wherein outstanding is the jittering noise that is caused by not matching of device in the buffer.
Therefore, to come work with the clock that reduced the amplitude of oscillation rather than rail-to-rail clock be desirable to a kind of integrated circuit CMOS receiver.But the receiver with conventional sense amplifier can not be not to be that clock from rail-to-rail swing comes work, and the efficient that becomes under high switching frequency is low or fall flat.In this receiver, when the pendulum width of cloth reduced at that time, the Vgs blasting of p type field-effect transistor (PFET) precharge device was reduced, and causes unsuitable slow precharge rate, causes receiver to fail under the current speed of being concerned about.
Therefore, need can be under the current speed of being concerned about with the new CMOS receiver of the clock work that reduced the amplitude of oscillation.
Summary of the invention
In system and method for the present invention, a kind of usefulness has reduced the new high-speed receiver that the clock of the amplitude of oscillation samples and has been provided.This receiver preferably can receive the differential input signal that has reduced the amplitude of oscillation.This receiver can realize having the high data rate of low system jitter noise.In the preferred embodiment of system, power and circuit area are saved by sharing the required omnibus circuit of pre-charging stage biasing.
Therefore, a kind of being used in integrated circuit is provided with the method for the clock sampling pair of differential input signals that reduced the amplitude of oscillation.This method comprises pre-charging stage (P1), and clock (CLK) is a low level at that time, and wherein voltage is located difference based on pair of differential input signals (DIN), (DIP) at a pair of node (X), (Y).Differential voltage causes at least one regenerated data signal output (DON) or (DOP) change of differential input signal is begun to change in response to this in pre-charging stage (P1).
According to a preferred aspect of the present invention, differential input signal has the signal swing that has reduced.Differential input signal can also be non-return-to-zero (NRZ) type.In addition, the clock that reduced amplitude of oscillation non-return-to-zero (NRZ) type preferably.
According to another aspect of the present invention, pair of differential input signals is applied to the corresponding input of a pair of active device, wherein pre-charging stage voltage by be connected to this to a pair of active entering apparatus of node at this to node place difference, and should control by differential input signal active entering apparatus.Aspect this, active entering apparatus preferably connects together to weaken relatively large electric current from one of node in pre-charging stage based on the value of differential input signal.In addition, active device preferably all is connected to first electromotive force, and wherein this first electromotive force raises in pre-charging stage, thereby raises this to the voltage on each of node.First electromotive force more preferably is connected to common node potential by device, and wherein this common node potential raises in pre-charging stage again.
According to another aspect of the present invention, regenerated data signal is output as pair of differential output.The preferably rail-to-rail signal of this differential output.
According to another aspect of the present invention, electric current preferably increases between described common potential and ground in pre-charging stage.
According to a further aspect of the invention, a kind of phase that is sampled in pair of differential input signals
Be provided with the method for second pair of differential input signal of the further sampling of the differential clock that has reduced the amplitude of oscillation in the cycle with clock.Aspect this, inversion clock is applied for the clock input of the second pair of differential input signal that be used to sample.In pre-charging stage, when inversion clock is low level, at the voltage at a pair of Section Point place based on the value of second pair of differential input signal and difference.Second voltage of difference causes at least one second regenerated data signal output to begin in response to the change of second pair of differential input signal to change in pre-charging stage then.
According to a further aspect of the invention, a kind of method of decomposing the data on the pair of differential input signals with the clock multichannel that has reduced speed and reduced the amplitude of oscillation is provided.This method comprises that each cycle for common clock produces the clock that has reduced buty cycle of " n " individual clock phase skew.Each of the clock that produces is applied to the respective sample latch of the high speed differential input signal that is used to sample as clock input.In pre-charging stage, when corresponding clock was low level, the voltage on a pair of node in the respective sample latch was based on the value of differential input signal and difference.Respective differentiated voltages causes the corresponding regenerated data signal output of at least one of respective sample latch the change of differential input signal to be begun to change in response to this in pre-charging stage again.
According to other aspects of the invention, carrying out the openly system of method of the present invention is provided.
Description of drawings
Figure 1A and 1B are the block diagrams of explanation first embodiment of the present invention.
Fig. 2 is the sequential chart of explanation according to the operation of the first method embodiment of the present invention.
Fig. 3 A and 3B are the block diagrams of explanation second embodiment of the present invention.
Fig. 4 A, 4B and 4C are the block diagrams of explanation the 3rd embodiment of the present invention.
Fig. 5 is the figure that explanation offers the clock input of the 3rd embodiment of the present invention.
Implement mode of the present invention
In order to overcome the foregoing problems of background technology, below, can be disclosed with the system and method for the integrated high-speed data sink of the clock that reduced the amplitude of oscillation rather than rail-to-rail (rail to rail) clock work.
Figure 1A and 1B schematically illustrate first system implementation plan of the present invention with the block diagram form respectively.As shown in Figure 1A, system implementation plan of the present invention is used as the sample latch with the acceptor unit in the integrated circuit of clock sampling pair of differential input signals DIN that has reduced the amplitude of oscillation and DIP.This clock that has reduced the amplitude of oscillation preferably comprises the differential clock of clock (CLK) and complementary clock (bCLK), and complementary clock (bCLK) and clock (CLK) be phasic difference 180 degree mutually.Export from the pair of differential data-signal DON and the DOP of differential input DIN and DIP regeneration from sample latch 110.The present invention is particularly suitable for having the low signal amplitude of oscillation (the rail-to-rail signal of supplying with Vdd with the voltage that swings to latch from earth potential is compared) and be the differential input signal DIN of non-return-to-zero type and the sampling of DIP.The use of low-swing differential signal can help to obtain the higher data transmission rate, because each cycle needs less amplification and shake to reduce.But the present invention does not need differential input signal to work like this.
The signal swing that is input to the differential clock of receiver " reduces " in the sense, and promptly it is not from rail-to-rail swing in each cycle, but swings between the level up and down at the non-zero that has than the rail-to-rail little amplitude of oscillation.The low-value of clock in can the conducting sample latch system the PFET precharge device but can blasting they, clock turn-offs the PFET precharge device once more apace.For example, in the sample latch of the voltage source V dd with 1.3V, the signal swing of clock can be for example between 1.3V and 0.6V, rather than the whole rail-to-rail amplitude of oscillation from 1.3V to 0.0V.
With reference to Figure 1B, sample latch 110 comprises by device n1, p1, and the CMOS inverter of the pair of cross coupling that n2 and p2 constitute, this CMOS inverter has output DON and DOP.Here at accompanying drawing of the present invention with in describing, represent NFET (n type MOS field-effect transistor) by letter " n " and numerical example as the device of " n1 " expression, and represent PFET (p type MOS field-effect transistor) as those devices of " p1 " expression by letter " p " and numerical example.Also comprise one group of precharge device p3 in the sample latch 110, p4, p5, p6 and p7, and respectively at differential a pair of active entering apparatus n3 and the n4 that imports DIN and DIP of applying respectively of nodes X and Y place.Other device n5 is connected to active entering apparatus n3 and n4 at node Vc place.
Pre-charge circuit 122 is configured in pre-charging stage and is low level and complementary clock (bCLK) conduction current when high-order when clock (CLK).Thereby, common node potential Vcom rises in pre-charging stage, the electromotive force at Vc place relies on the device n5 that makes its drain electrode be connected to common node potential and then to rise, and when CLK from the bottom of its amplitude of oscillation during towards direction rising that pre-charging stage finishes device n5 partly conduct electricity.Pre-charge circuit 122 comprises active device n6, preferably makes grid be connected to bCLK and is connected to the NFET of voltage source V dd by resistance device r1.
Preferably be input to a pair of active device n3 and the n4 that the drain electrode that makes them connects together at node Vc by the differential input signal DIN that arrives from transmission line of analog preamplifier after raising and DIP.These differential input signal DIN and DIP arrive in the middle of pre-charging stage, so as to allow sample latch 110 when clock during still for low level (work as that clock still changes and it in the stage of reading begin locate peaking before) begin output DON and DOP difference.
In pre-charging stage, PFET device p3, p4, p5, p6 and p7 are switched on.Device p4 and p6 provide current to nodes X and Y, and electric current flows through to difference active device n3 and n4 then, and this is by the value control of differential input DIN and DIP.Device p4 and p6 are crucial, because move higher level on the voltage level of they helps with two nodes X and Y, can be exaggerated in the voltage difference between the node on this level.Equalizing device p7 is preferred characteristic, but is not necessary condition of the present invention.Device p7 is preferably at early stage two nodes X of help rising of pre-charging stage and the voltage at Y place.When input DIN and DIP from one-period to the next cycle inverted status when (change polarity), device p7 helps more promptly nodes X and Y to be pre-charged to certain voltage, these voltages then can be based on the state of input DIN that existed at that time and DIP and difference.Thereafter, when clockwise the direction rising of precharge cycle end at that time, the function of device p7 little by little weakens up to it turn-offed.Then, the voltage at nodes X and Y place is based on the state that existed at that time of differential input DIN and DIP and by difference.
The operation of first embodiment of the present invention is described referring now to the sequential chart of Fig. 2.All curve chart A) to E) the sequential of waveform draw by same ratio and be synchronous.Waveform in the curve chart (A) is represented the differential input DIN and the DIP of sample latch 110, and each preferably has the amplitude of oscillation that has reduced and is (the swinging between 0.85V and 1.3V in this example) of non-return-to-zero type.Curve chart (B) shows the non-return-to-zero differential clock that has reduced the amplitude of oscillation that is made of waveform CLK and complementary bCLK thereof.Except differential input DIN and DIP, the sequential of the every other waveform shown in Fig. 2 is by CLK and bCLK control.CLK and bCLK preferably swing between 0.6V and 1.3V.Curve chart C) and D) represent voltage and the Vc and the Vcom at internal node X and Y place respectively.At curve chart E) in, DON and DOP represent the differential output of sample latch 110.
The cycle of the differential clock curve chart B) is divided into pre-charging stage P1, P2 and P3 and read stage S0, S1 and S2.In pre-charging stage, CLK moves towards low level and bCLK moves towards high-order, and this activates precharge device p3 again, p4, and p5, p6 and p7, internal node X and Y begin to rise from their low level at that time.At the pilot process of pre-charging stage, all devices comprise that optional equalizing device p7 is in activating the most fully of they, make nodes X and Y rise substantially, and owing to the operation of optional equalizing device p7 shows subequal voltage.Therefore, for example in the centre of pre-charging stage P1, the low level that internal node X and Y have left them rises to the only about half of of their end values.
Differential input DIN and DIP are arranged sequential, make them arrive their peak value before precharge cycle finishes.Though differential input DIN and DIP are when they show the voltage difference (representing the differential peak to peak signal difference of 0.9V) of about 0.45V when maintenance is identical on polarity from the one-period to the next cycle, but because intersymbol interference (ISI), the voltage difference between DIN and the DIP when their inverted status (change polarity) especially when the state back of reversing be that second time in the next cycle is much smaller when state reverses.This is Fig. 2 curve chart A) shown in the situation at the time t0 place.At that time, the peak to peak signal difference between DIN and the DIP is reduced to small-signal, it be when DIN and DIP keep identical from the one-period to the next cycle existing peak to peak signal difference about 1/4th to half.
In a back semiosis of pre-charging stage, when its low level was left in the CLK rising, early stage differential input DIN and the arrival of DIP began the voltage difference with internal node X and Y place.And these node voltages began CMOS inverter with sample latch 110 to n1 when CLK arrives its peak value before pre-charging stage finishes, and p1 and n2, p2 are driven into their end value.Therefore, in the back semiosis of pre-charging stage P1, by the DIN of the state change of demonstration from the low level to a high position, and show the DIP that opposite state changes, device n3 is than device n4 conducting more completely, and the latter begins to turn-off.As a result, nodes X and Y begin difference, and Y becomes higher than X.
Simultaneously, in pre-charging stage, the high-end trim conduction device n6 of bCLK, this causes the node potential at Vcom place to rise, and by the and then rising of voltage Vcom of device n5 (showing as resistive element at that time), Vc also rises.As shown in pre-charging stage P1, the increase of the Vc of time t0 place raise at that time two nodes X and the voltage at Y place, this allows their difference.Then, when Vc and Vcom decline and the more complete conducting of n5, the voltage on these nodes begins to descend once more.By rising to 1.0V at the time CLK of time t1 place, thereby indicate the beginning in the stage of reading, nodes X and Y show basic voltage difference (Δ V1).Rely on the early signal difference at nodes X and Y place, before pre-charging stage P1 finished, output signal DON had begun to leave its low level to the high-order transformation of its end value, and output signal DOP has begun to leave its high position to its end value low level transformation.In case these signals have been finished transformation, sample latch 110 is preserved these output by reading stage S1 so.
In the process of subsequently pre-charging stage P2, process repeats once more, except current differential input DIN and DIP remain on equal state (identical polar) from the one-period to the next cycle.Therefore, unconverted input DIN and DIP allow active entering apparatus n3 and n4 longer time ground difference node voltage, the more difference thereby the voltage at nodes X and Y place becomes.Again, the voltage Vc that raises of pre-charging stage helps they difference to peaking and when beginning to descend once more when the voltage at nodes X and Y place.Specifically, (time t2) nodes X has high voltage when CLK leaves pre-charging stage, because the higher DIP signal at device n4 place.As a result, nodes X and Y are in time t2 place voltage difference (Δ V2).This causes exporting DON again and DOP began to change between state before pre-charging stage P2 finishes.Therefore, before the centre of reading stage S2, output DON and DOP are by fully differential.
In the mode of front, the sense amplifier 110 with the input of low-swing differential clock and pair of differential input DIN and DIP can produce the output DON and the DOP of fully differential.In addition, differential input needs not be rail-to-rail, and also can be non return to zero, as employed in the preferred embodiment described herein.The voltage of pre-charge circuit 120 raises those operations of the charging permission sense amplifier 120 of operation and internal node X and Y in the early part of pre-charging stage.
Fig. 3 A and 3B also schematically illustrate second system implementation plan of the present invention with the block diagram form respectively.As illustrated among Fig. 3 A, in this embodiment, a pair of sample latch 310 and 311 is configured to shared pre-charge circuit 320 makes power and chip area to save.The first sample latch 310 CLK signal sampling, and second sample latch, 311 usefulness complementary clock bCLK sampling.
As further specifying among Fig. 3 B, sample latch 310 and 311 each comprise the CMOS inverter of pair of cross coupling.Each sample latch 310,311 are connected to identical pre-charge circuit 320, pre-charge circuit 320 has transistor n36, and the grid that transistor n36 preferably is configured to be used for diode operation is connected to the NFET of source electrode, and this NFET is connected to voltage by resistive element r31 and supplies with Vdd.Two sample latch 310 and 311 are located to be connected to jointly transistor n36 and are connected to bias device n37 in common potential (VCOM).Bias device preferably its source electrode is connected to the n type field-effect transistor (NFET) that common potential Vcom and its drain electrode connects ground.The grid of bias device n37 is connected to constant bias (CBIAS).
The operation of two sample latch of acceptor unit is as follows: when first sample latch 310 is in CLK for high-order when reading the stage, replaced C LK and second sample latch 311 that receives complementary clock bCLK is in pre-charging stage is because bCLK is low level at that time.It is resistive that low level bCLK input has more device n52 at that time, makes the voltage Vc2 of sample latch 311 rise.This helps to raise the nodes X 2 of sample latch 311 and the voltage at Y2 place again, so they are by precharge, and then in a back semiosis of pre-charging stage according to the value of differential input DIN2 that is provided to the there and DIP2 and difference.
Simultaneously, when taking place in top-operation is being in the sample latch 311 of pre-charging stage, sample latch 310 is in the stage of reading.At that time, bias device n37 does not raise the voltage level of Vc1 in the sample latch 310, because device n51 conducting at that time, makes the voltage at Vc1 place near the voltage that equals the Vcom place.At that time, read operation is finished in sample latch 310, and data are exported DON1 and their end value of DOP1 arrival and the preservation pre-charging stage up to next cycle.Thereafter, sample latch 310 enters the pre-charging stage of next cycle, and sample latch 311 is carried out and read and preserve its output DON2 and the DOP2 pre-charging stage up to its next cycle at that time.With second embodiment of the present invention (Fig. 3 A-3B) and first embodiment (Figure 1A-1B) compare, be understood that power and chip area are saved in second embodiment, because two sample latch 310 and 311 are just shared pre-charge circuits 320, rather than each sample latch all have its oneself have and the device of pre-charge circuit 320 same number and the pre-charge circuit 120 of configuration.
Fig. 4 A is the block diagram of explanation the 3rd embodiment of the present invention.In this embodiment, the differential data of a pair of introducing input DIN_N and DIN_P are by six sample latch 410,411,510,511, and 610 and 611 configuration is sampled.Sample latch is configured to according to six clock signal clks 0 to CLK5 and samples and preserve data, and all six clock signals obtain from common clock CLKA by clock generator circuit 450.These clock signals all are to have the non-return-to-zero signal that has reduced signal swing, as top about Figure 1A, 1B and 2 described, and to be configured to sampling preferably also be non return to zero and have the differential data input that has reduced signal swing.Be understood that, six sample latch 410 to 611 are configured to multichannel and decompose the data that arrive on differential input DIN and DIP, and each sample latch produces the DON0 and the DOP0 of for example corresponding sample latch 410 of output with the speed of the sixth of the data transaction speed of DIN and DIP.The output of each sample latch for example the DON0 of sample latch 410 and DOP0 by master-slave flip-flop for example FFO further be latched as rail-to-rail signal, and offer then buffer for example BUF0 with data output signal for example DOUT_0 be driven into its destination.
In this embodiment, be similar to embodiment illustrated among Fig. 3 A and the 3B, every pair of sample latch is shared common precharge circuit.For example, as illustrative among Fig. 4 B, a pair of sample latch 410,411 is shared pre-charge circuit 420.Each sample latch 410,411 shows to differential input DIN and being interconnected among Fig. 4 B of DIP and differential clock signal CLK0 and CLK3.
Refer again to Fig. 4 A, the current offset distributed circuit 430 that preferably includes band-gap reference, bias generator and current mirror device is connected to each of sample latch 410 to 611 employed pre-charge circuits 420,520 and 620.So employed this circuit 430 of whole six sample latch replaces device n37 (Fig. 3 A).In this case, be connected to every pair of sample latch for example 410,411 pre-charge circuit 426a have structure as shown in Fig. 4 C.
The waveform of clock signal clk 0 to CLK5 illustrates in Fig. 5.All clock signals have reduced between the low of the amplitude of oscillation and high level L and the H swing and have had identical period T identical.As from Fig. 5 apparently, signal CLK0 and CLK3 are complementary; CLK1 and CLK4, and CLK2 and CLK5 also are complementary.Each clock signal clk 0 to CLK5 departs from each other clock signal, the sixth of apart period T on the phase place.To be similar to the mode shown in Fig. 4 B, clock is input to sample latch to 510,511 to CLK1 and CLK4, and clock is input to sample latch to 610,611 to CLK2 and CLK5.
Refer again to Fig. 4 A, the operation of system is described.Pair of differential data-signal DIN_N that arrives from transmission line and DIN_P amplify and offer six sample latch 410 to 611 by analog preamplifier 460 each.Each of six sample latch 410 to 611 is then according to the phase place (for example CLK0 etc.) of the clock that is provided to there sampled data from differential input DIN and DINP successively, and will sample and export for example DON0, DOP0 is provided to the trigger FF0 for example that connects the there, then by buffer for example BUF0 be driven on transmission line as signal DOUT0 for example.For example, sample latch 410 is read the input data on DIN and the DIP and is preserved valid data at stage S0, and sample latch 510 is made same thing at stage S1, and sample latch 610 is made same thing at stage S2.Thereafter, sample latch 411 is read the input data on DIN and the DIP and is preserved valid data at stage S3, and sample latch 511 is made same thing at stage S4, and sample latch 611 is made identical thing at stage S5.Should be understood that DOL Data Output Line DOUT_0 to DOUT_5 drives by the identical order of the sample latch that is connected with them.
From the description of the preferred embodiment of front, the invention provides a kind of system and method apparently with the clock sampling data-signal that reduced signal swing.The present invention is applicable to and receives that high-speed data reduces simultaneously because the caused system noise of clock jitter, thereby but cause the conversion speed of the increase of the signal noise tolerance limit received signal improved, and potential low-power consumption.
Though the present invention here describes according to its some preferred embodiment, those skilled in the art only should expect not deviating from many modifications of being undertaken by the following additional true scope of the present invention that claim limited and essence easily and enrich.
Industrial usability
The present invention is applicable to the method and system of digital communication.
Claims (18)
1. in integrated circuit, a kind of method with the clock sampling pair of differential input signals that reduced the amplitude of oscillation comprises:
In pre-charging stage when described clock is low level, based on the value of pair of differential input signals with a pair of voltages at nodes difference;
Described differential voltage makes at least one regenerated data signal output begin to change in described pre-charging stage in response to the change of described pair of differential input signals.
2. according to the process of claim 1 wherein that described differential input signal has the signal swing that has reduced.
3. according to the method for claim 2, wherein said differential input signal is non-return-to-zero (NRZ) type.
4. according to the process of claim 1 wherein that the described clock that has reduced the amplitude of oscillation is non-return-to-zero (NRZ) type.
5. according to the method for claim 3, also comprise:
Described pair of differential input signals is applied to the corresponding input of a pair of active entering apparatus;
Wherein, in described a pair of node place difference, described a pair of active device is by described differential input signal control at a pair of active entering apparatus of the described voltage of described pre-charging stage by being connected to described a pair of node.
6. according to the method for claim 5, wherein said active entering apparatus links together to weaken big electric current from one of described node in described pre-charging stage based on the value of described differential input signal.
7. according to the method for claim 6, wherein said active entering apparatus all is connected to first electromotive force, and described first electromotive force rises in described first pre-charging stage, thus the described voltage on the described node that raises.
8. according to the method for claim 7, wherein said first electromotive force is connected to common node potential by device, and described common node potential raises in described pre-charging stage again.
9. according to the process of claim 1 wherein that described regenerated data signal is output as pair of differential output.
10. according to the method for claim 9, wherein said differential output is rail-to-rail signal.
11., also be included in the electric current of described pre-charging stage increase from described common node potential to ground according to the method for claim 1.
12. any one method according to claim 1-11, wherein said pair of differential input signals is sampled in first sample latch of receiver, described method also is included in the same period of the described clock that described pair of differential input signals is sampled second pair of differential input signal of sampling in second sample latch of described receiver, comprising:
To have reduced the amplitude of oscillation and be applied for the clock input of described second sample latch with the described second pair of differential input signal of sampling with the complementary clock of described clock complementation;
In pre-charging stage when described complementary clock is low level, based on the value of described second pair of differential input signal, with the second voltage difference at a pair of Section Point place of described second sample latch;
The change that second voltage of described difference is exported in response to described second pair of differential input signal at least one second regenerated data signal of described second sample latch begins to change in described pre-charging stage.
13. according to any one method of claim 1-11, be used for the clock that has reduced the amplitude of oscillation data on the pair of differential input signals being carried out the multichannel decomposition, comprise to have reduced speed:
Each cycle for common clock produces skew, the clock that reduced buty cycle, that reduced the amplitude of oscillation of " n " individual clock phase;
Each of described " n " individual described clock that has reduced the amplitude of oscillation is applied for the corresponding clock input of the respective sample latch of " n " individual sample latch;
In pre-charging stage when described corresponding clock is input as low level, based on the value of described pair of differential input signals a pair of voltages at nodes difference with described respective sample latch;
The change that the voltage of described difference is exported in response to described pair of differential input signals at least one regenerated data signal of described respective sample latch begins to change in described pre-charging stage.
14. a system has at least one sample latch according to any one method sampling pair of differential input signals of claim 1 to 13.
15. any one system according to right 1 to 13 comprises transistor, it is connected with in response to described clock input, controls described first electromotive force of described at least one sample latch and the electric current between the described common node potential.
16. according to the system of claim 15, also comprise transistor, it is connected to control the electric current between described common node potential and the ground.
17. according to the system of claim 15, wherein each described sample latch also comprises a pair of precharge device, it is connected with the electric current between the described node of control voltage source and each described sample latch.
18. according to the system of claim 17, also comprise equalizing device, it is connected to control the electric current between the described node.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US2003/003177 WO2004070968A1 (en) | 2003-01-31 | 2003-01-31 | Receiver system and method for reduced swing differential clock |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1714517A true CN1714517A (en) | 2005-12-28 |
Family
ID=32848672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN03825622.3A Pending CN1714517A (en) | 2003-01-31 | 2003-01-31 | Receiver system and method for reduced swing differential clock |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP1588500A1 (en) |
| CN (1) | CN1714517A (en) |
| AU (1) | AU2003214978A1 (en) |
| WO (1) | WO2004070968A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102075174A (en) * | 2009-11-24 | 2011-05-25 | 海力士半导体有限公司 | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5640115A (en) * | 1995-12-01 | 1997-06-17 | Sun Microsystems, Inc. | Self-enabling latch |
| GB9707349D0 (en) * | 1997-04-11 | 1997-05-28 | Univ Waterloo | A dynamic current mode logic family |
-
2003
- 2003-01-31 EP EP03710827A patent/EP1588500A1/en not_active Withdrawn
- 2003-01-31 WO PCT/US2003/003177 patent/WO2004070968A1/en not_active Application Discontinuation
- 2003-01-31 AU AU2003214978A patent/AU2003214978A1/en not_active Abandoned
- 2003-01-31 CN CN03825622.3A patent/CN1714517A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102075174A (en) * | 2009-11-24 | 2011-05-25 | 海力士半导体有限公司 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| AU2003214978A1 (en) | 2004-08-30 |
| EP1588500A1 (en) | 2005-10-26 |
| WO2004070968A1 (en) | 2004-08-19 |
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