EP1588418A1

EP1588418A1 - Soi structure comprising substrate contacts on both sides of the box, and method for the production of such a structure

Info

Publication number: EP1588418A1
Application number: EP04706606A
Authority: EP
Inventors: Steffen Richter; Dirk Nuernbergk; Wolfgang Goettlich
Original assignee: X Fab Semiconductor Foundries GmbH
Current assignee: X Fab Semiconductor Foundries GmbH
Priority date: 2003-01-30
Filing date: 2004-01-30
Publication date: 2005-10-26
Also published as: US7195961B2; AU2004208199A1; US20060154430A1; WO2004068579A1

Abstract

Disclosed are an arrangement and a production method for electrically connecting (20) active semiconductor structures (40) in the monocrystalline silicon layer (12) located on the front face of silicon-on-insulator semiconductor wafers (SOI; 10) to the substrate (13) located on the rear side and additional structures (13a) that are disposed therein. The electrical connection is made through the insulator layer (11).

Description

SOI structure with substrate contacts on both sides of the BOX and manufacturing process for such a structure

The invention relates to SOI structures (Silicon-on-Insulator), in which component structures in an upper

Semiconductor layer and in the semiconductor substrate are present, which are in electrical connections, which are guided through an insulator layer.

0 An SOI structure consists of a thin semiconductor layer, which is located on a thin oxide layer. The oxide layer is usually produced as a buried oxide (BOX) and in turn lies on a semiconductor layer, generally a silicon layer, namely the silicon substrate, which usually has a thickness of 300 μm to δOOμiri. This substrate is only used to handle the structure. The actual components and functions are implemented as in normal CMOS processes on homogeneous silicon wafers in the near-surface semiconductor layer 0.

An essential difference to the standard CMOS processes consists in SOI technology is that the structural elements by trenches which extend up to the insulating layer ₅ are dielectrically isolated from each other. This greatly reduces mutual electrical influence on the components. This dielectric insulation also makes SOI technology suitable for high-voltage applications.

0 There are advantages if the components are not coupled to one another via the substrate. This eliminates certain undesirable substrate effects, such as Latch-up, significant reverse currents at elevated temperatures, increased parasitic capacitances at the source / bulk or drain / bulk pn-S junctions.

The US-A 6,188,122 (Davari, IBM) shows an SOI structure with "Capacitor" in the substrate and an FET (active device) in the upper silicon layer, column 4, lines 40 ff. Conductive vias, column 5, lines 11 ff. reach through the oxide layer (there 30).

The object of the invention is to propose a method which enables improved substrate use to increase the packing density. Qualitative improvements in semiconductor circuits can be achieved. The invention is also intended to expand the integration possibilities of circuit arrangements on SOI semiconductor wafers to include components from others

Technologies such as To be able to integrate bipolar devices.

Solutions according to the invention are presented in claims 1 and 20. Further refinements of the invention are contained in the subclaims and subclaims. The arrangements produced are described in claims 8 and 27.

The inventive solutions assume that the substrate is also used for the expansion of circuits, i.e.

To generate doping regions in the substrate in order to be able to integrate additional and different types of components in SOI circuits. At the same time, the electrical connections to the substrate can suppress possible repercussions on the circuit structures in the thin upper silicon layer. Backside metallization of the substrate can be used for the purposes of including the substrate. On the other hand, the active components realized in the upper silicon layer are sensitive to an applied potential on the back. The disadvantage is that e.g. MOSFETs can be opened from the rear, at high rear voltages, or an on-resistance of high-voltage transistors depends on the rear voltage. Even simple diodes have a dependence of their breakdown voltage on the applied one

Substrate potential. These effects have to be taken into account when including the substrate, ie making electrical connections to the substrate. substrate terminals (Backside metallization) are originally not part of SOI technology. Corresponding housings do not provide a rear contact and often the number of pins on circuits is not sufficient to be able to contact the rear.

It has already been proposed (internally) to electrically connect the active structures of the upper silicon layer to the substrate without a rear-side metallization of the substrate by means of a metal bridge leading through the insulation layer, in a special case with a stack of metallization layers insulated from one another at the center, v-3g , the PCT application PCT / DE2004 / .... filed in parallel by the same applicants

In principle, this electrical connection makes it possible to use the substrate in the sense of a qualitative expansion of component arrangements.

The following examples serve to explain the invention in greater detail and are largely self-explanatory for the person skilled in the art with the reference numerals given.

Figure 1 shows schematically two different types of

Transistors 40, 50, which are produced on an SOI wafer 10 by means of SOI technology.

FIG. 2 shows schematically how p- and n-ion implantation and subsequent thermal treatment (the latter not shown) are used to produce p- and n-doped regions just below the boundary between insulation oxide 11 and substrate 13 in substrate 13 using a few process steps.

FIG. 3 shows in the simplest case schematically the implementation of a contact (as a path) from a doped zone 13a in the substrate through the insulation oxide 11 to the upper silicon layer 12 (the latter not shown), cf. but Figure 2.

Figure 3a to

FIG. 3 c shows designs of the aforementioned examples with the SOI wafer 10.

With the layers of certain dopings generated in the substrate 13 and their electrical connections 20 with the component structures on the upper side or the upper layer 12 of the SOI wafers 10, various active and passive structures can be created by desired or suitable combination.

Conductive (ohmic) contacts and Schottky contacts can be produced via the metal bridge 20 to the substrate 13. Diodes, MOSFETs, bipolar transistors, thyristors and IGBTs can be implemented as active structures. Capacities, resistances and shielding layers can be implemented as passive structures.

While capacitors and resistors use contacts, contacting shielding layers is not always absolutely necessary. Such areas are then floating freely (n.c). Shielding by means of substrate implantation achieves a desired reduction in the negative substrate influence (substrate bias) on structures in the upper active semiconductor layer 12. The shielding (not shown separately) realizes a decoupling of these active structures, for example 40 or 50, from effects which occur on the rear side R the SOI pane 10 can occur.

A multitude of new active and passive structures with improved properties is possible.

The SOI wafer structure illustrated in FIG. 1 with an insulator layer 11, a stronger substrate 13 and an active, thin layer 12 above the insulator 11 shows two different types of transistors 40, 50, an SOI MOSFET and an SOI power transistor , These are already at least partially integrated into the active silicon layer 12 and a trench 12a is provided between the transistors 40, 50, which interrupts the active silicon layer 12. Further

Interruptions are to the left and right of the two transistor types shown by way of example and these interruptions are referred to below as 12a, 12b, while the remainders of the active layer 12 are then structurally designated as 12 ', 12 "and 12"'.

The structure of the transistors is not described in any more detail; it is of a conventional design with a gate, drain and source and a bulk connection, which, however, is called a body here, since it does not affect the substrate but is arranged above the insulator layer 11. No openings are visible in FIG. 1, which break through the insulator layer and reach the substrate 13. These are illustrated in more detail in the following sections, in which structures of components in the substrate 13 are also shown, which have been omitted in FIG. 1 to illustrate the structure of transistors on an SOI wafer.

The reference symbols likewise run through the entire exemplary embodiments, so that they can be regarded as identical components without special mention.

Figure 2 illustrates the first process steps, here the radiation of ions by p-ion implantation and n-ion implantation. The p-type implantation 30 and the n-type implantation 31 are represented by vertical arrows. They reach through the active silicon as layer 12 from the front side V, through the buried oxide insulator 11, which represents the insulation layer of the SOI wafer, and into the substrate 13, to form symbolically represented doping regions 13 ', 13 ", as p-region (p-doping region) or as n-region 13 "

(n-doping region). In the following examples, these regions form component structures below the insulator layer 11 in the substrate.

A thermal treatment, not shown separately, activates the areas 13 ′, 13 ″ just below the boundary between the insulation layer (the BOX) and the rest of the substrate 13. The active structures, which have been symbolically represented with reference to FIGS. 1 and 2, are the first active structures for components 40, 50 above the insulator 11 and active structures 13 ', 13 "below this insulator, which are arranged as second structures for other components in the substrate. Electrical connections are made through the insulator layer, which are explained in more detail in the following examples.

In the simplest case, the embodiment according to FIG. 3 shows schematically the one produced by the filling 20 Breakthrough 19 in the insulator layer 11. The implementation of the contact of a doped zone 13a, produced according to FIG. 2, located in the substrate 13, through the insulation layer 11 as a BOX to the upper silicon layer 12, which is only shown schematically, is metallic or electrically conductive (ohmic contact ).

The first structures above the insulator layer 11, which are arranged in a thin layer 12 after it is thinner than the other layers 11, 13 used, arise e.g. 1 with the components visible there or other suitable components, depending on the application, bipolar transistors, tyristors, IGBTs or diodes. The breakthroughs are generated at locations where the active silicon layer 12 is no longer present. At locations where there is no active, single-crystalline layer 12, the fillings 20 of the openings 19 of the insulator layer 11 can be made with a metal. These regions are regarded as lateral insulation regions which lie between two active residual layers of the active silicon layer 12, for example the lateral insulation region 12a of FIG. 3b, between the residual layers 12 "and 12" ', or the lateral one

Isolation area 12c between the two remaining layers 12 "and 12 'according to FIG. 3a, or else the lateral isolation area 12b between the remaining layers 12' and 12" 'in the same figure.

The specific areas which receive an ion implantation are identified in FIG. 2 by 13 'and 13 "and are named accordingly in the remaining figures, so the layers 13a, 13a' and 13a".

The ion implantation 30, 31 with high-energy ions is carried out from the front, based on the specific areas which are provided on the basis of the topology to be achieved. The ion implantation takes place through the semiconductor layer 12 and the insulator layer 11 into the substrate 13, using templates and with different types of ions 30 or 31, depending on the component to be produced. The activation by temperature can optionally take place in several steps and at different temperatures, adapted to a respectively selected, implanted ion type in accordance with the aforementioned different ion implantations.

In the area of the active structures, metallization layers can be provided, which are shown in different variants in FIGS. 3a to 3c, applied to the SOI wafer structure described above. The ^• metallization layers can for example on the

Rear R can be arranged as shown as layer 14 in Figures 3b and 3c. The metallization layers can be insulated from one another. A filling is also regarded as metallization, which connects first structures on the top of the insulator layer with second structures under the insulator layer in the substrate 13 in an electrically conductive manner. In FIG. 3a, the metal filling 20 connects a doping region 13a ′ (in FIG. 3 13a) with a metallization layer 15 above the insulator, as shown in FIG. 3. This metallization layer is shaped as a bridge, so that it connects the electrically conductive filling 20 to a component on the top which is arranged in the remaining silicon layer 12 ″, for example according to FIG. 1.

The insulator layer 11 can be designed as a silicon oxide layer, which is also the case with most SOI wafers. The substrate 13 can consist of single-crystal silicon.

The various types of contact which result from the metal bridge (the filling 20) are outlined next to one another in FIG. 3a. Schottky contacts result in a metal filling 22 in an opening 21 if the upper side of the substrate 13 has no doping region. A Schottky contact with the substrate 13 is produced in the region of the opening. This Schottky contact 13c is shown on the right in FIG. 3a. A metal bridge is also shown above the filling 22 in the opening 21, mirror image of the metal bridge 15, here as a bridge 15 'for the electrically conductive one Connection to the active residual layer 12 ", to the right of the lateral isolation area 12c

A shielding layer 13a "is shown under the residual layer 12 'located between the lateral insulation regions 12b, 12c. It lies directly below the insulator layer 11 and is not electrically conductively contacted.

To the left of this, the previously described ohmic contact 13b between the metal filling 20 and the n- or p-doped region 13a 'is shown. Here, a diode structure is formed between the doping region and the substrate 13, in contrast to an ohmic contact (without directional dependence on the conductivity in the contact plane on the underside of the insulator layer BOX, denoted by 11).

The component produced using the described method lies on two levels, separated by the insulator layer 11. Above this layer are first structures, below this layer are second structures. Active components such as diodes can be provided in the substrate 13, cf. Figure 2 in the transition region between the doping region 13 'and 13 "and the substrate 13, or Figure 3 below the region 13a in the transition to the substrate 13, or MOSFETs, bipolar transistors, thyristors or IGBTs, in the manner of Figure 1, only within the Substrate 13.

The same components can be located above the insulator layer 11 in the active layer 12, or at least extend into them, in accordance with FIG. 1.

In addition, passive components can be arranged in the substrate 13 as second structures, such as capacitors, resistors or a shielding layer, as shown by 13a "in FIG. 3a.

A resistance is obtained, for example, by a doping region corresponding to that 13a 'of FIG. 3a when it comes to two of its ends with a metallic filling 20 in one respective opening 19 is contacted in the sense of the ohmic contact 13b.

FIG. 3b shows a continuous bridge 15 "with two arms, which bridge 15" conductively connects the two remaining layers 12 "and 12" ', at the same time making electrically conductive contact with the filling 20, which is arranged in the opening 19, in its central region. It forms an ohmic contact and a conductive path (vertical plug) through the insulator layer, to the doping region 13a. A metallic layer 14 is arranged on the rear side R on the opposite side.

The contacting described by the plugs 20 is provided for passive structures in substrate 13. Shielding layers, such as 13a "according to FIG. 3a, do not need such conductive connections to the top. They can remain isolated in the substrate. Such areas are then identified as floating freely (usually n.c. - not connected).

Shielding by means of substrate implantation 13a "can be achieved. This area shields electrically.

FIG. 3c shows a metallic shield 14 'above a filling 20 in an opening 19 which leads to a

Doping region 13a leads, as was illustrated in FIG. 3. In addition to the shielding, which is to be regarded as a metallization layer, a component 60 is shown schematically in section, which can correspond to that of FIG. 1, for example component 40. To the left of component 60, the trench can be seen in FIG. 3c, which also in FIG Figure 1 is clearly visible between two components above the insulator layer 11.

The embodiment according to FIG. 3c has two metallizations opposite, from the front V and the rear R, and semiconductor structures above the insulator layer 11 and in the substrate 13, below the insulator layer 11. Die Components 60, 50 or 40 are dielectrically separated or insulated from one another by trenches which extend as far as the insulation layer 11. As a result, the mutual electrical influence of components which are arranged on the same side is greatly reduced.

Such dielectric insulation makes SOI technology suitable for high-voltage applications. The components are not coupled to one another via the substrate; bulk connections are omitted, in favor of body connections for switchable components.

Nevertheless, the substrate is not ignored, but is used to expand the power circuits described, i.e. provided with doping areas in order to be able to integrate additional and different types of components.

The rear side metallization 14 of FIGS. 3b and 3c suppresses adverse effects on the circuit structures 40, 50 and 60 in and above the active silicon layer 12 or their residues, after their structuring into the sections which were previously identified by 12 ', 12 "and 12"' were designated.

, ? **

Claims

Claims:

1. Method for producing an integrated circuit on and in an SOI semiconductor wafer with front (V) and rear (R), first structures (40, 50, 60) of active components in an upper semiconductor layer (12) via electrical connections ( 20, 22), which are led through an insulator layer (11), are connected to second structures (13a, 13a ', 13c) of components in the substrate (13), with the following steps in certain areas (13', 13 ") Ion implantation (30, 31) with high-energy ions from the front side (V) through the semiconductor layer (12) and the insulator layer (11) into the substrate (13); a temperature treatment for activating the ions implanted in the substrate (13) takes place, adapted to the implanted ion type (30, 31); manufacture of the first structures (40, 50, 60) at least partially in the upper, single-crystal design

Layer (12);

Generation of at least one, preferably several openings (19, 21) in the insulator layer (11); Filling (20; 22) the at least one opening (19, 21) in the insulator layer with a (conductive) metal;

Production of metallization tracks (15, 15 ', 15 ") which are insulated from one another in the area of the active structures (40, 50, 60) and which cover the first structures of the upper side with the second structures in the substrate (13) via the metal fillings (20 ; 22) in the

Connect breakthroughs electrically.

2. The method according to claim 1, wherein the insulator layer (11) is a silicon oxide layer.

The method of claims 1 and 2, wherein only one insulator layer (11) is provided through which the metal filling extends. 3a. The method of claim 1, wherein the top layer (12) is thin opposite the substrate (13) of the SOI wafer (10).

3b. The method of claim 1, wherein the main operations are performed sequentially.

3c The method of claim 1, wherein using

Templates and with different types of ions (30, 31) are used to generate components under the insulator layer (11).

3d. The method of claim 1, wherein the activation of the implanted ions takes place in several steps of different temperature.

3e. The method of claim 1, wherein the breakthroughs occur at locations where there is no active, single-crystalline layer (12) (as lateral insulation areas).

3f. The method of claim 1, wherein the upper semiconductor layer (12) consists of silicon.

4. The method of claim 1 or 2, wherein the first structures (40) are at least partially produced in the upper silicon layer.

5. The method according to any one of the preceding claims, wherein the substrate (13) consists of single crystal silicon.

6. The method according to any one of the preceding claims, wherein with the process of producing the at least one filling

(Metal bridge) of the at least one opening (19, 21), an ohmic contact (13b) or a conductive path to the substrate is produced.

7. The method according to any one of claims 1 to 5, wherein with the process of producing the filling (metal bridge) of at least one opening (19, 21) is a Schottky contact (13c) with the substrate (13).

7a. The method of claim 1, wherein two first structures for two first components (40, 50) above the insulating layer

(11) are separated and isolated by at least one trench (12a, 12b, 12c) which extends to the insulating layer.

7b. The method of claim 1, wherein a rear side metallization (14) is applied to the rear side (R).

7c. The method of claim 1, wherein the metallic sheets (15, 15 ') are metallization layers.

7d. The method of claim 7c, wherein the webs as

Metal bridges are formed on at least two different levels above the insulator layer (11).

8. Component arrangement manufactured or producible with the method according to one of the preceding claims.

9. The component arrangement according to claim 8, wherein active components such as diodes, MOSFETs, bipolar transistors, thyristors and IGBTs are present individually or in combination in the substrate (13).

10. The component arrangement according to claim 8 or 9, wherein in

Substrate (13) (also) structures for passive components such as capacitors, resistors or a shielding layer (13a ") are present.

0. Method of making integrated circuits

SOI semiconductor wafers, in which the active component structures in the thin upper semiconductor layer are connected to component structures in the substrate via electrical connections which are guided through the insulator layer, characterized by the series of the main operations listed below which involve (known per se) Process steps are carried out:

In certain areas, ion implantation with high-energy ions from the front through the single-crystal semiconductor layer and the insulator layer into the substrate, optionally using templates and with different types of ions, as are customary for producing components. - Temperature treatment to activate the implanted ions, possibly in several steps of different temperatures, adapted to the implanted type of ions. Production of the component structures in the thin upper single-crystalline silicon layer. - Creation of the openings in the insulator layer at locations where there is no active thin single-crystalline silicon layer (lateral insulation regions).

Filling the openings in the insulator layer with a metal.

Production of metallization layers which are insulated from one another in the area of the active component structures and which electrically connect the structures of the top side to those of the substrate via the metal filling of the openings in the insulator layer.

21. The method of claim 20, wherein the insulator layer is a silicon oxide layer.

22. The method of claim 20, wherein each bridge is self-contained.

23. The method of claim 20, wherein a

Rear side metallization (14) is attached to the substrate (13).

24. The method according to any one of the preceding claims, wherein the substrate consists of a single-crystalline silicon wafer.

25. The method according to any one of the preceding claims, wherein the process of producing the metal bridge of the opening creates an ohmic contact with the substrate.

26. The method according to any one of claims 21 to 24, wherein a Schottky contact with the substrate is produced with the process of producing the metal bridge of the opening.

27. Component arrangement using the method according to one of claims 21 to 26.

28. The component arrangement according to claim 27, wherein active components such as diodes, MOSFETs, bipolar transistors, thyristors and IGBTs are present individually or in combination in the substrate.

29. The component arrangement according to claim 27 or 28, wherein in addition to active components, passive structures such as capacitors, resistors and shielding layers are also present in the substrate.