EP1579483A2 - System and method for expanding a pulse width - Google Patents

System and method for expanding a pulse width

Info

Publication number
EP1579483A2
EP1579483A2 EP03783154A EP03783154A EP1579483A2 EP 1579483 A2 EP1579483 A2 EP 1579483A2 EP 03783154 A EP03783154 A EP 03783154A EP 03783154 A EP03783154 A EP 03783154A EP 1579483 A2 EP1579483 A2 EP 1579483A2
Authority
EP
European Patent Office
Prior art keywords
signal
pulse width
pulse
capacitor
shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03783154A
Other languages
German (de)
French (fr)
Other versions
EP1579483A4 (en
Inventor
Severin Barth
Fabrice Picot
Philippe Coll
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of EP1579483A2 publication Critical patent/EP1579483A2/en
Publication of EP1579483A4 publication Critical patent/EP1579483A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Pulse Circuits (AREA)
  • Dram (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

A circuit (10) and method for expanding the pulse width of a signal (20) based on the input signal's (18) pulse width. A circuit (10) generates a delay equal to the pulse width of the input signal ((18) for both a SHIFT (52) and OUT (20) signal, which are out of phase with each other. The delay is generated when a capacitor (16) applies voltage to two control transistors in both the SHIFT (12) and OUT (14) blocks, reducing gate control in these transistors and generating a delay in the falling edge of these signals such that the pulse width of the SHIFT signal (52) is reduced and the pulse width of the OUT signal (20) is increased. The capacitor (16) is charged by a transistor (22) activated by the SHIFT signal (52). The pulse-doubling system is self-converging: when the SHIFT signal's (52) pulse width is zero, the OUT signal's (20) pulse width is doubled, and the capacitor's (16) charging level is fixed since it is no longer charged by the transistor (22) controlled by the SHIFT signal. The circuit (10) may be modified so that the output signal's (20) pulse width is a known factor of multiplication wider than the input signal's (18) pulse width.

Description

Description
SYSTEM AND METHOD FOR EXPANDING A PULSE WIDTH
FIELD OF THE INVENTION
This invention relates to a circuit for generating a delay in a periodic pulse such that the pulse width is expanded by a chosen factor of multiplication.
BACKGROUND ART
The components of semiconductor devices are controlled by various signals. The pulse width of these signals is often quite important for the proper operation of the components and the semiconductor device.
For instance, in asynchronous SRAM devices the Edge Transition Detection (ETD) signal is often used as the internal clock of the device, allowing the device to operate internally in a synchronous manner. If the pulse width of the ETD signal is too wide or too narrow, the memory device will not be able to function properly.
Address transition detection (ATD) circuits are used to detect a change in user-supply address bits in memory devices. The pulse from the ATD circuit is often used to precharge the data path to and from the memory address for the transfer of data. If the ATD signal pulse width is too narrow, the pulse is insufficient to precharge the data path.
It would be desirable to be able to modulate the pulse width of a signal so the signal could be used to accurately serve as a device's internal clock or detect an address transition and precharge a memory. Expanding a narrow pulse width would also be useful for measuring signals with narrow pulse widths. The prior art has addressed controlling pulse widths. For instance, U.S. Patent No. 5,995,444 to McClure discusses controlling the width of an ETD pulse of a memory device by varying the logic state of one or more control signals of the memory device. By changing the combination of logic states of the control signals, the pulse width of the ETD signal may be varied to produce an optimal ETD pulse width.
U.S. Patent No. 5,706,246 to Choi et al . dis- cusses producing an ATD signal of sufficient width to stably operate an internal circuit. An input signal is delayed until its pulse width is of sufficient duration to prevent malfunction of a memory device.
The prior art discussed here discusses expand- ing pulse widths by determining the desired pulse width and then varying the input signal to produce the desired pulse width. The output pulse width is not dependent on the input pulse width. The prior art discussed here does not provide a mechanism for multiplying the width of the input signal by a known factor.
It is an object of this invention to provide a method and system for expanding an input signal's pulse width by a known factor.
SUMMARY OF THE INVENTION
The object is achieved by a circuit which generates a delay equal to the pulse width of the input signal for both a SHIFT and OUT signal, which are out of phase with each other. The delay is generated when a capacitor applies voltage to two control transistors in both the SHIFT and OUT blocks, reducing gate control in these transistors and generating a delay in the falling edge of these signals such that the pulse width of the SHIFT signal is reduced and the pulse width of the OUT signal is increased. The capacitor is charged by a transistor activated by the SHIFT signal. The pulse-doubling system is self-converging: when the SHIFT signal's pulse width is zero, the OUT signal's pulse width is doubled, and the capacitor's charging level is fixed since it is no longer charged by the transistor controlled by the SHIFT signal . The circuit may be modified to provide greater pulse width expansion. This circuit may be employed in CMOS submicron technologies .
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a schematic diagram of a pulse width doubling system.
Fig. 2 is a time chart showing how the pulse widths of SHIFT and OUT signals are affected by the pulse width doubling system shown in Fig. 1.
Fig. 3 is a circuit diagram of the pulse width doubling system shown in Fig. 1.
Fig. 4 is a graph plotting the performance of the pulse width doubling system.
Fig. 5 is a schematic diagram of an expanded width generator multiplier chain.
BEST MODE FOR CARRYING OUT THE INVENTION In Fig. 1, one embodiment of a pulse width doubling system 10 contains two blocks or modules 12, 14. One block 12 is a shifting block producing a SHIFT signal 52, the other block 14 produces the OUT signal 20; the SHIFT 52 and OUT 20 signals are produced in response to an input signal 18, in this case a low state input pulse.
The input signal 18 passes through an inverting amplifier 24 before reaching the output block 14.
The SHIFT signal controls a transistor 22 that charges a capacitor 16. The capacitance value ranges from 2 to 5 pF and will vary with the technology used. The charge level of the capacitor (VCD) 16 is increased at each cycle until the SHIFT signal 52 has zero pulse width or the capacitor is discharged (both of these situations are discussed in further detail below) . At each cycle, the capacitor applies charge, Vcd, to each of the blocks 12, 14 through a gate 26, generating a delay in the falling edge of the input signal 18 to each block 12, 14. As Vcd increases, the falling edge of the SHIFT signal 52 is delayed more and more until the low state pulse on SHIFT disappears. When this occurs, the transistor 22 no longer loads the capacitor 16. In addition, when the SHIFT signal 52 has a pulse width of zero, a delay equal to the width of the input pulse 18 has been generated at both blocks 12, 14 and the width of the OUT pulse 20 is therefore doubled.
In Fig. 2, the input pulse 18, Vcd 54, SHIFT signal 52, and OUT signal 20 are shown over the course of several cycles. At cycle a, when low state input pulse 18 of width T 56 is received, Vcd 54 is increased. At cycle b, Vcd 54 continues to increase, SHIFT signal 52 shows a delay on its falling edge, and OUT signal 20 shows a similar delay on its falling edge. The delays on the SHIFT and OUT signals 52, 20 are due to Vcd 54 being applied to the blocks responsible for generating the signals 52, 20. As Vcd 54 is increased in cycle c, the delay t 58 in the falling edges of the SHIFT and OUT signals 52, 20 also continues to increase. This pattern is continued in cycle d; as the pulse width on the SHIFT signal 52 decreases, the pulse width of the OUT signal 20 increases. At cycle e, the SHIFT 52 pulse width is zero; therefore the transistor controlled by the SHIFT signal no longer loads the capacitor. A delay equal to the width of the input pulse 18 has been generated for both the SHIFT and OUT signals 52, 20. As shown at cycle f, when the delay generated for the SHIFT pulse 52 is sufficient to create zero pulse width, the delay generated for the OUT pulse 20 doubles the pulse width 60 of the OUT signal .
With respect to Fig. 3, the SHIFT block 12 in this embodiment of a pulse width doubling system contains a control transistor 36, an inverter p-channel transistor 38, and an inverter n-channel transistor 40. The signal produced by these transistors 36, 38, 40 passes through an inverting amplifier 42. The output block 14 also has a control transistor 44, an inverter p-channel transistor 46, and an n-channel transistor 48. The signal from these transistors 44, 46, 48 passes through an inverting amplifier 50. The transistors 36, 44 in each block 12, 14 which are charged by the capacitor 16 should be the same size in order to generate the same delay at each cycle .
As noted above, the SHIFT signal 52 produced by the SHIFT block 12 activates a transistor 22 (in one embodiment, a PMOS transistor) that charges the capacitor 16. Voltage from the capacitor 16, Vcd 54, is applied to the SHIFT and output blocks' 12, 14 control transistors 36, 44 at gates 30, 28. The applied voltage activates the blocks' 12, 14 control transistors 36, 44. This affects the signal processing carried out by each block's 12, 14 inverter transistors 38, 40, 46, 48, causing a delay to be added to the SHIFT or OUT pulse produced by each block 12 , 14. If the pulse width doubling system 10 receives a reset signal 32, the capacitor 16 is drained through transistor 34. After the capacitor 16 is drained, the system is reset because the capacitor 16 is no longer carrying sufficient charge to affect the SHIFT and OUT signals generated by the SHIFT and OUT blocks 12, 14. As described above, the capacitor's 16 charge is increased with each pulse of the SHIFT signal until the SHIFT signal's pulse width is zero. In Fig. 4, the OUT signal 20 produced by the pulse width doubling system is compared to a value 58 equal to two times the width of the input signal over a range of input signals from 100 ps to 60 ns . These results are from a HSPICE simulation of the pulse width doubling system in a 0.25 μm process. The pulse width doubling system shows an error of less than 1% for pulses less than 40 ns and an error of 4% for pulses exceeding 40 ns.
The pulse width doubling system, or circuit, described above can be used for 2N pulse width multiplication, which would allow the direct observation of the crosstalk-induced signal at the output pad. In order to achieve 2N pulse width multiplication, 2N capacitance must be provided. As shown in Fig. 5, the circuit 50 could be modified somewhat by providing a cascade of several delay blocks 62 (half double-width generators which add a delay equal to the width 56 of the input signal T) along with the delay blocks (the SHIFT block 12 and the OUT block 14) from double width generator described above in Figs. 1 and 3. Only one capacitor 16 is necessary in this configuration. This modified circuit produces NT pulse width multiplication, where N is the number of blocks employed and T is the pulse duration. Three delay blocks 62 are used in addition to the SHIFT 12 and OUT 14 blocks, for a total of five blocks in the system; therefore, the pulse width 60 is quintupled. Any other number of delay blocks may be used in other embodiments to expand a pulse width the desired amount.

Claims

Claims
1. A circuit for extending a pulse width comprising: a) a first means for generating a pulse-type shift signal in response to an input signal; b) a second means for generating a pulse-type output signal in response to the input signal; and c) a capacitor charged by a transistor activated by the shift signal, the capacitor in electrical connection with the first means and the second means and applying charge at each cycle to the first and second means, the applied charge generating a first delay in a falling pulse edge of the shift signal and a second delay in a falling edge of the output signal such that the output signal's pulse width is expanded while the shift signal's pulse width is decreased.
2. The circuit of claim 1 further comprising a reset means in electrical connection with the capacitor, wherein the reset means discharges the capacitor when the circuit receives a reset signal .
3. The circuit of claim 1 wherein the transistor is a PMOS transistor.
4. The circuit of claim 1 wherein the output signal's pulse width is doubled when the shift signal's pulse width is zero.
5. The circuit of claim 1 further comprising at least one additional delay block in electrical connection with the capacitor, wherein the output signal's pulse width is increased for every additional delay block.
6. The circuit of claim 5 wherein the at least one additional delay block is a half double-width generator having means for adding a delay to the output signal equal to the width of the input signal .'
7. A method of extending a periodic pulse comprising: a) receiving a low state input pulse at a shift signal block generating a shift signal and an output block generating an output signal; b) charging a capacitor with a transistor activated by the shift signal; c) applying charge from the capacitor to both the shift signal block and the output block, wherein a delay in a falling edge of the shift signal and output signal is generated; and d) repeating steps a - c at each cycle, wherein the capacitor is no longer charged when there is no pulse on the shift signal.
8. The method of claim 7 further comprising discharging the capacitor when a reset signal is received.
9. The method of claim 7 wherein a generated delay in the shift signal equal to the initial width of the input pulse results in a zero pulse width of the shift signal .
10. The method of claim 7 wherein the output pulse is doubled when there is no pulse on the shift signal.
11. The method of claim 7 further comprising applying charge from the capacitor to at least one additional delay block, wherein the output signal is expanded for each additional delay block receiving charge from the capacitor.
EP03783154A 2002-12-02 2003-11-04 System and method for expanding a pulse width Withdrawn EP1579483A4 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0215156A FR2848037B1 (en) 2002-12-02 2002-12-02 SYSTEM AND METHOD FOR HEARING A PULSE WIDTH
FR0215156 2002-12-02
PCT/US2003/035203 WO2004051704A2 (en) 2002-12-02 2003-11-04 System and method for expanding a pulse width

Publications (2)

Publication Number Publication Date
EP1579483A2 true EP1579483A2 (en) 2005-09-28
EP1579483A4 EP1579483A4 (en) 2008-10-29

Family

ID=32309918

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03783154A Withdrawn EP1579483A4 (en) 2002-12-02 2003-11-04 System and method for expanding a pulse width

Country Status (11)

Country Link
US (1) US6753713B1 (en)
EP (1) EP1579483A4 (en)
JP (1) JP2006520113A (en)
KR (1) KR20050085303A (en)
CN (1) CN101061549A (en)
AU (1) AU2003291225A1 (en)
CA (1) CA2507693A1 (en)
FR (1) FR2848037B1 (en)
NO (1) NO20053191D0 (en)
TW (1) TW200414225A (en)
WO (1) WO2004051704A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI333332B (en) * 2007-03-13 2010-11-11 Novatek Microelectronics Corp Pulse extension circuits for extending pulse signals
JP6409864B2 (en) 2014-03-20 2018-10-24 日本電気株式会社 Termination device, termination control method, and storage medium storing termination control program
CN103929155B (en) * 2014-04-30 2017-01-11 广州视源电子科技股份有限公司 Pulse width broadening circuit
CN107272485A (en) * 2017-06-16 2017-10-20 中国科学院苏州生物医学工程技术研究所 A kind of pulse signal acquisition device and method based on low speed ADC
KR102636148B1 (en) * 2017-11-21 2024-02-14 삼성전자주식회사 Operation method of signal receiver, pulse width controller, and electric device including the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177019A (en) * 1985-01-31 1986-08-08 Matsushita Electric Ind Co Ltd Pulse stretch circuit
US5706246A (en) * 1996-03-11 1998-01-06 Lg Semicon Co., Ltd. Address transition detection circuit
US5793699A (en) * 1997-03-04 1998-08-11 Sgs-Thomson Microelectronics S.R.L. Circuit for the generation and reset of timing signal used for reading a memory device
US5995444A (en) * 1997-12-30 1999-11-30 Stmicroelectronics, Inc. Edge transition detection control of a memory device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3426608B2 (en) * 1990-04-04 2003-07-14 ユニシス コーポレイシヨン Clock deskew circuit
US5856753A (en) * 1996-03-29 1999-01-05 Cypress Semiconductor Corp. Output circuit for 3V/5V clock chip duty cycle adjustments
US6346841B2 (en) * 1998-06-29 2002-02-12 Hyundai Electronics Industries Co., Ltd. Pulse generator
JP2001101870A (en) * 1999-09-30 2001-04-13 Fujitsu Ltd Semiconductor integrated circuit
KR100434201B1 (en) * 2001-06-15 2004-06-04 동부전자 주식회사 Semiconductor package and fabrication method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177019A (en) * 1985-01-31 1986-08-08 Matsushita Electric Ind Co Ltd Pulse stretch circuit
US5706246A (en) * 1996-03-11 1998-01-06 Lg Semicon Co., Ltd. Address transition detection circuit
US5793699A (en) * 1997-03-04 1998-08-11 Sgs-Thomson Microelectronics S.R.L. Circuit for the generation and reset of timing signal used for reading a memory device
US5995444A (en) * 1997-12-30 1999-11-30 Stmicroelectronics, Inc. Edge transition detection control of a memory device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 0103, no. 86 (E-467), 24 December 1986 (1986-12-24) & JP 61 177019 A (MATSUSHITA ELECTRIC IND CO LTD), 8 August 1986 (1986-08-08) *
See also references of WO2004051704A2 *

Also Published As

Publication number Publication date
KR20050085303A (en) 2005-08-29
CA2507693A1 (en) 2004-06-17
CN101061549A (en) 2007-10-24
WO2004051704A2 (en) 2004-06-17
FR2848037A1 (en) 2004-06-04
NO20053191L (en) 2005-06-30
TW200414225A (en) 2004-08-01
US6753713B1 (en) 2004-06-22
EP1579483A4 (en) 2008-10-29
AU2003291225A1 (en) 2004-06-23
NO20053191D0 (en) 2005-06-30
JP2006520113A (en) 2006-08-31
AU2003291225A8 (en) 2004-06-23
WO2004051704A3 (en) 2007-01-18
FR2848037B1 (en) 2005-01-14
US20040104752A1 (en) 2004-06-03

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