EP1573605A4 - Method, system, and article of manufacture for implementing metal-fill - Google Patents

Method, system, and article of manufacture for implementing metal-fill

Info

Publication number
EP1573605A4
EP1573605A4 EP03786859A EP03786859A EP1573605A4 EP 1573605 A4 EP1573605 A4 EP 1573605A4 EP 03786859 A EP03786859 A EP 03786859A EP 03786859 A EP03786859 A EP 03786859A EP 1573605 A4 EP1573605 A4 EP 1573605A4
Authority
EP
European Patent Office
Prior art keywords
fill
article
manufacture
implementing metal
implementing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03786859A
Other languages
German (de)
French (fr)
Other versions
EP1573605A2 (en
Inventor
Thanh Vuong
William H Kao
David C Noice
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/300,715 external-priority patent/US7328419B2/en
Priority claimed from US10/300,722 external-priority patent/US7287324B2/en
Priority claimed from US10/300,724 external-priority patent/US20040098688A1/en
Priority claimed from US10/300,544 external-priority patent/US7231624B2/en
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Publication of EP1573605A2 publication Critical patent/EP1573605A2/en
Publication of EP1573605A4 publication Critical patent/EP1573605A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
EP03786859A 2002-11-19 2003-11-19 Method, system, and article of manufacture for implementing metal-fill Withdrawn EP1573605A4 (en)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US10/300,715 US7328419B2 (en) 2002-11-19 2002-11-19 Place and route tool that incorporates a metal-fill mechanism
US300722 2002-11-19
US300544 2002-11-19
US10/300,722 US7287324B2 (en) 2002-11-19 2002-11-19 Method, system, and article of manufacture for implementing metal-fill on an integrated circuit
US10/300,724 US20040098688A1 (en) 2002-11-19 2002-11-19 Method, system, and article of manufacture for implementing long wire metal-fill
US300715 2002-11-19
US300724 2002-11-19
US10/300,544 US7231624B2 (en) 2002-11-19 2002-11-19 Method, system, and article of manufacture for implementing metal-fill with power or ground connection
PCT/US2003/036989 WO2004047001A2 (en) 2002-11-19 2003-11-19 Method, system, and article of manufacture for implementing metal-fill

Publications (2)

Publication Number Publication Date
EP1573605A2 EP1573605A2 (en) 2005-09-14
EP1573605A4 true EP1573605A4 (en) 2006-08-16

Family

ID=32330032

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03786859A Withdrawn EP1573605A4 (en) 2002-11-19 2003-11-19 Method, system, and article of manufacture for implementing metal-fill

Country Status (4)

Country Link
EP (1) EP1573605A4 (en)
AU (1) AU2003295659A1 (en)
TW (1) TWI354901B (en)
WO (1) WO2004047001A2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5763955A (en) * 1996-07-01 1998-06-09 Vlsi Technology, Inc. Patterned filled layers for integrated circuit manufacturing
US5923563A (en) * 1996-12-20 1999-07-13 International Business Machines Corporation Variable density fill shape generation
US6093631A (en) * 1998-01-15 2000-07-25 International Business Machines Corporation Dummy patterns for aluminum chemical polishing (CMP)
US6305000B1 (en) * 1999-06-15 2001-10-16 International Business Machines Corporation Placement of conductive stripes in electronic circuits to satisfy metal density requirements
US20020199162A1 (en) * 2001-06-22 2002-12-26 Bae Systems Method for providing a fill pattern for an integrated circuit design

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5892249A (en) * 1996-02-23 1999-04-06 National Semiconductor Corporation Integrated circuit having reprogramming cell
US6189133B1 (en) * 1998-05-14 2001-02-13 International Business Machines Corporation Coupling noise reduction technique using reset timing

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5763955A (en) * 1996-07-01 1998-06-09 Vlsi Technology, Inc. Patterned filled layers for integrated circuit manufacturing
US5923563A (en) * 1996-12-20 1999-07-13 International Business Machines Corporation Variable density fill shape generation
US6093631A (en) * 1998-01-15 2000-07-25 International Business Machines Corporation Dummy patterns for aluminum chemical polishing (CMP)
US6305000B1 (en) * 1999-06-15 2001-10-16 International Business Machines Corporation Placement of conductive stripes in electronic circuits to satisfy metal density requirements
US20020199162A1 (en) * 2001-06-22 2002-12-26 Bae Systems Method for providing a fill pattern for an integrated circuit design

Non-Patent Citations (9)

* Cited by examiner, † Cited by third party
Title
KAHNG A B ET AL: "FILLING ALGORITHMS AND ANALYSES FOR LAYOUT DENSITY CONTROL", IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 18, no. 4, April 1999 (1999-04-01), pages 445 - 462, XP002370281, ISSN: 0278-0070 *
KAHNG A B ET AL: "Filling and slotting: analysis and algorithms", 1998, ISPD-98. 1998 INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN ACM NEW YORK, NY, USA, pages 1 - 8, XP002385851, Retrieved from the Internet <URL:http://vlsicad.ucsd.edu/Publications/Conferences/c75.pdf> [retrieved on 20060619] *
KAHNG ANDREW B: "IC layout and manufacturability: Critical links and design flow implications", 1999, pages 1 - 7, XP002385852, Retrieved from the Internet <URL:http://ieeexplore.ieee.org/iel4/6007/16057/00745132.pdf?isnumber=&arnumber=745132> [retrieved on 20060619] *
NELSON M ET AL: "Optimizing pattern fill for planarity and parasitic capacitance", ADVANCED SEMICONDUCTOR MANUFACTURING, 2004. ASMC '04. IEEE CONFERENCE AND WORKSHOP BOSTON, MA, USA 4-6 MAY 2004, PISCATAWAY, NJ, USA,IEEE, US, 4 May 2004 (2004-05-04), pages 115 - 118, XP010768975, ISBN: 0-7803-8312-5 *
RANDAL E BRYANT ET AL: "Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI", PROCEEDINGS OF THE IEEE, IEEE. NEW YORK, US, vol. 89, no. 3, March 2001 (2001-03-01), pages 341 - 365, XP011044482, ISSN: 0018-9219 *
RUIQI TIAN ET AL: "Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability", IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS IEEE USA, vol. 20, no. 7, July 2001 (2001-07-01), pages 902 - 910, XP002370282, ISSN: 0278-0070 *
STINE B E ET AL: "THE PHYSICAL AND ELECTRICAL EFFECTS OF METAL-FILL PATTERNING PROCTICES FOR OXIDE CHEMICAL-MECHANICAL POLISHING PROCESSES", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE SERVICE CENTER, PISACATAWAY, NJ, US, vol. 45, no. 3, March 1998 (1998-03-01), pages 665 - 679, XP000738545, ISSN: 0018-9383 *
YU CHEN ET AL: "Area fill synthesis for uniform layout density", IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 21, no. 10, August 2002 (2002-08-01), pages 1132 - 1147, XP002309863, ISSN: 0278-0070 *
YU CHEN ET AL: "Area Fill Synthesis for Uniform Layout Density", IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 21, no. 10, October 2002 (2002-10-01), pages 1132 - 1147, XP011070638, ISSN: 0278-0070 *

Also Published As

Publication number Publication date
AU2003295659A8 (en) 2004-06-15
AU2003295659A1 (en) 2004-06-15
WO2004047001A2 (en) 2004-06-03
TWI354901B (en) 2011-12-21
TW200417874A (en) 2004-09-16
EP1573605A2 (en) 2005-09-14
WO2004047001A3 (en) 2004-09-23

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Legal Events

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PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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Effective date: 20050617

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AX Request for extension of the european patent

Extension state: AL LT LV MK

DAX Request for extension of the european patent (deleted)
A4 Supplementary search report drawn up and despatched

Effective date: 20060717

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Effective date: 20080225

STAA Information on the status of an ep patent application or granted ep patent

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18D Application deemed to be withdrawn

Effective date: 20140603