EP1573507A2 - Dispositif de memorisation d une liste d elements et pr ocede de memorisation d un element dans un tel dispositif - Google Patents
Dispositif de memorisation d une liste d elements et pr ocede de memorisation d un element dans un tel dispositifInfo
- Publication number
- EP1573507A2 EP1573507A2 EP03780166A EP03780166A EP1573507A2 EP 1573507 A2 EP1573507 A2 EP 1573507A2 EP 03780166 A EP03780166 A EP 03780166A EP 03780166 A EP03780166 A EP 03780166A EP 1573507 A2 EP1573507 A2 EP 1573507A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- memory
- presented
- elements
- stored
- memorized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
- G06F21/80—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in storage media based on magnetic or optical technology, e.g. disks with sectors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/2101—Auditing as a secondary aspect
Definitions
- the present invention relates generally to the field of security in systems which require the storage of a secure history. It relates more particularly to a device for memorizing a list of elements and to a method for memorizing an element in such a device.
- a typical example concerns a recording device which is only authorized to make a single copy (or a limited number of copies) of each content which it is capable of recording. This is necessary with digital recording devices to avoid the proliferation of illegal copies while allowing copying for private use.
- An immediate solution to guarantee this consists in keeping in the recording device a list of all the contents (or more precisely a list of identifiers of all the contents) already recorded by it. Each time the recording device receives a command to record a particular content, it checks before this content is not present in the list of already recorded content. If the content (or more precisely its identifier) is present in the list, the recording device refuses to record it.
- FIFO type memory (acronym for "First In First Out” meaning “First Entered First Exit”) is usually used to store a list as above.
- the present invention aims to solve the aforementioned problems.
- This device relates to a device for memorizing a list of elements intended to memorize any element which was last presented to it.
- This device comprises a first memory and it further comprises according to the invention means responsible, when the first memory is full and a new element must be memorized, to randomly select an element memorized in the first memory to erase this selected element. and to memorize the new element presented.
- the device is capable of storing N elements, N being a natural integer, and it further comprises a second memory intended for permanently storing the M elements which were last presented to said device, M being a natural integer less than N, the first memory being intended to memorize the NM other elements.
- the device according to the invention even if it is presented with more than N elements to memorize, there is no way of knowing at the end which (s) element (s) is (are) no longer in the device .
- the device is further adapted to provide information indicating whether the element which was last presented to it is already present in the device. According to yet another characteristic, the device contains only a single copy of each memorized element.
- the device also stores, with each element, the number of times this element has been presented to it.
- the device is adapted to supply information indicating whether the element which was last presented to it has already been presented to it a number of times which exceeds a predetermined number.
- the invention also relates to a method for storing an element in a device as described above. It includes the steps of (a) receiving an item which is presented to the device; (b) check whether this element is already present in the device; and - in the event of a positive verification, designate the element as the element memorized last, and
- the oldest element stored in the second memory is transferred to the first memory; ii) the element received is stored in the second memory (2); and iii) if the first memory is full, then an element stored in the first memory is randomly selected to be deleted so that the oldest element stored in the second memory can be transferred to the first memory.
- the storage device of the invention is designed to contain a maximum of N elements, for example identifiers of content to be recorded.
- This device which bears the reference 5 in the single figure, is in particular integrated in a digital recording device.
- the device 5 comprises two memories A and B.
- Memory A always contains the M last elements which have been memorized in the device.
- Memory B contains elements which were memorized before the last M elements.
- element J is already present in memory A, then it is marked in memory A as the last memorized element. If element J is already present in memory B, then it is moved to memory A at the location of the last memorized element. In these two cases, the device 5 then returns the information according to which the element J is present.
- J is memorized in memory A. If memory A already contained M elements, then the oldest element memorized in memory A is transmitted to memory B to be recorded there. It is at the same time erased from memory A to make room for element J. If memory B is also full, that is to say if it already contains P elements, then an element already memorized in memory B is randomly selected to be deleted and replaced by the oldest element in memory A. The device 5 then returns the information according to which the element J was not present but is now memorized.
- the storage device 5 comprises a management device 1 and two memories A and B referenced 2 and 3 respectively.
- the management device 1 has three inputs 10, 13 and 15 and three outputs 11, 12 and 14.
- the input 10 receives the element J to be memorized which is then transmitted to the output 12 of the management device.
- the output 11 is a boolean signal which indicates whether the element J is already memorized in the storage device 5.
- the signal present at the output 11 is worth “1” (for "true") if the element J is already memorized and is worth “0"
- Inputs 13 and 15 and output 14 are also Boolean signals which will be described below.
- the memory A has two inputs 20 and 21 and two outputs 22 and 23.
- the input 20 receives the output 12 of the management device which transmits to it the element J to be memorized or whose presence must be sought in the memory A.
- the input 21 which is connected to the output 14 of the management device 1 is a Boolean signal which indicates, when its value is "1"("true") that the element J received at the input 20 must be stored in memory A.
- the output 22 of memory A is also a Boolean signal which indicates, when its value is "1" ("true"), that the element J presented at input 20 is already present in memory A. This output 22 is connected to input 15 of the management device 1.
- the output 23 of memory A is used only when memory A is full and a new element present at input 20 must be memorized. In this case, output 23 provides the oldest element stored in memory A. Otherwise, output 23 provides no signal.
- the memory B has two inputs 30 and 32 and an output 31.
- the input 30 is connected to the output 12 of the management device 1 and receives the element J whose presence in the memory B must be verified.
- the output 31 is a Boolean signal whose value is "1" ("true") when the element J received at the input 30 is present in the memory B; it is connected to input 13 of the management device 1.
- the input 32 of the memory B receives the element to be memorized which comes from the memory A when the latter is full.
- the input 32 is for this purpose connected to the output 23 of the memory A.
- the operation of the assembly is as follows.
- the management device 1 receives an element J at its input 10, it supplies this element J at its output 12. If this element J is present in memory A, a signal “1" (for "true”) is received on the input 15 of the management device 1. If the element J is present in the memory B, a signal “1” (for "true”) is received at the input 13 of the management device 1.
- the management device 1 provides on its output 11 a signal "0" (“false") and on its output 14 a signal "1" signifying that the element
- the management device 1 If the boolean signal received on input 15 has a value "1"("true"), signifying that the element J is already present in memory A, then the management device 1 provides on its output 11 a signal “ 1 "(" true ") and on its output 14 a signal” 0 ". In the case where the boolean signal received on the input 13 has a value "1"("true"), signifying that the element J is already present in the memory B, then the management device 1 supplies on its output 11 a signal "1"("true") and on its output 14 a signal "1".
- memory A When memory A receives an element J at its input 20, it first checks whether it already contains this element. If element J is already present in memory A, then the signal at output 22 takes the value "1" ("true"). Element J is then designated as the element memorized last by memory A. For example, element J is placed at the head of the stack if memory A has a stack structure, or else an index table elements stored in memory A is updated.
- output 22 takes the value "0" ("false").
- Memory B behaves differently from memory A.
- the signal 31 is "false"
- the memory B contains fewer than P elements and it stores the new element J
- memory B already contains P elements, that is to say that it is full. In the latter case, it randomly selects an item already memorized in memory B and it erases it to memorize instead the new element received on its input 32.
- Memory B is therefore emptied randomly.
- a hacker who wishes to eliminate an element from the storage device 5 should therefore make many more attempts than in the case of a simple FIFO type memory. Indeed, if the overall memory size is N elements, an attacker will have to make on average many more than N attempts to eliminate an element from memory.
- memories A and B which are shown separately in the single figure can in reality be two subsets of the same physical memory.
- the storage device 5 may in fact include a memory A of zero size.
- a user is allowed to present a determined number of times each element to the storage device. For example, if this device is integrated into a recording device, and if this device is authorized to make a number x of copies of each content, it will be stored in the memory, with each identifier of content already recorded by the device, the number y of times the content was presented to the device for recording. When the number y of presentation of a given content reaches the number x, then it is no longer possible to record this content and the storage device 5 will return corresponding information to the recording apparatus.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Storage Device Security (AREA)
- Time Recorders, Dirve Recorders, Access Control (AREA)
- Semiconductor Integrated Circuits (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Electrically Operated Instructional Devices (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0213333 | 2002-10-16 | ||
FR0213333A FR2846114A1 (fr) | 2002-10-16 | 2002-10-16 | Dispositif de memorisation d'une liste d'elements et procede de memorisation d'un element dans un tel dispositif |
PCT/EP2003/050718 WO2004036411A2 (fr) | 2002-10-16 | 2003-10-14 | Dispositif de memorisation d'une liste d'elements et procede de memorisation d'un element dans un tel dispositif |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1573507A2 true EP1573507A2 (fr) | 2005-09-14 |
Family
ID=32050668
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP03780166A Withdrawn EP1573507A2 (fr) | 2002-10-16 | 2003-10-14 | Dispositif de memorisation d une liste d elements et pr ocede de memorisation d un element dans un tel dispositif |
Country Status (9)
Country | Link |
---|---|
US (1) | US20060155666A1 (fr) |
EP (1) | EP1573507A2 (fr) |
JP (1) | JP2006515441A (fr) |
KR (1) | KR100952803B1 (fr) |
CN (1) | CN100565444C (fr) |
AU (1) | AU2003288268A1 (fr) |
FR (1) | FR2846114A1 (fr) |
MX (1) | MXPA05003915A (fr) |
WO (1) | WO2004036411A2 (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11626010B2 (en) * | 2019-02-28 | 2023-04-11 | Nortek Security & Control Llc | Dynamic partition of a security system |
US20200279473A1 (en) * | 2019-02-28 | 2020-09-03 | Nortek Security & Control Llc | Virtual partition of a security system |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4008460A (en) * | 1975-12-24 | 1977-02-15 | International Business Machines Corporation | Circuit for implementing a modified LRU replacement algorithm for a cache |
GB2251323B (en) * | 1990-12-31 | 1994-10-12 | Intel Corp | Disk emulation for a non-volatile semiconductor memory |
US5381539A (en) * | 1992-06-04 | 1995-01-10 | Emc Corporation | System and method for dynamically controlling cache management |
US5450562A (en) * | 1992-10-19 | 1995-09-12 | Hewlett-Packard Company | Cache-based data compression/decompression |
JP3218107B2 (ja) * | 1993-01-29 | 2001-10-15 | ローム株式会社 | ファジィニューロン |
US5623627A (en) * | 1993-12-09 | 1997-04-22 | Advanced Micro Devices, Inc. | Computer memory architecture including a replacement cache |
EP0675436B1 (fr) * | 1994-03-31 | 1999-10-27 | STMicroelectronics, Inc. | Antémémoire associative récupérable |
JP3568110B2 (ja) * | 1999-10-15 | 2004-09-22 | インターナショナル・ビジネス・マシーンズ・コーポレーション | キャッシュメモリの制御方法、コンピュータシステム、ハードディスクドライブ装置およびハードディスク制御装置 |
CN100414864C (zh) * | 2000-03-09 | 2008-08-27 | 松下电器产业株式会社 | 具有编辑装置和记录媒体的音频数据重放管理系统及方法 |
US20020069341A1 (en) * | 2000-08-21 | 2002-06-06 | Gerard Chauvel | Multilevel cache architecture and data transfer |
EP1182570A3 (fr) * | 2000-08-21 | 2004-08-04 | Texas Instruments Incorporated | Mémoire tampon de traduction d'adresses avec champ d'identification de ressource |
US7174194B2 (en) * | 2000-10-24 | 2007-02-06 | Texas Instruments Incorporated | Temperature field controlled scheduling for processing systems |
-
2002
- 2002-10-16 FR FR0213333A patent/FR2846114A1/fr active Pending
-
2003
- 2003-10-14 US US10/530,899 patent/US20060155666A1/en not_active Abandoned
- 2003-10-14 JP JP2004544311A patent/JP2006515441A/ja active Pending
- 2003-10-14 KR KR1020057006614A patent/KR100952803B1/ko not_active IP Right Cessation
- 2003-10-14 CN CNB2003801016435A patent/CN100565444C/zh not_active Expired - Fee Related
- 2003-10-14 AU AU2003288268A patent/AU2003288268A1/en not_active Abandoned
- 2003-10-14 MX MXPA05003915A patent/MXPA05003915A/es active IP Right Grant
- 2003-10-14 WO PCT/EP2003/050718 patent/WO2004036411A2/fr active Application Filing
- 2003-10-14 EP EP03780166A patent/EP1573507A2/fr not_active Withdrawn
Non-Patent Citations (1)
Title |
---|
See references of WO2004036411A2 * |
Also Published As
Publication number | Publication date |
---|---|
AU2003288268A8 (en) | 2004-05-04 |
FR2846114A1 (fr) | 2004-04-23 |
CN100565444C (zh) | 2009-12-02 |
KR20050084855A (ko) | 2005-08-29 |
WO2004036411A3 (fr) | 2005-03-24 |
KR100952803B1 (ko) | 2010-04-14 |
JP2006515441A (ja) | 2006-05-25 |
WO2004036411A2 (fr) | 2004-04-29 |
AU2003288268A1 (en) | 2004-05-04 |
MXPA05003915A (es) | 2005-08-16 |
CN1705931A (zh) | 2005-12-07 |
US20060155666A1 (en) | 2006-07-13 |
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RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: THOMSON LICENSING |
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RBV | Designated contracting states (corrected) |
Designated state(s): DE ES FR GB IT |
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RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
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Effective date: 20160125 |
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Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
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18D | Application deemed to be withdrawn |
Effective date: 20160705 |