EP1560134A2 - Leiterplatte mit Emulationsschaltkreis und Netzwerkinterface - Google Patents

Leiterplatte mit Emulationsschaltkreis und Netzwerkinterface Download PDF

Info

Publication number
EP1560134A2
EP1560134A2 EP04105443A EP04105443A EP1560134A2 EP 1560134 A2 EP1560134 A2 EP 1560134A2 EP 04105443 A EP04105443 A EP 04105443A EP 04105443 A EP04105443 A EP 04105443A EP 1560134 A2 EP1560134 A2 EP 1560134A2
Authority
EP
European Patent Office
Prior art keywords
network
resource
emulation
interface circuit
ram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04105443A
Other languages
English (en)
French (fr)
Other versions
EP1560134A3 (de
Inventor
Sweyyan Shei
Ming Yang Wang
Vincent Chiu
Neu Choo Ngui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Springsoft Inc
Original Assignee
Fortelink Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fortelink Inc filed Critical Fortelink Inc
Publication of EP1560134A2 publication Critical patent/EP1560134A2/de
Publication of EP1560134A3 publication Critical patent/EP1560134A3/de
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Definitions

  • the present invention relates to systems employing programmable logic devices and other resources to emulate the behaviour of an electronic circuit, and in particular to a circuit board for providing emulation resources for an emulation system.
  • a typical digital integrated circuit employs register transfer logic (RTL) wherein each block of logic within the IC includes an output register for synchronizing state changes in its output signals to edges of a clock signal.
  • RTL register transfer logic
  • An IC designer will usually generate an initial, high-level netlist employing Boolean expressions to characterize each block of logic. The designer will then employ a synthesis tool to convert the high level netlist into a "gate level" netlist describing the logic blocks as sets of interconnected cells, where each cell is a standard IC component such as a transistor or a logic gate.
  • the gate level netlist references each cell instance to be included in the IC by referring to an entry for that cell type in a cell library, a database including an entry for each kind of cell that can be included in an IC.
  • the cell library entry for each cell type describes the internal layout of the cell and includes a model of the cell's behaviour.
  • the designer employs a placement and routing (P&R) tool to convert the gate level netlist into an IC layout file indicating the position within a semiconductor die of each cell forming the IC and describing how the nets are to be routed between cell terminals.
  • the layout file guides IC fabrication.
  • An IC designer can use computer-aided simulation and verification tools at each step of the design process to verify that the IC described by the design will behave as expected.
  • the designer develops a "test bench" incorporating a netlist describing the IC to be simulated and indicating how the IC's input signals are to change state over time.
  • the test bench will also list various signals of the IC to be monitored during the simulation.
  • the simulator creates a behavioural model of the IC based on the test bench description of the IC and on behavioural models of the IC's cells obtained from the cell library, and then tests the IC model to determine how the monitored signals would respond to input signal patterns the test bench describes.
  • the simulator generates a "dump file" containing waveform data representing the time-varying behaviour of the monitored signals. The designer can then use various debugging tools to inspect the dump file to determine whether the IC behaved as expected.
  • a simulator can accurately model the behaviour of an IC based on either a high-level or gate-level netlist, it can require much processing time to simulate IC behaviour.
  • a designer can program a simulator to simulate only selected portions of an IC design that are new or have been modified, but this approach may not provide any assurance that the new and old portions of the design will work properly together.
  • programmable logic devices PLDs
  • PLDs programmable logic devices
  • U.S. patent 6,377,911 issued April 23, 2002 to Sample et al describes a logic emulation system employing field programmable gate arrays (“FPGAs") that can be programmed to emulate IC logic. Since FPGAs employ high-speed logic gates and other devices to emulate circuit behaviour, an emulation system using FPGAs can usually verify IC behaviour more quickly than a simulator.
  • FPGAs field programmable gate arrays
  • Fig. 1 illustrates a typical prior art emulation system 10 including a set of circuit boards 12 each holding an array of FPGAs 14, each of which can be programmed to emulate the logic of a large number of interconnected logic gates, flip-flops and registers.
  • Each FPGA 14 has many input/output (IO) terminals and many of those IO terminals are linked to IO terminals of other FPGAs 14 on the same circuit board 12 so that the FPGAs can communicate with one another.
  • ICs may include large standardized components such as embedded computer processors and memories
  • emulation system 10 may include processors, memory ICs or other devices mounted on other resource boards 18 for emulating those large IC components. Cable connectors or back plane typically provide signal paths between FPGAs 14 and other resources mounted on resource boards 12 and 18.
  • emulator 10 When emulator 10 is to act as an in-circuit emulation ("ICE") system, it emulates an IC within its intended operating environment, installed on a circuit board of an external system so that it can communicate with other devices within that system.
  • a cable 20 links IO terminals of some of FPGAs 14 to a socket of an external system 22 of the type in which the IC being emulated will eventually reside.
  • an external pattern generator 24 supplies test signal inputs to FPGAs 14 though a probe interface circuit 26 programmed to route the test signals to the appropriate FPGA terminals.
  • a logic analyser 28 monitors various signals the emulated IC produces through signal paths provided by probe interface circuit 26 provides.
  • a user programs FPGAs 14, pattern generator 24, and probe interface 26 and communicates with logic analyser 28 through a workstation 30 linked to those devices through a suitable interface circuits 32 such as for example, the workstations serial ports and JTAG bus interfaces.
  • Each FPGA 14 will have a large number of IO terminals and each circuit board 12 must provide signal paths between the FPGAs and between the FPGAs and external equipment so that they can communicate with one another.
  • Fig. 2 illustrates one prior art approach to routing signals between FPGAs wherein traces on circuit board 12 connect IO terminals of each FPGA 14 to IO terminals of many or all of the other FPGAs 14.
  • Buffers 32 mounted on circuit board 12 buffer signals passing between circuit board 12 and other resource boards and test equipment via cables or motherboard back plane wiring 34. This hard-wired approach to FPGA interconnects is relatively inexpensive, but not very flexible since the number of direct signal paths between each pair of FPGA 14, and between the resource board and other resource boards or test equipment is fixed.
  • Fig. 3 illustrates another prior art approach to signal routing between FPGAs 14 wherein the IO terminals of FPGAs 14 and the external signal buffers 32 all communicate through a switching matrix 34, such as a crosspoint switch, mounted on circuit board 12.
  • the switch matrix approach provides more flexible routing than the fixed routing of Fig. 2 because it allows any FPGA terminal to directly communicate within any other FPGA terminal or any external resource.
  • the number of signal paths switch matrix 34 must provide is proportional to the square of the number of FPGA terminals and buffered signal paths to be interconnected, the necessary switch matrix size becomes impractically large for a circuit board having a large array of FPGAs, each having a large number of IO terminals.
  • the resource board should also provide the logic and balanced signal paths needed to deliver clock signals to the PLDs. It would also be helpful to reduce the number of signals needed to communicate with external equipment by implementing much of the pattern generation and data acquisition functionality needed to test an emulated circuit on the resource board itself.
  • the invention provides to a resource board (a circuit board containing emulation resources) for an emulation system that may include several such resource boards and one or more workstations. Each resource board communicates with other resource boards and with one or more workstations through data packets transmitted over a network. Each resource board includes a "network/resource interface circuit" acting as an interface between the network and emulation resources such as field programmable gate arrays (FPGAs) or other types of programmable logic devices (PLDs) mounted on the resource board.
  • FPGAs field programmable gate arrays
  • PLDs programmable logic devices
  • a network/resource interface circuit of one resource board can monitor output signals of PLDs mounted on that resource board and send packets containing data indicating the states of those output signals to a network/resource interface circuit of another resource board.
  • the packet receiving network/resource interface circuit can then drive signals supplied to input terminals of selected PLDs mounted on its local resource board to states indicated by the data conveyed in the packets.
  • a "local bus" formed on the resource board connects the network/resource interface circuit to several input/output (IO) terminals of each PLD to allow the network/resource interface circuit to transmit input signals to each FPGA and to monitor output signals produced by each FPGA when the network/resource interface circuit is providing virtual signals paths between an FPGA and resources external to the resource board.
  • IO input/output
  • the packet routing network can also provide virtual signal paths between the workstation and the resource boards.
  • the workstation can also send PLD programming data via packets to the network/resource interface circuit on each resource board, with each packet being addressed to a particular PLD to be programmed.
  • a "select map" bus connected between the network/resource interface circuit and each PLD on the board allows the network/resource interface circuit to forward programming data arriving in a packet to the addressed PLD.
  • an emulation resource board in accordance with the invention provides a convenient way to interface a workstation to emulation resources on the board to allow the workstation to program the emulation resources on the board and to also emulate a portion of the IC being emulated and to program the emulation resources on the board.
  • a resource board in accordance with a preferred embodiment of the invention includes several FPGAs or other types of PLDs and a separate random access memory (RAM) corresponding to each FPGA.
  • a set of switches controlled by the network/resource interface circuit in response to control data received via incoming packets selectively couple terminals of each FPGA to its corresponding RAM, thereby allowing circuits emulated by the FPGA to read and write access the RAM so that the RAM can emulate memory embedded in the circuit being emulated.
  • a workstation can also program the resource board's network/resource interface circuit to act as a pattern generator supplying test signal inputs to the portions of the circuit being emulated on the resource board.
  • the network/resource interface circuit includes RAM for storing data for controlling the signal patterns it is to generate during the emulation, and a workstation can load the pattern control data into the RAM prior to the start of the emulation by sending it in packets to the network/resource interface circuit.
  • the network/resource interface circuit can also act as a data acquisition system by monitoring PLD output signals and storing "probe data" in its RAM representing PLD output signal state sequence that occur during an emulation. The network/resource interface circuit can then forward the probe data in packets to a workstation for analysis.
  • a "probe bus" formed on the resource board connects several other IO terminals of each PLD to the network/resource interface circuit to enable the network/resource interface circuit to send test signals to and monitor output signals from the PLD.
  • a workstation can also program the network/resource interface circuit to act as a clock logic circuit for deriving signals for clocking logic within the PLDs from number of clock signal sources.
  • a clock bus formed on the resource board delivers clock signal edges concurrently from the network/resource interface circuit to each PLD and also delivers gating signals from each PLD back to the network/resource interface circuit.
  • each resource board includes connectors allowing cables to provide high-bandwidth hard-wire paths between PLD IO terminals on that resource board and other resources when necessary.
  • the cable connectors can also be used to connect terminals of the PLDs to an IC socket in a target circuit board when the emulation system is to act as an in-circuit emulator.
  • an emulation resource board in accordance with the invention holds PLDs and RAMs and employs both hard-wired and virtual signal paths to flexibly route signals between the PLDs and RAMS on the resource board and between the PLDs and other resource boards, workstations and other external equipment.
  • the resource board also provides the logic and balanced signal paths needed to deliver clock signals to the PLDs and reduces the number of signals needed to communicate with external test equipment by implementing much of the pattern generation and data acquisition functionality needed to test an emulated circuit.
  • the present invention relates to a network-based emulation system using various programmable resources to emulate the behaviour of an IC to determine how signals an IC produces would behave in response to test signals applied as inputs to the IC.
  • the invention relates in particular to a circuit board employed by the emulation system for holding emulation resources, for providing programming and data signal paths to the resources, and for providing some test functions needed during a circuit emulation. While the specification below and the accompanying drawings depict an example embodiment of an emulation resource board considered to be a best mode of practicing the invention, those of skill in the art will appreciate that the invention may be practiced in other ways.
  • the claims appended to this specification therefore apply not only to the example embodiment described below but to any embodiment of the invention including elements or steps that may be functional equivalents of the example elements or steps of the exemplary embodiment of the invention depicted in the specification and drawings.
  • Fig. 4 illustrates an example emulation system 40 in accordance with the invention including a computer workstation 42, one or more "resource boards” 44, and a packet routing network 46 comprising one or more network buses that may be interconnected by conventional network routers, switches or hubs.
  • Each resource board 44 holds one or more emulation resources 48 for use in emulating portions of an IC.
  • Emulation resources 48 may include, for example, programmable gate arrays (FPGAs) or other types of programmable logic devices (PLDs), random access or read only memories, application specific integrated circuits (ASICs), microprocessors or any other devices suitable for emulating portions of an IC at various levels of abstraction.
  • Each resource board 44 also includes a "network/resource interface circuit" 49 for providing an interface between packet routing network 46 and emulation resources 48.
  • Workstation 42 and network/resource interface circuit 49 may transmit packets to one another via packet routing network 46.
  • packet routing network 46 Various types of networks known to those of skill in the art can implement packet routing network 46, and each packet is arranged in accordance with the particular physical layer protocol the network uses. However, each packet will typically include a header containing information the network needs to route the packet to the appropriate destination, along with the payload data the packet is to convey to the recipient.
  • Workstation 42, each network/resource interface circuit 49, and each emulation resource 48 has a unique network address, and the header included in each data packet transmitted via packet routing network 46 suitably indicates the network addresses of the devices designated as the source and destination of the packet. 42.
  • the header also includes a command telling the recipient network/resource interface circuit or workstation to carry out some type of an action.
  • the packet's payload data acts as an argument to the command included in the header and may be of fixed or variable length depending on the nature of the network(s physical layer protocol, though variable length packets are preferable. For example, if the command tells a receiving network/resource interface circuit 49 to drive particular signals of an addressed emulation resource 48 to particular states, then the payload constituting the command(s argument will reference those signals and indicate the states to which they are to be driven.
  • a network/resource interface circuit 49 will execute the command in an incoming packet only if the network destination address included in the packet header matches the address of any emulation resource 48 on the local resource board 44.
  • each network/resource interface circuit 49 of each resource board 44 not only transmits and receives packets but also communicates with the local emulation resources 48 on that resource board. Since the types of transactions each network/resource interface circuit 49 carries out during an emulation depends to some extent on the nature of the circuit to be emulated, each network/resource interface circuit 49 includes one or more programmable logic devices that can be programmed to carry out various functions during a circuit emulation. network/resource interface circuit's 49 are initially loaded with a boot program supplied from an external source through a JTAG or other type of bus, or via a programmable read only memory to enable the network/resource interface circuit to communicate via packet routing network 46. With the boot program loaded into network/resource interface circuit 49, workstation 42 can thereafter reprogram network/resource interface circuit 49 using programming data conveyed by incoming packets addressed to network/resource interface circuit 49.
  • Packets from a workstation also convey emulation resource programming data.
  • emulation resources 48 includes FPGAs
  • workstation 42 addresses packets conveying a "download" command and FPGA programming data to the particular FPGAs to be programmed.
  • the network/resource interface circuit 49 on the resource board 44 containing an addressed FPGA responds to the download command in the incoming packet by forwarding the packet's payload programming data to the programming input of that FPGA.
  • a packet may convey data indicating current states of resource output signals or indicating state to which resource input signals are to be driven. For example a "read" command in an incoming packet can tell a network/resource interface circuit 49 to return a signal data packet to the source address containing payload data indicating states of signals at various IO terminals of an FPGA addressed by the incoming packet's destination address. A "force" command in a packet can tell a receiving network/resource interface circuit 49 to drive specified IO terminals of an emulation resource addressed by the packet's destination address to particular states.
  • a sequence of packets containing force commands can emulate the behaviour of signal paths between output terminals of emulation resources 48 on the resource board 44 sending the packets and input terminals of emulation resources 48 on the resource board to which the packets are addressed.
  • the force commands implement "virtual signal paths" between IO terminals of resources mounted on separate emulation boards so that emulate the logical behaviour of hard-wired signal paths.
  • workstation 42 In a "co-validation mode of operation", workstation 42 (or any other computer accessing packet routing network 46) can emulate some portions of an IC while emulation resources 48 on resource boards 44 emulate other portions of the IC. In that mode of operation, workstation 42 and network/resource interface circuits 49 can use packets conveying force commands to drive signal inputs to resources within various modules.
  • a resource board 44 may include a large amount of random access memory that can, for example, emulate the function of a large memory bank.
  • a write command conveyed in an incoming packet(s header might tell network/resource interface circuit 49 to write data to a particular address or a block of addresses within the memory selected by the packet's destination address.
  • the packet's data payload references the memory address or addresses to be accessed as well as the data to be written to that memory address.
  • a memory read command in an incoming packet tells a network/resource interface circuit 49 to read data at a particular address or block of addresses of a memory addressed by the destination address and to return the data read out of the memory in a packet addressed to the device identified by the source address included in the incoming packet(s header.
  • the packet routing system can implement a "virtual memory bus" enabling the workstation or any emulation resource to read or write access a memory mounted on a resource board.
  • Emulation system 40 can act as an in-circuit emulator (ICE) emulating an IC in its intended operating environment, installed in a socket within an external "target system” 47 such as a circuit board containing other components.
  • ICE operating mode emulation resources 48 communicate directly with external system 47, for example, through signal paths provided by a cable having a connector that plugs into the socket within target system 47 normally intended to hold the IC being emulated.
  • Fig. 5 is a plan view of an example resource board in accordance with the invention suitable for use as one of resource boards 44 of Fig. 3.
  • the emulation resources mounted on resource board 44 include a set of eight FPGAs F1-F8 and a set of eight RAMs M1-M8.
  • the board's network/resource interface circuit 49 includes a resource controller 50, a bus switch 52, a set of RAMs 53 (suitably high-speed SDRAMs, DDRs or QDRs), a pair of oscillators 54, an input/output clock buffer IC 55 and a network interface circuit 56.
  • Network interface 56 handles packet communications between network 46 and resource controller 50.
  • Each FPGA F1-F8 is suitably an Xilinx model Virtex-II 6000 FF1517 having 1104 IO pins and providing up to 400K gates, however other FPGA makes and models and be used. Other types of PLDs could also be mounted on the resources board in addition to or in lieu of FPGAs F1-F8.
  • Resource controller 50 suitably implemented by a boot PROM and a Xilinx Virtex-II FPGA, has several functions as discussed below.
  • Resource controller 50 programs FPGAs F1-F8 with programming data workstation 42 sends via packets to network interface 56.
  • Each FPGA F1-F8 has its own network address, and before the start of an emulation, resource controller 50 forwards the programming data addressed to each FPGA that is to take part in the emulation.
  • the network interface 56 on each resource board 44 forwards FPGA programming data addressed to any of local FPGAs F1-F8 to resource controller 50, and the resource controller 50 loads the programming data into the addressed FPGA.
  • resource controller 50 can act as a programmable pattern generator providing test signal inputs to the IC being emulated.
  • resource controller 50 Before the start of the emulation process, workstation 42 or any other device accessing the packet routing network, loads data into RAMs 53 defining the test signal patterns resource controller 50 is to generate during the emulation. Resource controller 50 then reads the programming data out of RAMS 53 during the emulation to determine how to control the test signals it supplies to FPGAs F1-F8. Resource controller 50 can also act as a data acquisition system during an emulation, sampling signals FPGAs F1-F8 produce during an emulation and storing "probe data" in RAMs 53 indicating the states of those signals. At various times during the emulation, or when the emulation is complete, resource controller 50 can read the probe data out of RAMs 53 and forward it via packets to workstation 42. Workstation 42 can then use the probe data as a basis for analysing the behaviour of the emulated IC, for producing waveform displays, or for any other purpose.
  • resource controller 50 can communicate with workstation 42 and with resource controllers on other resource boards using packets sent and received over packet routing network 46 (Fig. 4) and network interface circuit 56.
  • packet routing network 46 Fig. 4
  • network interface circuit 56 For example, suppose workstation 42 has programmed FPGAs mounted on different resource boards to implement separate portions of an IC and that IO terminals of those separate portions are to communicate with one another through a set of signals.
  • Resource controller 50 can monitor output signals of FPGAs F1-F8 on resource board 44 that are to act as input signals to FPGAs or other devices on another resource board and, following each cycle of a system clock, can send a force command packet to the other resource board containing data indicating the state of each FPGA output signal.
  • the force command tells the resource controller on the other resource board to drive the appropriate input signals of its emulation resources to the indicated states at the start of the next system clock cycle.
  • resource controller 50 can respond to a force command packet from the resource controller on the other circuit board by driving the appropriate FPGA inputs to the states indicated by the state data in the incoming write command packet.
  • Resource controller 50 can also send or respond to "read command" packets requesting a recipient controller to read states of signals produced by local emulation resources and return a response packet containing data indicating those signals states.
  • each resource board 44 can act as a set of "virtual signal paths" that appear to interconnect terminals of portions of an IC being emulated by workstation 42 and the separate resource boards 44.
  • Resource board 44 also includes a set of connectors J1-J8, each linked by conductive traces on the board to terminals of a corresponding one of FPGAs F1-F8.
  • a cable connected between connector J1 and a connector on the other resource board can provide high bandwidth, hard-wire signal paths between FPGA F1 and other resource board.
  • the emulation system may act as an in-circuit emulation (ICE) system, emulating an IC when mounted in its intended operating environment, for example, mounted in a socket on a target board. In such case a cable connected between the target board socket and any subset of connectors J1-J8 can provide the necessary signal paths between resource board 44 and the target board.
  • ICE in-circuit emulation
  • each FGPA F1-F8 is suitably an Xilinx model Virtex-II 6000 FF1517 having 1104 IO terminals, and traces 60 suitably hard wire a total of 840 IO terminals of each FPGA F1-F8 to IO terminals of the other FPGAs.
  • traces 62 link 144 IO terminals of each FPGA F1-F8 to a corresponding one of connectors J1-J8 and, through a switch S1-S8, to a corresponding one of RAMs M1-M8.
  • Bus switch 52 of Fig. 5 implements switches S1-S8, and an additional switch S9 linking connectors F1 and F5.
  • Control data stored in control registers 64 within resource controller 50 control the switching states of switches S1-S9.
  • workstation 42 (Fig. 3) sends a packet to resource board 44 telling it to load appropriate control data into registers 64.
  • switches S1-S8 When none of RAMs M1-M8 are needed during an emulation, switches S1-S8 are open, but when any of FPGAs F1-F8 are to access its corresponding one of RAMs M1-M8 during a emulation, its corresponding switch S1-S8 remains closed to provide the necessary signal paths between the FPGA and its corresponding RAM.
  • switch S9 can be closed to provide an additional 144 signal paths between those two FPGAs.
  • a cable connected to any of connectors J1-J8 can link up to 144 IO terminals of its corresponding FPGA F1-F8 to terminals of external devices that are to directly communicate with the FPGAs.
  • a circuit board or cable plugged into and providing signal paths between connectors J1-J8 can be used when necessary to increase the number of direct connections between any set of FPGAs F1-F8.
  • a "local controller” 68 implemented within resource controller 50, can act as the local end of up to 52 virtual signal paths linking terminals of FPGAs F1-F8 to terminals of other emulation resources external to the resource board.
  • Local controller 68 responds to incoming force commands conveyed in packets received via network interface 56 by driving selected lines of local bus 66 to states indicating by the force commands.
  • Local controller 68 also responds to incoming read commands by reading states of lines of local bus 66 and returning a packet containing data indicating the line states to the network device that sent the read command.
  • Local controller 68 can read states of lines of local bus 66 and then send a force command to a local controller within another resource board telling it to drive selected signals to those states.
  • Local controller 68 can also send out read commands to a local controller of another resource board requesting it to return states of lines of its local bus so that local controller 68 can drive lines its local bus 66 to similar states.
  • Resource controller 50 can also emulate portions of the IC being emulated, and is particularly suited for emulating the IC's clock logic circuits.
  • a typical digital IC will employ register transfer logic in which various blocks of logic communicate through registers and other clocked devices to provide a high level of timing synchronization between the logic blocks.
  • An IC will receive one or more primary clock signals as inputs, but may include clock logic circuit for deriving one or more secondary clock signals from its primary clock signals.
  • Fig. 12 illustrates an example clock logic circuit 80 is might be included in an IC for processing a primary clock signal CLK1 and a clock gate signal GATE to produce a secondary clock signal CLK2.
  • clock logic circuit 80 consists of an AND gate 82 producing the CLK2 signal of similar phase and frequency as the CLK signal when the GATE signal is high, and turning off the CLK2 signal when the GATE signal is low.
  • clock logic circuits can include many more inputs and more complicated clock logic.
  • a pair of clock trees 84 and 86 (networks of conductors and buffers) deliver the CLK1 and CLK2 clock signal to the clock inputs of various clocked devices 88 and 89, such as registers and flip-flops, that may be used for controlling the timing of data signals passing between various blocks of logic within the IC.
  • clock trees 84 and 86 are balanced so that edges of clock signal CLK1 arrive concurrently at clocked devices 88 and edges of the CLK2 clock signal arrive concurrently at clocked devices 89.
  • resource board 44 of Fig. 5 programmable logic within resource controller 50 can emulate clock logic circuit 80, logic within FPGAs F1-F8 emulate clocked devices 88 and 89, and balanced signal on resource board 44 extending from clock logic circuit 80 to FPGAs F1-F8 and signal paths inside the FPGAs emulate the balanced clock trees 84 and 86.
  • Resource board 44 of Fig. 5 includes a pair of oscillators 54 for generating clock signals for use as primary clock signals.
  • a connector J9 provides a point of entry for other primary clock signals from external circuits.
  • Buffers 55 buffer the clock signals produced by oscillators 54 and received via connector J9 FPGAs F1-F8.
  • Workstation 44 or any other resource board can also send "virtual clock signal edges" to resource board 44 via a virtual signal path, and resource controller 50 can supply such a virtual clock signal as an input to the clock logic it implements.
  • Fig. 9 illustrates a 16-line clock bus 70 for delivering to FPGAs F1-F8 via buffers 55 up to 16 clock signals produced by clock logic circuits 72 implemented within resource controller 50.
  • Clock logic circuits 72 can receive clock signal inputs from several sources.
  • Oscillators 54 supply primary clock signals (OSCCLK) of up to 16 different frequencies to clock logic circuit 70.
  • External circuits can also supply up to 16 different clock signals (ICECLK) as inputs to clock logic circuits 72 via connector J9 and buffers 56.
  • Workstation 42 and other resource boards 44 of Fig. 4 can supply up to sixteen different clock signals (COSCLK) to clock logic circuit 72 via virtual signal paths.
  • COSCLK sixteen different clock signals
  • Clock bus 70 is a star bus having a uniform signal path length from resource controller 50 to each FPGA F1-F8, thereby ensuring that edges of each clock signal arrive concurrently at all FPGAs F1-F8.
  • Another pair of conductors delivers up to two signals (GATCLK) from each FPGA F1-F8 back to clock logic circuit 72 for use as clock gating signals.
  • Clock gating signals can, for example, turn a secondary clock signal input to FPGAs F1-F8 on or off, or switch the reference source of the secondary clock signal to another primary clock signal input of clock logic circuit 72.
  • FIG. 10 illustrates traces 74 on the resource board implementing a 4-line JTAG bus for linking resource controller 50 and JTAG terminals of FPGAs F1-F8 to external host equipment.
  • the host equipment can use the JTAG bus to initially load a bootstrap program into resource controller 50 and can also use the JTAG bus to monitor states of signals within resource controller 50 or any of FPGAs F1-F8 for diagnostic purposes.
  • Fig. 11 illustrates traces 76 on resource board 44 implementing a set of 12-line buses connecting a "select map" input of each FPGA F1-F8 to a select map controller 72 implemented within resource controller 50.
  • select map controller 72 receives FPGA programming data via download commands conveyed by packets addressed to FPGAs F1-F8 from the workstation and loads the programming data into the addressed FPGA via the appropriate select map bus 70. Programming data delivered by packets can also reprogram selected FPGAs F1-F8 to accommodate changes in the design of the IC being emulated without having to reprogram the entire emulator.
  • example emulation resource board in accordance with the invention for holding a set of PLDs and RAMs and providing both hard-wired and virtual signal paths to flexibly route signals between the PLDs and RAMS and resources mounted on other resource boards, workstations and other external equipment.
  • the resource board also provides the logic and balanced signal paths needed to deliver clock signals to the PLDs, and reduces the number of signals needed to communicate with external test equipment by implementing much of the pattern generation and data acquisition functionality needed to test an emulated circuit.
  • an emulation resource board in accordance with the invention may include more or fewer FPGAs and RAMS, may include PLDs and memories other than FPGAs and RAMS, and may include other types of emulation resources in addition to or in lieu of PLDs and RAMs.
  • the claims are therefore intended to apply to any mode of practicing the invention comprising the combination of elements or steps as described in any one of the claims, including elements or steps that may be functional equivalents of the example elements or steps of the exemplary embodiment of the invention depicted in the specification and drawings.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
EP04105443A 2003-12-11 2004-11-01 Leiterplatte mit Emulationsschaltkreis und Netzwerkinterface Withdrawn EP1560134A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/735,342 US7120571B2 (en) 2003-06-16 2003-12-11 Resource board for emulation system
US735342 2003-12-11

Publications (2)

Publication Number Publication Date
EP1560134A2 true EP1560134A2 (de) 2005-08-03
EP1560134A3 EP1560134A3 (de) 2005-10-12

Family

ID=34653594

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04105443A Withdrawn EP1560134A3 (de) 2003-12-11 2004-11-01 Leiterplatte mit Emulationsschaltkreis und Netzwerkinterface

Country Status (3)

Country Link
US (1) US7120571B2 (de)
EP (1) EP1560134A3 (de)
JP (1) JP4664056B2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006048525A (ja) * 2004-08-06 2006-02-16 Toshiba Corp シミュレーション方法
KR100731106B1 (ko) * 2005-12-29 2007-06-22 동부일렉트로닉스 주식회사 라이브러리 테스트 회로 및 그 방법
WO2008110198A1 (en) * 2007-03-09 2008-09-18 Mentor Graphics Corporation Hardware interface board for connecting an emulator to a network
JP2009140999A (ja) * 2007-12-04 2009-06-25 Toshiba Corp 半導体集積回路
US7970597B2 (en) * 2008-05-15 2011-06-28 Springsoft, Inc. Event-driven emulation system
US8683404B2 (en) * 2008-08-05 2014-03-25 Nec Corporation Semiconductor verification apparatus, method, and program
JP5333792B2 (ja) * 2008-10-08 2013-11-06 日本電気株式会社 半導体検証装置、方法およびプログラム
US8701076B2 (en) * 2009-01-22 2014-04-15 Qualcomm Incorporated Capture of interconnectivity data for multi-pin devices in the design of emulator circuit boards
JP5471406B2 (ja) * 2009-12-18 2014-04-16 日本電気株式会社 半導体検証装置および方法
US8255853B2 (en) 2010-04-08 2012-08-28 Springsoft Usa, Inc. Circuit emulation systems and methods
US20110264435A1 (en) * 2010-04-21 2011-10-27 Vixs Systems, Inc. Modular circuit emulation system
US8577666B2 (en) * 2010-04-21 2013-11-05 Vixs Systems, Inc. Clock synchronization in a modular circuit emulation system
US20110289469A1 (en) * 2010-05-21 2011-11-24 Huang Thomas B Virtual interconnection method and apparatus
WO2012057783A1 (en) * 2010-10-29 2012-05-03 Hewlett-Packard Development Company, L.P. Signal manager
US9152748B2 (en) 2011-05-06 2015-10-06 Xcelemor, Inc. Computing system with switching mechanism and method of operation thereof
US9286423B2 (en) 2012-03-30 2016-03-15 International Business Machines Corporation Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator
US9230046B2 (en) * 2012-03-30 2016-01-05 International Business Machines Corporation Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator
US20150012903A1 (en) * 2013-07-04 2015-01-08 Tabula, Inc. Non-intrusive monitoring and control of integrated circuits
US9516054B2 (en) * 2014-04-14 2016-12-06 Trap Data Security Ltd. System and method for cyber threats detection
EP2988420B1 (de) * 2014-08-20 2021-03-10 Framatome Schaltungsanordnung für ein sicherheits-i&c-system
US9959375B2 (en) * 2014-10-06 2018-05-01 Synopsys, Inc. Efficient emulation and logic analysis
US10198538B1 (en) * 2015-12-28 2019-02-05 Cadence Design Systems, Inc. Relocate targets to different domains in an emulator
US9652573B1 (en) * 2016-10-17 2017-05-16 Synopsys, Inc. Creating and using a wide-gate data structure to represent a wide-gate in an integrated circuit (IC) design
CN109428588B (zh) * 2017-08-28 2023-12-12 中科亿海微电子科技（苏州）有限公司 具有低时钟偏斜特征的三维fpga
US10796040B2 (en) * 2019-02-05 2020-10-06 Arm Limited Integrated circuit design and fabrication
US11681804B2 (en) 2020-03-09 2023-06-20 Commvault Systems, Inc. System and method for automatic generation of malware detection traps

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6026230A (en) * 1997-05-02 2000-02-15 Axis Systems, Inc. Memory simulation system and method

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0820967B2 (ja) * 1987-09-25 1996-03-04 三菱電機株式会社 集積回路
US5671432A (en) * 1995-06-02 1997-09-23 International Business Machines Corporation Programmable array I/O-routing resource
US5907697A (en) * 1995-10-13 1999-05-25 Mentor Graphics Corporation Emulation system having a scalable multi-level multi-stage hybrid programmable interconnect network
US5802348A (en) * 1995-12-18 1998-09-01 Virtual Machine Works, Inc. Logic analysis system for logic emulation systems
US5841967A (en) * 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
US6651225B1 (en) * 1997-05-02 2003-11-18 Axis Systems, Inc. Dynamic evaluation logic system and method
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US6034538A (en) * 1998-01-21 2000-03-07 Lucent Technologies Inc. Virtual logic system for reconfigurable hardware
US6275499B1 (en) * 1998-03-31 2001-08-14 Alcatel Usa Sourcing, L.P. OC3 delivery unit; unit controller
JP2000163456A (ja) * 1998-11-25 2000-06-16 Hitachi Ltd 論理検証方法
US6539438B1 (en) * 1999-01-15 2003-03-25 Quickflex Inc. Reconfigurable computing system and method and apparatus employing same
US6604230B1 (en) * 1999-02-09 2003-08-05 The Governing Counsel Of The University Of Toronto Multi-logic device systems having partial crossbar and direct interconnection architectures
US6832185B1 (en) * 2000-03-09 2004-12-14 Quickturn Design Systems, Inc. Non-synchronous hardware emulator
JP2002041321A (ja) * 2000-07-24 2002-02-08 Mitsubishi Electric Corp 検証方式及びエミュレーション基板
US7054802B2 (en) * 2000-10-20 2006-05-30 Quickturn Design Systems, Inc. Hardware-assisted design verification system using a packet-based protocol logic synthesized for efficient data loading and unloading
US6754763B2 (en) * 2001-07-30 2004-06-22 Axis Systems, Inc. Multi-board connection system for use in electronic design automation

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6026230A (en) * 1997-05-02 2000-02-15 Axis Systems, Inc. Memory simulation system and method

Also Published As

Publication number Publication date
EP1560134A3 (de) 2005-10-12
US7120571B2 (en) 2006-10-10
US20040254906A1 (en) 2004-12-16
JP4664056B2 (ja) 2011-04-06
JP2005174349A (ja) 2005-06-30

Similar Documents

Publication Publication Date Title
US7120571B2 (en) Resource board for emulation system
US7072825B2 (en) Hierarchical, network-based emulation system
US7366652B2 (en) Method of programming a co-verification system
US9449138B2 (en) Prototype and emulation system for multiple custom prototype boards
US5663900A (en) Electronic simulation and emulation system
US6785873B1 (en) Emulation system with multiple asynchronous clocks
US7512728B2 (en) Inter-chip communication system
US6389379B1 (en) Converification system and method
US6810442B1 (en) Memory mapping system and method
US6182247B1 (en) Embedded logic analyzer for a programmable logic device
JP4125675B2 (ja) タイミングに鈍感なグリッチのない論理システムおよび方法
US8997034B2 (en) Emulation-based functional qualification
US8732650B2 (en) Method and apparatus for versatile controllability and observability in prototype system
JP2002505024A (ja) 並行ハードウェア―ソフトウェア・コシミュレーション
EP0410502B1 (de) Methode und Gerät zur Wechselwirkung-Emulation zwischen einer anwendungsspezifischen integrierten Schaltung (ASIC) während der Entwicklung und ein Zielsystem
Tessier et al. The virtual wires emulation system: A gate-efficient ASIC prototyping environment
US7036046B2 (en) PLD debugging hub
KR100928134B1 (ko) 주문형 ｖｃｄ 시스템 및 방법
US6850880B1 (en) High speed software driven emulator comprised of a plurality of emulation processors with an improved maintenance bus that streams data at high speed
Goossens et al. A high-level debug environment for communication-centric debug
US7703054B2 (en) Circuit emulation and debugging method
US20230306169A1 (en) Hybrid Switching Architecture For SerDes Communication Channels In Reconfigurable Hardware Modeling Circuits
KR20000038391A (ko) 에프피쥐에이 애뮬레이터를 이용한 멀티 에프피쥐에이 검증방법

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL HR LT LV MK YU

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL HR LT LV MK YU

17P Request for examination filed

Effective date: 20060405

AKX Designation fees paid

Designated state(s): DE FI FR GB

17Q First examination report despatched

Effective date: 20080306

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: SPRINGSOFT, INC.

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20110428