EP1559196A4 - Schneller gesteuerter ausgangspuffer - Google Patents
Schneller gesteuerter ausgangspufferInfo
- Publication number
- EP1559196A4 EP1559196A4 EP03759287A EP03759287A EP1559196A4 EP 1559196 A4 EP1559196 A4 EP 1559196A4 EP 03759287 A EP03759287 A EP 03759287A EP 03759287 A EP03759287 A EP 03759287A EP 1559196 A4 EP1559196 A4 EP 1559196A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- output buffer
- controlled output
- fast controlled
- fast
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| ITAO20020811 | 2002-09-18 | ||
| ITAO20020811 | 2002-09-18 | ||
| US323614 | 2002-12-18 | ||
| US10/323,614 US6734701B2 (en) | 2002-09-18 | 2002-12-18 | Fast controlled output buffer |
| PCT/US2003/029307 WO2004027777A2 (en) | 2002-09-18 | 2003-09-16 | A fast controlled output buffer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP1559196A2 EP1559196A2 (de) | 2005-08-03 |
| EP1559196A4 true EP1559196A4 (de) | 2009-07-01 |
Family
ID=56290486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP03759287A Withdrawn EP1559196A4 (de) | 2002-09-18 | 2003-09-16 | Schneller gesteuerter ausgangspuffer |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP1559196A4 (de) |
| KR (1) | KR20050049496A (de) |
| NO (1) | NO20051557L (de) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3929350C1 (en) * | 1989-09-04 | 1990-07-19 | Siemens Ag, 1000 Berlin Und 8000 Muenchen, De | CMOS input to digital output signal level converter - has PMOS and NMOS FET control transistors and current limiter |
| JPH03121618A (ja) * | 1989-10-04 | 1991-05-23 | Toshiba Corp | 出力回路 |
| US5214320A (en) * | 1992-06-12 | 1993-05-25 | Smos Systems, Inc. | System and method for reducing ground bounce in integrated circuit output buffers |
| US5367210A (en) * | 1992-02-12 | 1994-11-22 | Lipp Robert J | Output buffer with reduced noise |
| US5703517A (en) * | 1993-05-25 | 1997-12-30 | Texas Insturments Incorporated | Power reduction in a temperature compensating transistor circuit |
| US6130549A (en) * | 1998-07-01 | 2000-10-10 | Siemens Aktiengesellschaft | Output driver of an integrated semiconductor chip |
-
2003
- 2003-09-16 KR KR1020057004714A patent/KR20050049496A/ko not_active Ceased
- 2003-09-16 EP EP03759287A patent/EP1559196A4/de not_active Withdrawn
-
2005
- 2005-03-23 NO NO20051557A patent/NO20051557L/no not_active Application Discontinuation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3929350C1 (en) * | 1989-09-04 | 1990-07-19 | Siemens Ag, 1000 Berlin Und 8000 Muenchen, De | CMOS input to digital output signal level converter - has PMOS and NMOS FET control transistors and current limiter |
| JPH03121618A (ja) * | 1989-10-04 | 1991-05-23 | Toshiba Corp | 出力回路 |
| US5367210A (en) * | 1992-02-12 | 1994-11-22 | Lipp Robert J | Output buffer with reduced noise |
| US5214320A (en) * | 1992-06-12 | 1993-05-25 | Smos Systems, Inc. | System and method for reducing ground bounce in integrated circuit output buffers |
| US5703517A (en) * | 1993-05-25 | 1997-12-30 | Texas Insturments Incorporated | Power reduction in a temperature compensating transistor circuit |
| US6130549A (en) * | 1998-07-01 | 2000-10-10 | Siemens Aktiengesellschaft | Output driver of an integrated semiconductor chip |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20050049496A (ko) | 2005-05-25 |
| EP1559196A2 (de) | 2005-08-03 |
| NO20051557L (no) | 2005-03-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| 17P | Request for examination filed |
Effective date: 20050408 |
|
| AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR |
|
| RBV | Designated contracting states (corrected) |
Designated state(s): DE FR GB NL |
|
| A4 | Supplementary search report drawn up and despatched |
Effective date: 20090604 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
| 18D | Application deemed to be withdrawn |
Effective date: 20090331 |
|
| R18D | Application deemed to be withdrawn (corrected) |
Effective date: 20090904 |