EP1556909A1 - Vertical integrated component, component arrangement and method for production of a vertical integrated component - Google Patents
Vertical integrated component, component arrangement and method for production of a vertical integrated componentInfo
- Publication number
- EP1556909A1 EP1556909A1 EP03778239A EP03778239A EP1556909A1 EP 1556909 A1 EP1556909 A1 EP 1556909A1 EP 03778239 A EP03778239 A EP 03778239A EP 03778239 A EP03778239 A EP 03778239A EP 1556909 A1 EP1556909 A1 EP 1556909A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- conductive layer
- electrically conductive
- nanostructure
- layer
- component according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000002086 nanomaterial Substances 0.000 claims abstract description 70
- 239000003989 dielectric material Substances 0.000 claims abstract description 14
- 230000005669 field effect Effects 0.000 claims description 83
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 80
- 239000002041 carbon nanotube Substances 0.000 claims description 75
- 229910021393 carbon nanotube Inorganic materials 0.000 claims description 75
- 239000000463 material Substances 0.000 claims description 57
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 48
- 239000002071 nanotube Substances 0.000 claims description 32
- 239000003054 catalyst Substances 0.000 claims description 24
- 235000012239 silicon dioxide Nutrition 0.000 claims description 24
- 239000000377 silicon dioxide Substances 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 20
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 229910001414 potassium ion Inorganic materials 0.000 claims description 9
- 239000002073 nanorod Substances 0.000 claims description 8
- 229910052742 iron Inorganic materials 0.000 claims description 7
- 239000010941 cobalt Substances 0.000 claims description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 6
- 239000012777 electrically insulating material Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 5
- 239000003302 ferromagnetic material Substances 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 4
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- -1 Titanium molybdenum aluminum Titanium Chemical compound 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052758 niobium Inorganic materials 0.000 claims description 3
- 239000010955 niobium Substances 0.000 claims description 3
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims description 3
- PPWPWBNSKBDSPK-UHFFFAOYSA-N [B].[C] Chemical compound [B].[C] PPWPWBNSKBDSPK-UHFFFAOYSA-N 0.000 claims description 2
- CKUAXEQHGKSLHN-UHFFFAOYSA-N [C].[N] Chemical compound [C].[N] CKUAXEQHGKSLHN-UHFFFAOYSA-N 0.000 claims description 2
- 150000004770 chalcogenides Chemical class 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 2
- ITRNXVSDJBHYNJ-UHFFFAOYSA-N tungsten disulfide Chemical compound S=[W]=S ITRNXVSDJBHYNJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 2
- DZXOZMCJXVIQOP-UHFFFAOYSA-N [Ge].[In].[Si] Chemical compound [Ge].[In].[Si] DZXOZMCJXVIQOP-UHFFFAOYSA-N 0.000 claims 1
- NAWOSTKISNSQHP-UHFFFAOYSA-N tantalum titanium Chemical compound [Ti].[Ti].[Ti].[Ti].[Ti].[Ti].[Ti].[Ta].[Ta].[Ta] NAWOSTKISNSQHP-UHFFFAOYSA-N 0.000 claims 1
- 238000000034 method Methods 0.000 description 28
- 230000008569 process Effects 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 238000000151 deposition Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 description 7
- 229910052700 potassium Inorganic materials 0.000 description 7
- 239000011591 potassium Substances 0.000 description 7
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 229910052799 carbon Inorganic materials 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 230000005291 magnetic effect Effects 0.000 description 5
- 239000002070 nanowire Substances 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
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- 239000004065 semiconductor Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 3
- 238000004377 microelectronic Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical class CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 230000005294 ferromagnetic effect Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- XMWRBQBLMFGWIX-UHFFFAOYSA-N C60 fullerene Chemical compound C12=C3C(C4=C56)=C7C8=C5C5=C9C%10=C6C6=C4C1=C1C4=C6C6=C%10C%10=C9C9=C%11C5=C8C5=C8C7=C3C3=C7C2=C1C1=C2C4=C6C4=C%10C6=C9C9=C%11C5=C5C8=C3C3=C7C1=C1C2=C4C6=C2C9=C5C3=C12 XMWRBQBLMFGWIX-UHFFFAOYSA-N 0.000 description 1
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- DZVPMKQTULWACF-UHFFFAOYSA-N [B].[C].[N] Chemical compound [B].[C].[N] DZVPMKQTULWACF-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001722 carbon compounds Chemical class 0.000 description 1
- 230000003197 catalytic effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 125000002534 ethynyl group Chemical group [H]C#C* 0.000 description 1
- 229910003472 fullerene Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000002048 multi walled nanotube Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
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- 239000010980 sapphire Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002109 single walled nanotube Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000002918 waste heat Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
- H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
- H10K85/221—Carbon nanotubes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/60—Organic compounds having low molecular weight
- H10K85/615—Polycyclic condensed aromatic hydrocarbons, e.g. anthracene
Definitions
- the invention relates to a vertically integrated component, a component arrangement and a method for producing a vertically integrated component.
- Nano structures such as, for example, nanotubes, in particular carbon nanotubes, and nanorods, also called nanowires, are known as possible successors to conventional semiconductor electronics.
- Carbon nanotube is a single-walled or multi-walled tubular carbon compound.
- multi-walled nanotubes at least one inner nanotube is coaxially surrounded by an outer nanotube.
- Single-walled nanotubes typically have a diameter of Inm, the length of a nanotube can be several hundred niti. The ends of a nanotube are often terminated with half a fullerene molecule.
- Nanotubes can be produced by depositing a catalyst material layer, for example made of iron, cobalt or nickel, on a substrate and on this catalyst material layer using a chemical vapor deposition (CVD) process by introducing a carbon-containing material (for example Acetylene) are grown in the process chamber carbon nanotubes on the catalyst material layer. Because of the good electrical
- Conductivity of carbon nanotubes and due to the adjustability of this conductivity, for example by applying an external electric field or by doping the nanotubes with potassium, for example, nanotubes are suitable for a large number of applications, in particular in electrical coupling technology in integrated circuits, for components in microelectronics as well as an electron emitter.
- a carbon nanotube can be used to form such a field effect transistor, as a result of which a so-called CNT-FET (“carbon nanotube field effect transistor”) is formed.
- CNT-FET carbon nanotube field effect transistor
- a nanotube is planarly formed and contacted on a dielectric layer on a conductive substrate.
- the conductivity of the carbon nanotube is controlled via a suitable electrical voltage applied to the conductive substrate, so that the electrical current flow through the nanotube, clearly the electrical current flow between the source / drain connections of the CNT-FET, by applying a voltage to the conductive one Substrate is controllable.
- a method for forming a field effect transistor using a carbon nanotube is described, for example, in [2].
- a silicon dioxide layer is first formed on a silicon substrate and contact pads are formed thereon.
- a carbon nanotube is then applied between two contacting pads and contacted with the contacting pads, the conductivity of the carbon nanotube being controllable by applying a voltage to the silicon substrate.
- the size of the electrical current flow between the two end sections of a carbon nanotube is dependent on the conductivity of the carbon anotube at a given electrical voltage and can therefore be controlled by means of the electrical voltage on the silicon substrate.
- Carbon nanotubes, nanorods, also called nanowires, are used as nanostructures for an integrated circuit.
- free-standing zinc oxide nanowires with diameters of approximately 40 nm to 150 nm can be produced, with a density of approximately 10 3 wires per cm 2 .
- tufts of zinc oxide nanowires are used as laser components.
- Cross-formed nanowires made of p-doped silicon and n-doped gallium nitride.
- the nanowires according to [4] are only planarly formed and contacted in the horizontal direction on a substrate surface. Since the dimension of a component obtained is determined by the length of a nanostructure (on the order of micrometers), the method known from [4] runs counter to the need for progressive miniaturization.
- [7] discloses ultra-high density nanotransistors using selectively grown vertical carbon nanotubes.
- [8] discloses an electronic component with an electrically conductive connection made of carbon nanotubes and method for its production.
- the problem underlying the invention is to increase the integration density of sufficiently precisely controllable components with a nanostructure and to provide sensitive nano-structures in such a way that they are protected against mechanical damage.
- a vertically integrated component is created with a first electrically conductive layer, a middle layer partially made of dielectric material on the first electrically conductive layer and a second electrically conductive layer on the middle layer. Furthermore, a nanostructure integrated in a through-hole made in the middle layer is provided with a first end section coupled to the first electrically conductive layer and with a second end section coupled to the second electrically conductive layer.
- the middle layer has a third electrically conductive layer, the thickness of which, between two adjacent dielectric sublayers is less than the thickness of at least one of the dielectric sub-layers.
- the invention provides a component arrangement with at least two components arranged next to one another and / or with at least two components arranged one above the other with the above-mentioned features.
- a first electrically conductive layer is formed, a middle layer is partially formed from dielectric material and a through hole is made in the middle layer. Furthermore, a nanostructure having a first end section and a second end section is formed in the through hole, the first end section being coupled to the first electrically conductive layer. A second electrically conductive layer is formed on the middle layer and coupled to the second end section of the nanostructure.
- the middle layer is formed in such a way that a third electrically conductive layer is formed between two adjacent dielectric sublayers, the thickness of which is less than the thickness of at least one of the dielectric sublayers.
- a basic idea of the invention is to be seen in the fact that by means of the sufficiently thin third electrically conductive layer contained in the middle layer, the electrical conductivity of an adjacent region of the nanostructure can be controlled reliably.
- the vertically integrated component can thus be operated as a field-effect transistor-like component, the third electrically conductive layer serving in this case as a gate electrode layer, whereas the nanostructure clearly serves as a channel region.
- the third electrically conductive layer is provided sufficiently thin according to the invention, it forms when an electrical voltage is applied to the third electrically conductive layer due to an electrostatic peak effect in an adjacent surrounding area of the nanostructure, a particularly strong electric field is produced, in other words there is a field concentration. Using the field effect, the electrical conductivity in the region of the nanostructure adjacent to the third electrically conductive layer can be controlled with very high accuracy.
- the thickness of a respective layer can be set with an accuracy of up to one atomic layer, that is to say to a few angstroms.
- the desired position and thickness of the third electrically conductive layer within the middle layer can thus be defined very precisely according to the invention.
- safe blocking or safe conduction of the channel region of the field effect transistor is optionally made possible, the desired operating state in each case being adjustable by means of applying or not applying a voltage to the third electrically conductive layer.
- the adjustability of the electrical conductivity of the nanotube is clearly improved compared to the prior art in that a spatially precisely defined location of the nanostructure is influenced by means of a spatially localized electrical field of a large amplitude, instead of using a less specific and Undefined control of the conductivity of almost an entire nanostructure, as according to the prior art.
- Carbon nanotubes growing up in a through hole Carbon nanotubes growing up in a through hole.
- An advantage of the vertically integrated component according to the invention is the miniaturization of the component down to the range of lateral nanometer dimensions, since the surface requirement of a vertically integrated component is in principle only limited by the cross-sectional area of the nanostructure. Furthermore, according to the invention, the often sensitive nanostructure is incorporated in an insulating and protective matrix made of the dielectric material of the middle layer.
- the spatial arrangement of nanostructures of different vertically integrated components of a component arrangement according to the invention can be realized by specifying a spatial arrangement of through holes in which the nanostructures are grown, so that an orderly arrangement of different nanostructures is made possible. Furthermore, the presence of a crystalline substrate is unnecessary.
- Carbon nanotubes in a vertical contact hole can be technologically implemented with reasonable effort. Furthermore, the length of the nanostructure, for example a carbon nanotube, can be adjusted by dividing the thickness of the middle layer.
- the first conductive layer and the nanostructure there is preferably catalyst material for catalyzing the Forming the nanostructure arranged.
- catalyst material for catalyzing the Forming the nanostructure arranged.
- the catalyst material can, for example, be deposited locally in the through hole, alternatively a catalyst material layer can be formed between the first electrically conductive layer and the middle layer, or, in certain applications, the first conductive layer can be produced from such a material that the first electrically conductive layer can be used as a catalyst for catalyzing the formation of the nanostructure.
- the first electrically conductive layer can be made of iron material and can therefore be used as a catalyst for growing carbon nanotubes
- the third electrically conductive layer can surround the nanostructure in a surrounding area of the first or the second end section.
- the third conductive layer can be functionally split into a first and a second partial layer, the first partial layer being located in the area of the first conductive layer and the second partial layer being located in the area of the second conductive layer. With the aid of this split third conductive layer, it is possible to perform optimal gate control of the Schottky barriers formed in these areas at both end contacts of the nanostructure.
- the third electrically conductive layer surrounds the nanostructure in a surrounding area from one of the end sections of the nanostructure at which it adjoins the first or the second electrically conductive layer, an additional improvement of the
- a Schottky barrier is formed between the first electrically conductive layer and the first end section of the nanostructure, and between the second electrically conductive layer and the second end section of the nanostructure is sensitive and is very spatially localized. If the third electrically conductive layer is formed near the first or the second end section, the electrical conductivity of the nanostructure can be set particularly sensitively by applying an electrical voltage to the third electrically conductive layer.
- the thickness of the third electrically conductive layer can be less, preferably significantly less, than the thickness of both dielectric sublayers.
- the thickness ratio between the first or the second dielectric partial layer on the one hand and the third electrically conductive layer is preferably at least three, more preferably at least five, and even more preferably at least ten.
- the component according to the invention can also be designed as a field effect transistor, in which component the first end section of the nanostructure serves as the first source / drain region and the second end section of the nanostructure as the second source / drain region, and in which component in the third electrically conductive region Layer, which serves as the gate electrode of the field effect transistor, is arranged along the through hole made in the third electrically conductive layer, a ring structure made of an electrically insulating material as the gate insulating region of the field effect transistor.
- the electrical conductivity of the nanostructure can clearly be controlled by applying a suitable electrical potential to the third electrically conductive layer, since such an electrical potential characteristically influences the electrical conductivity of the nanotube due to the field effect, which thus acts as a channel region in this area of a field effect transistor can be used. Due to the ring-like structure of the gate-insulating layer, the electrical field generated as a result of the electrical potential of the third electrically conductive layer reaches the nanostructure sufficiently well, which is due to the fact that the gate electrode is electrically insulated on all sides by means of the gate-insulating layer.
- the middle layer can have an additional electrically conductive layer, which serves at least one additional electrically conductive layer as an additional gate electrode of the field effect transistor, with an additional ring structure made of an electrically insulating material as an additional along the through hole made in the additional electrically conductive layer Gate insulating region of the field effect transistor is arranged.
- the component designed as a field effect transistor can have one or more additional gate connections, as a result of which the controllability of the electrical resistance of the nanostructure is further improved.
- the possibility of providing additional electrically conductive middle layers as additional gate connections is based essentially on the fact that the electrically conductive layer or layers in the middle layer are sufficiently thin.
- the component according to the invention can have an additional field effect transistor, which is arranged above the field effect transistor.
- critical parameters such as the gate length of such a field effect transistor, are defined according to the invention not by means of a structuring process but by means of a deposition process. A much higher structural accuracy can be achieved with a deposition process than with a structuring process. For example, using the ALD method
- atomic layer deposition the thickness of a deposited layer down to the dimension of an atomic layer, ie down to a few angstroms accuracy.
- Field effect transistor of the component according to the invention can be connected to one another as an inverter circuit.
- the field effect transistor and the additional field effect transistor are designed as transistors with different conduction types, for example the field effect transistor as a transistor of the p-conduction type and the additional field effect transistor as a transistor of the n conduction type or vice versa.
- the first and / or the second electrically conductive layer of the component can have tantalum, tantalum nitride (TaN), titanium, titanium nitride (TiN), molybdenum (Mo), aluminum (Al) and / or a ferromagnetic material, or can have any layer stack from a combination of the specified materials
- the first and / or the second electrically conductive layer is made of ferromagnetic material such as iron, cobalt or nickel or of a suitable ferromagnetic alloy, in particular of a hard magnetic or a soft magnetic material
- the component for applications can be used in the "Spintronic".
- semiconductor technology is combined with magnetic effects.
- the spintronic uses, in addition to the electron charge in electricity transport, additionally or alternatively the spin of the electron.
- Applications in spintronic are particularly advantageous according to the invention if the nanostructure is designed as a carbon nanotube, since the charge transport through a carbon nanotube is spin-preserving over sufficiently large dimensions, that is to say takes place without a spin flip.
- ferromagnetic first and second electrically conductive layers for example an MRAM memory cell (“magnetic random access memory”) comes into consideration.
- MRAM memory cell magnetic random access memory
- the vertically integrated component in the embodiment of the vertically integrated component according to the invention as a field effect transistor, it can be set up, for example, as a switching transistor of a DRAM memory cell, in which case a further stack capacitor is to be formed.
- Field effect transistor is designed as a charge storage layer (e.g. as an ONO layer), the storage and deletion of information in this case being carried out by injecting electrons or holes into the charge storage layer.
- a charge storage layer e.g. as an ONO layer
- the third and / or the additional electrically conductive layer preferably has polysilicon, tantalum, titanium, niobium and / or aluminum.
- the dielectric material of the middle layer can be one or a combination of the materials silicon dioxide (Si0 2 ), silicon nitride (Si 3 N 4 ) or silicon dioxide doped with potassium ions.
- Silicon dioxide doped with potassium ions has the particular advantage that potassium ions can be expelled from such a dielectric layer by means of heating and can therefore serve as a dopant for a surrounding material.
- the nanostructure can be a nanotube, a bundle of nanotubes or a nanorod (also called nanowire).
- the nanostructure can be semiconducting.
- the nanorod can contain silicon, germanium, indium phosphide, gallium nitride, gallium arsenide, zirconium oxide and / or a metal.
- the nanotube can be a carbon nanotube, a carbon-boron nanotube, a carbon-nitrogen nanotube, a carbon-boron-nitrogen nanotube, a tungsten sulfide nanotube or a chalcogenide nanotube.
- the nanostructure is a
- Carbon nanotube, iron, cobalt and / or nickel can be used as catalyst material.
- the nanostructure is a gallium arsenide nanorod, gold is preferably used as the catalyst material.
- the portion of the through hole that is free of the nanostructure can be at least partially filled with an electrically insulating spacer structure.
- the component can be formed exclusively from dielectric material, metallic material and the material of the nanostructure. Furthermore, the component can be formed on and / or in a substrate made of polycrystalline or amorphous material.
- the component according to the invention can only consist of electrically conductive material, dielectric material and material of the nanostructure (preferably a carbon nanotube).
- the component can be manufactured without expensive semiconductor technology processes.
- Another important advantage in this connection is that a polycrystalline or amorphous material, that is to say a non-single-crystalline material, can be used as the substrate in order to produce the component. It is therefore an expensive, single-crystalline substrate for the production of the component
- any starting substrate can be used according to the invention (e.g. glass).
- the middle layer which is dielectric Partial layers and additional conductive layers (for example made of polysilicon, tantalum, titanium, niobium, aluminum) can be deposited.
- a vertical through-hole with a typical diameter between 0.4nm and 100nm and with a typical length between O.Ol ⁇ m and 3 ⁇ m can then be made in the middle layer.
- the dielectric and electrically conductive partial layers of the middle layer are structured.
- the third electrically conductive layer interspersed with the through hole is further oxidized along the circumference of the through hole, for example a third electrically conductive layer made of polysilicon material can be oxidized, so that electrically insulating silicon dioxide material is electrically in a surrounding area of the through hole in the third Is formed conductive layer, which silicon dioxide material can be used as a gate insulating layer.
- an annular, gate-insulating layer is formed using the chemical vapor deposition (CVD) method or the atomic layer deposition (ALD) method, in that the through-hole is uniformly coated with an electrically insulating wall layer is coated.
- the nanostructure can then be formed in the through hole, for example a carbon nanotube is grown on a catalyst material deposited on the first electrically conductive layer.
- the catalyst material can either be deposited as a layer on the first electrically conductive layer or, after forming the gate insulating layer using the "electroless deposition" method, can be deposited on the surface of the first electrically conductive layer in the through hole.
- an intermediate region can be sealed between the through hole and the nanostructure, for example by introducing silicon dioxide material into at least part of the through hole using a CVD or spin-on method. Excess material can optionally be etched back to expose the nanostructure, and the second electrically conductive Layer can be formed on the surface of the layer sequence and optionally structured.
- FIG. 1A shows a cross-sectional view of a component according to a first exemplary embodiment of the invention
- FIG. IB shows an enlarged cross-sectional view, taken along the section line A-A from FIG. 1A, of the component shown in FIG. 1A according to the first exemplary embodiment of the invention
- FIG. 2 shows a cross-sectional view of a component according to a second exemplary embodiment of the invention
- FIG. 3 shows a component arrangement according to a first exemplary embodiment of the invention
- FIG. 4A shows a cross-sectional view of a component arrangement according to a second exemplary embodiment of the invention
- FIG. 4B shows an equivalent circuit of the component arrangement shown in FIG. 4A according to the second exemplary embodiment of the invention
- FIG. 5 shows a cross-sectional view of a component according to a third exemplary embodiment of the invention.
- a vertically integrated component 100 according to a first exemplary embodiment of the invention is described below with reference to FIGS. 1A, 1B.
- the vertically integrated component 100 shown in FIG. 1A has a first electrically conductive layer 101, a middle layer 102 partially formed from dielectric material on the first electrically conductive layer 101 and a second electrically conductive layer 103 on the middle layer 102. Furthermore provided is a carbon nanotube 104 integrated into a through-hole 108 made in the middle layer 102, which has a first end section 104a coupled to the electrically conductive layer 101 and a second end section 104b coupled to the second electrically conductive layer 103.
- Catalyst material 107 for catalyzing the formation of the carbon nanotube 104 is arranged between the first conductive layer 101 and the carbon nanotube 104.
- the middle layer 102 is divided into two dielectric sublayers 102a, 102b arranged one above the other.
- a third electrically conductive layer 105 is arranged between the first middle sublayer 102a and the second middle sublayer 102b, the thickness of which is substantially less than the thickness of both dielectric sublayers 102a, 102b.
- the first electrically conductive layer 101 and the second electrically conductive layer 103 are made of tantalum nitride, the third electrically conductive layer 105 is made of polysilicon, the dielectric material of the middle layer 102 is silicon dioxide or silicon dioxide containing potassium ions.
- the vertically integrated Component 100 is the nanostructure a carbon nanotube 104 and the catalyst material 107 is an alloy of iron, cobalt and nickel. It is known that this combination of materials has an advantageous catalytic effect on the formation of a carbon nanotube.
- the vertically integrated component 100 is designed as a field effect transistor, in which component 100 the first end portion 104a of the carbon nanotube 104 serves as the first source / drain region and the second end portion 104b of the carbon nanotube 104 serves as the second source / drain region, and in of the third electrically conductive layer 105, which serves as the gate electrode of the field effect transistor, a ring structure 106 made of an electrically insulating material is arranged as a gate-insulating region of the field transistor along the through hole 108 made therein.
- the vertically integrated component 100 shown in FIG. 1A fulfills the functionality of a field effect transistor.
- the conductivity of the carbon nanotube 104 can be influenced characteristically by applying a suitable electrical voltage to the third electrically conductive layer 105, which has the functionality of a gate electrode.
- the conductivity of the carbon nanotube 104 can be influenced characteristically in a spatially sharply defined central region 104c.
- the central area 104c clearly functions as a channel area.
- the third electrically conductive layer 105 is provided according to the invention in a sufficiently thin manner, an electrical voltage is applied to the third electrically conductive layer 105 due to an electrostatic peak effect in an adjacent one
- the electrical conductivity of the carbon tube 104 in the central region 104c adjoining the third electrically conductive layer 105 can be controlled very precisely by means of the field effect.
- FIG. 1B shows an enlarged cross-sectional view, taken along the section line A-A from FIG. 1A, of the vertically integrated component 100 from FIG. 1A.
- the carbon nanotube 104 is contained in the through hole 108.
- the semiconducting carbon nanotube 104 is decoupled from the third electrically conductive layer 105 by means of the electrically insulating ring structure 106.
- the strength of an electrical current flow between the first and second electrically conductive layers 101, 103 functioning as source / drain connections depends on whether or not an electrical voltage is applied to the gate electrode 105.
- the vertically integrated component 100 therefore fulfills the function of a field effect transistor.
- the first electrically conductive layer 101 is formed by applying titanium nitride, for example using a CVD method (“chemical vapor deposition”).
- a first middle sub-layer 102a is formed by depositing silicon dioxide material.
- the third electrically conductive layer 105 is formed on the first middle sublayer 102a by depositing polysilicon material. Again, this can be done using a CVD process.
- second middle sub-layer 102b is formed by depositing silicon dioxide. Both the silicon dioxide material of the first middle sublayer 102a and the silicon dioxide material of the second middle sublayer 102b can be made according to a modified TEOS
- tetra-ethyl-orthosilicate are formed such that the middle sub-layers 102a, 102b can each have potassium doping atoms.
- the middle layer 102 which is at least partially formed on dielectric material, is formed.
- the through hole 108 is made in the middle layer 102. This is done using a lithography and an etching process.
- the etching method is preferably selected in such a way (in particular by specifying the etchant) that the etching process on the electrically conductive layer 101 stops.
- the electrically insulating ring structure 106 is formed from silicon dioxide by means of thermal oxidation of the third electrically conductive layer 105 made of polysilicon material.
- the catalyst material 107 made of iron, cobalt and nickel is deposited in the through hole 108 and on the first electrically conductive layer 101.
- This can be implemented using a vapor deposition, sputtering, electro or electroless deposition method.
- electroless deposition a conductive material is deposited autocatalytically from a solution containing the material to be deposited without applying an electrical current to certain surface areas of a layer sequence.
- the carbon nanotube 104 is then grown in the through hole 108, the first end section 104 a being coupled to the first conductive structure 101.
- a carbon nanotube is formed using a CVD process in which a methane / hydrogen mixture is introduced as a carbon source into the process chamber. In this way, a p-doped carbon nanotube 104 is often formed.
- the possibly introduced potassium ions from the first can be tempered
- Middle sublayer 102a and the second middle sublayer 102b are expelled, these potassium ions diffuse into the previously p-doped carbon nanotube 104 and act as an n-dopant.
- the initially p-doped carbon nanotube 104 is converted into a carbon nanotube 104 of the n-conduction type.
- the second electrically conductive layer 103 is formed on the middle layer 102 and coupled to the second end section 104b of the carbon nanotube 104, as a result of which the vertically integrated component 100 shown in FIGS. 1A, 1B is obtained.
- a vertically integrated component 200 designed as a field effect transistor is described below with reference to FIG. Only the differences between the vertically integrated component 200 and the vertically integrated component 100 are described below.
- the electrically insulating ring structure 106 from FIG. 1A is not provided.
- the through hole 108 of the vertically integrated component 200 is provided with a continuous electrically insulating edge coating 201, which perceives the functionality of a gate insulating layer.
- Component 200 from FIG. 2 has the function of a
- Voltage to the third electrically conductive layer 105 is controlled. This takes place using the field effect, for which a partial area of the electrically insulating edge coating 201 surrounding the central area 104c of the carbon nanotube 104 is essential.
- the through hole 108 is coated uniformly with an electrically insulating material using the CVD method, thereby electrically insulating edge coating 201 is formed.
- This can additionally fulfill the function of a spacer or a guide for the carbon nanotube 104.
- a component arrangement 300 according to a first exemplary embodiment of the invention is described below with reference to FIG.
- the component arrangement 300 has two components arranged one above the other, each of which is configured similarly to the vertically integrated component 100.
- the component arrangement 300 clearly has a field effect transistor, formed by the vertically integrated component 100, which is arranged above another field effect transistor.
- the additional field effect transistor which is arranged below the vertically integrated component 100, has a common electrically conductive layer 301 together with the vertically integrated component 100, in other words, in the component arrangement 300, the first electrically conductive layer 101 from FIG. lA and the upper electrically conductive layer of the underlying
- the field effect transistor additionally provided in the component arrangement 300 compared to the vertically integrated component 100 has an additional first electrically conductive layer 303, on which an additional middle layer 302 is formed. This is formed from a first middle sublayer 302a, a second middle sublayer 302b and an additional third electrically conductive layer 305, which is arranged between the middle sublayers 302a, 302b.
- the first middle sublayer 302a and the second middle sublayer 302b of the additional middle layer 302 are made of silicon dioxide material.
- the additional third electrically conductive layer 305 is designed like the electrically conductive layer 105. Furthermore, an additional through hole 308 of the lower region of the component arrangement 300 according to FIG.
- FIG. 3 is in a region in which the through hole 308 is the additional third electrically conductive layer 305 penetrates, an additional electrically insulating ring structure 306 arranged.
- An additional carbon nanotube 304 has been grown on additional catalyst material 307, the lower end section 304a of which is coupled to the additional catalyst material 307 according to FIG. 3, and the upper end section 304b of which is coupled to the common electrically conductive layer 301.
- the nanostructure in the component arrangement 300 is clearly formed from the carbon nanotube 104 and the additional carbon nanotube 304. Subareas of
- the nanostructure namely the carbon nanotube 104 on the one hand and the additional carbon nanotube 304 on the other hand, have a different electrical conductivity.
- the carbon nanotube 104 of the nanostructure is (as described above) doped with charge carriers of the n-type, and the additional carbon nanotube 304 of the nanostructure is doped with p-type charge carriers.
- the different doping of the carbon nanotubes 104, 304 is based on the fact that the carbon nanotube 104 is surrounded by silicon dioxide material 102a, 102b doped with potassium ions, whereas the additional carbon nanotube 304 is surrounded by pure silicon dioxide material 302a, 302b.
- the potassium material is driven out of the layers 102a, 102b and diffuses into the carbon nanotube 104, which is thereby n-doped.
- the upper field effect transistor of the component arrangement 300 according to FIG. 3 fulfills the functionality of an n-MOSFET, whereas the lower field effect transistor of the component arrangement 300 according to FIG. 3 fulfills the functionality of a p-MOSFET.
- the component arrangement 300 is produced by first forming the lower field-effect transistor in accordance with FIG. 3, analogously to that described above with reference to FIG. 1A.
- the first middle sublayer 302a and the second middle sublayer 302b are each made of pure potassium doping atoms Silicon dioxide manufactured. This creates the lower field-effect transistor of the component arrangement 300, which has the additional carbon nanotube 304 of the p-conduction type.
- a vertically integrated component 100, as shown in FIG. 1A, is subsequently produced on this layer sequence.
- both the first middle sublayer 102a and the second middle sublayer 102b are produced from silicon dioxide material doped with potassium material, so that the carbon nanotube 104 obtained as a p-doped carbon nanotube in the CVD production process faces upwards described annealing is n-doped.
- the component arrangement 300 provides an n-MOS transistor on a p-MOS transistor, therefore the component arrangement 300 can be used as a CMOS component.
- CMOS technology complementary metal oxide semiconductor
- alternating n-channel and p-channel MOSFETs are used as switches.
- CMOS devices are used in many highly integrated circuits, for example, many modern microprocessors are built in this technology.
- a component arrangement 400 according to a second exemplary embodiment of the invention is described below with reference to FIGS. 4A, 4B.
- a p-MOS field-effect transistor 401 formed by the lower layer sequence according to FIG. 4 A and an n-MOS field transistor 402, formed by the upper layer sequence of the component arrangement 400 according to FIG interconnected as an inverter circuit.
- Field effect transistor 402 the electrical ground potential V ss 403 created. Furthermore, the electrical potential of a supply voltage Vdd 404 is applied to the additional first electrically conductive layer 303 of the p-MOS field-effect transistor 401.
- the third electrically conductive layer 105 and the additional third electrically conductive layer 305 are coupled to an input 405 of the CMOS inverter.
- the common electrically conductive layer 301 is coupled to an output 406 of the CMOS inverter.
- FIG. 4B shows an equivalent circuit 410 of the component arrangement 400, which component arrangement 400 is connected as a CMOS inverter.
- the input 405 is coupled to the gate regions of the p-MOS field-effect transistor 401 and the n-MOS field-effect transistor 402, that is to say to the components of the component arrangement 400 functioning as the respective gate electrode, namely to the third electrically conductive layer 105 and with the additional third electrically conductive layer 305.
- the second electrically conductive layer 103 of the n-MOS field-effect transistor 402 serves as the first source / drain connection of the n-MOS field-effect transistor 402, and is to the first electrically conductive layer 103 therefore the electrical ground potential V SS 403 applied.
- a second source / drain connection of the n-MOS field-effect transistor 402 and a first source / drain connection of the p-MOS field-effect transistor 401 are jointly formed as a common electrically conductive layer 301 and connected to the output 406 as the CMOS Inverter connected component arrangement 410 coupled.
- a second source / drain connection of the p-MOS field-effect transistor 401 is formed by the additional electrically conductive layer 303, to which the electrical potential of the supply voltage V d 404 is applied.
- a vertically integrated component 500 according to a third preferred exemplary embodiment of the invention is described below with reference to FIG.
- the middle layer 501 of the vertically integrated component 500 has, in addition to the first middle sublayer 102a made of potassium-doped silicon dioxide, the second middle sublayer 102b made of potassium doped silicon dioxide, the third electrically conductive layer 105 made of polysilicon and the electrically insulating ring structure 106 a third middle sublayer 501a made of silicon nitride, which is arranged between the third electrically conductive layer 105 and a fourth electrically conductive layer 502.
- An additional electrically insulating ring structure 503 is located in a boundary area between the through hole 108 and the fourth electrically conductive layer 502 arranged.
- the fourth electrically conductive layer 502 is made of polysilicon material and the fourth electrically insulating ring structure 503 is made of silicon dioxide material.
- the vertically integrated component 500 represents a field effect transistor with two gate electrodes 105, 502.
- a field effect transistor with a plurality of gate connections can be advantageous in order to improve the electrical conductivity of the
- a vertically integrated component is created according to the invention, which is optionally available as
- CMOS component inverter and field effect transistor with multiple gate electrodes can be used.
- a large number of more complex circuits can be constructed or formed from these basic components, for example logic gates and further complex circuit arrangements. Due to the vertical orientation, the individual components of the invention can be formed one above the other in any way, and can also be formed side by side.
Abstract
The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer (101), a mid layer (102), partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer (103) on the mid layer and a nanostructure (104) integrated in a through hole introduced in the mid layer with a first end section coupled to the first electrical conducting layer and a second end section coupled to the second electrical conducting layer. The mid layer comprises a third electrical conducting layer (105) between two adjacent dielectric partial layers (102a, 102b) the thickness of which is less than the thickness of at least one of the dielectric partial layers.
Description
BesehreibungBesehreibung
Vertikal integriertes Bauelement, Bauelement-Anordnung und Verfahren zum Herstellen eines vertikal integrierten BauelementsVertically integrated component, component arrangement and method for producing a vertically integrated component
Die Erfindung betrifft ein vertikal integriertes Bauelement, eine Bauelement-Anordnung und ein Verfahren zum Herstellen eines vertikal integrierten Bauelements .The invention relates to a vertically integrated component, a component arrangement and a method for producing a vertically integrated component.
Die herkömmliche Silizium-Mikroelektronik wird bei weiter voranschreitender Verkleinerung an ihre Grenzen stoßen. Insbesondere die Entwicklung zunehmend kleinerer und dichter angeordneter Transistoren von mittlerweile mehreren hundert Millionen Transistoren pro Chip wird in den nächsten zehn Jahren prinzipiellen physikalischen Problemen und Begrenzungen ausgesetzt sein. Wenn Strukturabmessungen von ungefähr 80nm unterschritten werden, werden die Bauelemente durch Quanteneffekte störend beeinflusst und unterhalb von Dimensionen von etwa 30nm dominiert. Auch führt die zunehmende Integrationsdichte der Bauelemente auf einem Chip zu einem dramatischen Anstieg der Abwärme.Conventional silicon microelectronics will reach its limits as the scale continues to decrease. In particular, the development of increasingly smaller and more densely arranged transistors, which now has several hundred million transistors per chip, will be exposed to fundamental physical problems and limitations in the next ten years. If the structural dimensions fall below approximately 80 nm, the components are disrupted by quantum effects and dominated below dimensions of approximately 30 nm. The increasing integration density of the components on a chip also leads to a dramatic increase in waste heat.
Als mögliche Nachfolgetechnik der herkömmlichen Halbleiterelektronik sind NanoStrukturen wie beispielsweise Nanoröhren, insbesondere KohlenstoffnanorÖhren, und Nanostäbchen, auch Nanodrähte genannt, bekannt.Nano structures such as, for example, nanotubes, in particular carbon nanotubes, and nanorods, also called nanowires, are known as possible successors to conventional semiconductor electronics.
Einen Überblick über die Technologie der Kohlens of nanoröhren gibt beispielsweise [1] . EineFor example, an overview of the technology of the Kohlens of nanotubes [1]. A
Kohlenstoffnanoröhre ist eine einwandige oder mehrwandige röhrenartige Kohlenstoff erbindung. Bei mehrwandigen Nanoröhren ist mindestens eine innere Nanoröhre von einer äußeren Nanoröhre koaxial umgeben. Einwandige Nanoröhren weisen typischerweise Durchmesser von Inm auf, die Länge einer Nanoröhre kann mehrere Hundert niti betragen. Die Enden
einer Nanoröhre sind häufig mit jeweils einem halben Fulleren-Molekül abgeschlossen. Nanoröhren können hergestellt werden, indem auf einem Substrat eine Katalysatormaterial- Schicht, beispielsweise aus Eisen, Kobalt oder Nickel, abgeschieden wird und auf dieser Katalysatormaterial-Schicht unter Verwendung eines CVD-Verfahrens ("chemical vapour deposition") mittels Einleitens eines kohlenstoffhaltigen Materials (beispielsweise Azetylen) in die Verfahrenskammer Kohlenstoffnanoröhren auf der Katalysatormaterial-Schicht aufgewachsen werden. Aufgrund der guten elektrischenCarbon nanotube is a single-walled or multi-walled tubular carbon compound. In multi-walled nanotubes, at least one inner nanotube is coaxially surrounded by an outer nanotube. Single-walled nanotubes typically have a diameter of Inm, the length of a nanotube can be several hundred niti. The ends of a nanotube are often terminated with half a fullerene molecule. Nanotubes can be produced by depositing a catalyst material layer, for example made of iron, cobalt or nickel, on a substrate and on this catalyst material layer using a chemical vapor deposition (CVD) process by introducing a carbon-containing material (for example Acetylene) are grown in the process chamber carbon nanotubes on the catalyst material layer. Because of the good electrical
Leitfähigkeit von Kohlenstoffnanoröhren sowie aufgrund der Einstellbarkeit dieser Leitfähigkeit, beispielsweise mittels Anlegens eines externen elektrischen Feldes oder mittels Dotierens der Nanoröhren beispielsweise mit Kalium, eignen sich Nanoröhren für eine große Zahl von Anwendungen, insbesondere in der elektrischen Kopplungstechnik in integrierten Schaltkreisen, für Bauelemente in der Mikroelektronik sowie als Elektronenemitter.Conductivity of carbon nanotubes and due to the adjustability of this conductivity, for example by applying an external electric field or by doping the nanotubes with potassium, for example, nanotubes are suitable for a large number of applications, in particular in electrical coupling technology in integrated circuits, for components in microelectronics as well as an electron emitter.
Für viele integrierte Bauelemente in der Silizium- Mikroelektronik werden Feldeffekttransistoren benötigt. Zum Ausbilden eines solchen Feldeffekttransistors kann eine Kohlenstoffnanoröhre verwendet werden, wodurch ein sogenannter CNT-FET ( " carbon nanotube field effect transistor") gebildet wird. Hierfür wird beispielsweise eine Nanoröhre auf einer dielektrischen Schicht auf einem leitfähigen Substrat planar ausgebildet und kontaktiert. Die Leitfähigkeit der Kohlenstoffnanoröhre wird über eine geeignete an dem leitfähigen Substrat angelegte elektrische Spannung gesteuert, so dass der elektrische Stromfluss durch die Nanoröhre, anschaulich der elektrische Stromfluss zwischen den Source-/Drain-Anschlüssen des CNT-FETs, mittels Anlegens einer Spannung an das leitfähige Substrat steuerbar ist.
Ein Verfahren zum Ausbilden eines Feldeffekttransistors unter Verwendung einer Kohlenstoffnanoröhre ist beispielsweise in [2] beschrieben. Gemäß dem in [2] beschriebenen Verfahren wird auf einem Silizium-Substrat zunächst eine Siliziumdioxid-Schicht ausgebildet und auf dieser werden Kontaktierungs-Pads ausgebildet. Dann wird eine Kohlenstoffnanoröhre zwischen zwei Kontaktierungs-Pads aufgebracht und mit den Kontaktierungs-Pads kontaktiert, wobei die Leitfähigkeit der Kohlenstoffnanoröhre mittels Anlegens einer Spannung an das Silizium-Substrat steuerbar ist. Die Größe des elektrischen Stromflusses zwischen den beiden Endabschnitten einer Kohlenstoffnanoröhre ist bei einer vorgegebenen elektrischen Spannung von der Leitfähigkeit der Kohlenstoff anoröhre abhängig und daher mittels der elektrischen Spannung an dem Silizium-Substrat steuerbar.Field effect transistors are required for many integrated components in silicon microelectronics. A carbon nanotube can be used to form such a field effect transistor, as a result of which a so-called CNT-FET (“carbon nanotube field effect transistor”) is formed. For this purpose, for example, a nanotube is planarly formed and contacted on a dielectric layer on a conductive substrate. The conductivity of the carbon nanotube is controlled via a suitable electrical voltage applied to the conductive substrate, so that the electrical current flow through the nanotube, clearly the electrical current flow between the source / drain connections of the CNT-FET, by applying a voltage to the conductive one Substrate is controllable. A method for forming a field effect transistor using a carbon nanotube is described, for example, in [2]. According to the method described in [2], a silicon dioxide layer is first formed on a silicon substrate and contact pads are formed thereon. A carbon nanotube is then applied between two contacting pads and contacted with the contacting pads, the conductivity of the carbon nanotube being controllable by applying a voltage to the silicon substrate. The size of the electrical current flow between the two end sections of a carbon nanotube is dependent on the conductivity of the carbon anotube at a given electrical voltage and can therefore be controlled by means of the electrical voltage on the silicon substrate.
Ferner ist aus [2] bekannt, eine halbleitende Kohlenstoffnanoröhre wahlweise des p-Leitungstyps oder des n- Leitungstyps herzustellen. Beim herkömmlichen Ausbilden einer Kohlenstoffnanoröhre wird diese häufig im p-Leitungszustand erhalten. Mittels Temperns im Vakuum oder mittels Dotierens mit Kalium-Ionen kann eine Kohlenstoffnanoröhre des p- Leitungstyps in eine Kohlenstoffnanoröhre des n-Leitungstyps umgewandelt werden.Furthermore, it is known from [2] to produce a semiconducting carbon nanotube of either the p-type or the n-type. In the conventional formation of a carbon nanotube, it is often obtained in the p-conduction state. A p-type carbon nanotube can be converted into an n-type carbon nanotube by annealing in a vacuum or by doping with potassium ions.
Allerdings weist das aus [2] bekannte Verfahren den Nachteil auf, dass lediglich eine Herstellung planarer, horizontal orientierter Nanoröhren auf einem Substrat ermöglicht ist. Ein Kohlenstoffnanoröhren-Feldeffekttransistor mit einer horizontal auf einem Substrat ausgebildeten Nanoröhre weist jedoch den Nachteil auf, dass der Platzbedarf eines solchen Bauelements auf der Oberfläche eines Substrats groß ist, so dass die Integrationsdichte von Bauelementen, beispielsweise Kohlenstoffnanoröhren-Feldeffekttransistor, auf einem Substrat gering ist.
Alternativ zu Nanoröhren, insbesondere zuHowever, the method known from [2] has the disadvantage that it is only possible to produce planar, horizontally oriented nanotubes on a substrate. However, a carbon nanotube field effect transistor with a nanotube formed horizontally on a substrate has the disadvantage that the space requirement of such a component on the surface of a substrate is large, so that the integration density of components, for example carbon nanotube field effect transistor, on a substrate is low. As an alternative to nanotubes, especially to
Kohlenstoffnanoröhren, werden Nanostäbchen, auch Nanodrähte genannt, als Nanostrukturen für einen integrierten Schaltkreis verwendet. Beispielsweise ist aus [3] bekannt, ein Büschel von vertikalen Zinkoxid-Nanodrähten auf einem Gold-Katalysator, der auf einem Saphir-Substrat aufgebracht ist, auszubilden. Auf diese Weise können freistehende Zinkoxid-Nanodrähte mit Durchmessern von ungefähr 40nm bis 150nm hergestellt werden, mit einer Dichte von ungefähr 103 Drähten pro cm2. Gemäß dem aus [3] bekannten Konzept werden Büschel von Zinkoxid-Nanodrähten als Laserkomponenten verwendet .Carbon nanotubes, nanorods, also called nanowires, are used as nanostructures for an integrated circuit. For example, it is known from [3] to form a tuft of vertical zinc oxide nanowires on a gold catalyst which is applied to a sapphire substrate. In this way, free-standing zinc oxide nanowires with diameters of approximately 40 nm to 150 nm can be produced, with a density of approximately 10 3 wires per cm 2 . According to the concept known from [3], tufts of zinc oxide nanowires are used as laser components.
Ferner ist aus [4] bekannt, Feldeffekttransistoren und logische Gatter aus horizontalen, auf einerIt is also known from [4], field effect transistors and logic gates from horizontal, on a
Substratoberfläche gebildeten, gekreuzten Nanodrähten aus p- dotiertem Silizium und n-dotiertem Galliumnitrid herzustellen.Cross-formed nanowires made of p-doped silicon and n-doped gallium nitride.
Allerdings werden die Nanodrähte gemäß [4] nur in horizontaler Richtung auf einer Substratoberfläche planar ausgebildet und kontaktiert. Da dadurch die Dimension eines erhaltenen Bauelements durch die Länge einer Nanostruktur (in der Größenordnung Mikrometer) bestimmt ist, läuft das aus [4] bekannte Verfahren dem Bedürfnis nach einer fortschreitenden Miniaturisierung zuwider.However, the nanowires according to [4] are only planarly formed and contacted in the horizontal direction on a substrate surface. Since the dimension of a component obtained is determined by the length of a nanostructure (on the order of micrometers), the method known from [4] runs counter to the need for progressive miniaturization.
Aus [5] ist bekannt, in eine dicke Gate-Elektroden-Schicht ein Durchgangsloch einzubringen und in diesem ein vertikales Nanoelement aufzuwachsen. Dadurch wird ein vertikaler Feldeffekttransistor mit dem Nanoelement als Kanal-Bereich erhalten, wobei die elektrische Leitfähigkeit des Kanal- Bereichs mittels des das Nanoelement entlang annähernd seiner gesamten LängserStreckung umgebenden Gate-Elektroden-Bereichs steuerbar ist.
[6] offenbart einen vertikalen nanodi ensionealen Transistor unter Verwendung von Kohlenstoffnanoröhren und ein Verfahren zum Herstellen dieses Transistors.It is known from [5] to make a through hole in a thick gate electrode layer and to grow a vertical nano-element in it. This results in a vertical field effect transistor with the nano-element as the channel region, the electrical conductivity of the channel region being controllable by means of the gate electrode region surrounding the nano-element along almost its entire longitudinal extent. [6] discloses a vertical nanodimensional transistor using carbon nanotubes and a method of manufacturing this transistor.
[7] offenbart ultrahochdichte Nanotransistoren unter Verwendung von selektiv aufgewachsenen vertikalen Kohlenstoffnanoröhren .[7] discloses ultra-high density nanotransistors using selectively grown vertical carbon nanotubes.
[8] offenbart ein elektronisches Bauelement mit einer elektrisch leitenden Verbindung aus Carbon-Nanoröhren und Verfahren zu seiner Herstellung.[8] discloses an electronic component with an electrically conductive connection made of carbon nanotubes and method for its production.
Der Erfindung liegt das Problem zugrunde, die Integrationsdichte von ausreichend präzise steuerbaren Bauelementen mit einer Nanostruktur zu erhöhen und empfindliche NanoStrukturen so vorzusehen, dass sie vor einer mechanischen Schädigung geschützt sind.The problem underlying the invention is to increase the integration density of sufficiently precisely controllable components with a nanostructure and to provide sensitive nano-structures in such a way that they are protected against mechanical damage.
Das Problem wird durch ein vertikal integriertes Bauelement, eine Bauelement-Anordnung und ein Verfahren zum Herstellen eines vertikal integrierten Bauelements mit den Merkmalen gemäß den unabhängigen Patentansprüchen gelöst.The problem is solved by a vertically integrated component, a component arrangement and a method for producing a vertically integrated component with the features according to the independent patent claims.
Erfindungsgemäß ist ein vertikal integriertes Bauelement mit einer ersten elektrisch leitfähigen Schicht, einer teilweise aus dielektrischem Material ausgebildeten Mittel-Schicht auf der ersten elektrisch leitfähigen Schicht und einer zweiten elektrisch leitfähigen Schicht auf der Mittel-Schicht geschaffen. Ferner ist eine in ein in die Mittel-Schicht eingebrachtes Durchgangsloch integrierte Nanostruktur mit einem ersten, mit der ersten elektrisch leitfähigen Schicht gekoppeltem Endabschnitt und mit einem zweiten, mit der zweiten elektrisch leitfähigen Schicht gekoppelten Endabschnitt bereitgestellt. Die Mittel-Schicht weist zwischen zwei benachbarten dielektrischen Teilschichten eine dritte elektrisch leitfähige Schicht auf, deren Dicke
geringer ist als die Dicke von zumindest einer der dielektrischen Teilschichten.According to the invention, a vertically integrated component is created with a first electrically conductive layer, a middle layer partially made of dielectric material on the first electrically conductive layer and a second electrically conductive layer on the middle layer. Furthermore, a nanostructure integrated in a through-hole made in the middle layer is provided with a first end section coupled to the first electrically conductive layer and with a second end section coupled to the second electrically conductive layer. The middle layer has a third electrically conductive layer, the thickness of which, between two adjacent dielectric sublayers is less than the thickness of at least one of the dielectric sub-layers.
Ferner ist erfindungsgemäß eine Bauelement-Anordnung mit mindestens zwei nebeneinander angeordneten und/oder mit mindestens zwei übereinander angeordneten Bauelementen mit den oben genannten Merkmalen bereitgestellt.Furthermore, the invention provides a component arrangement with at least two components arranged next to one another and / or with at least two components arranged one above the other with the above-mentioned features.
Gemäß dem Verfahren zum Herstellen des vertikal integrierten Bauelements wird eine erste elektrisch leitfähige Schicht ausgebildet, wird eine Mittel-Schicht teilweise aus dielektrischem Material ausgebildet und wird ein Durchgangsloch in die Mittel-Schicht eingebracht. Ferner wird in dem Durchgangsloch eine Nanostruktur mit einem ersten Endabschnitt und einem zweiten Endabschnitt ausgebildet, wobei der erste Endabschnitt mit der ersten elektrisch leitfähigen Schicht gekoppelt wird. Es wird eine zweite elektrisch leitfähige Schicht auf der Mittel-Schicht ausgebildet und mit dem zweiten Endabschnitt der Nanostruktur gekoppelt. Die Mittel-Schicht wird derart ausgebildet, dass zwischen zwei benachbarten dielektrischen Teilschichten eine dritte elektrisch leitfähige Schicht ausgebildet wird, deren Dicke geringer ist als die Dicke von zumindest einer der dielektrischen Teilschichten.According to the method for producing the vertically integrated component, a first electrically conductive layer is formed, a middle layer is partially formed from dielectric material and a through hole is made in the middle layer. Furthermore, a nanostructure having a first end section and a second end section is formed in the through hole, the first end section being coupled to the first electrically conductive layer. A second electrically conductive layer is formed on the middle layer and coupled to the second end section of the nanostructure. The middle layer is formed in such a way that a third electrically conductive layer is formed between two adjacent dielectric sublayers, the thickness of which is less than the thickness of at least one of the dielectric sublayers.
Eine Grundidee der Erfindung ist darin zu sehen, dass mittels der in der Mittelschicht enthaltenen ausreichend dünnen dritten elektrisch leitfähigen Schicht die elektrische Leitfähigkeit eines daran angrenzenden Bereichs der Nanostruktur sicher steuerbar ist. Somit kann das vertikal integrierte Bauelement als Feldeffekttransistor-ähnliches Bauelement betrieben werden, wobei die dritte elektrisch leitfähige Schicht in diesem Fall als Gate-Elektroden-Schicht dient, wohingegen die Nanostruktur anschaulich als Kanal- Bereich dient. Da die dritte elektrisch leitfähige Schicht erfindungsgemäß ausreichend dünn vorgesehen ist, bildet sich
bei Anlegen einer elektrischen Spannung an die dritte elektrisch leitfähige Schicht aufgrund eines elektrostatischen Spitzeneffekts in einem angrenzenden Umgebungsbereich der Nanostruktur ein besonders starkes elektrisches Feld aus, mit anderen Worten erfolgt eine Feldkonzentration. Mittels des Feldeffekts ist die elektrische Leitfähigkeit in dem an die dritte elektrisch leitfähige Schicht angrenzenden Bereich der Nanostruktur mit sehr hoher Genauigkeit steuerbar.A basic idea of the invention is to be seen in the fact that by means of the sufficiently thin third electrically conductive layer contained in the middle layer, the electrical conductivity of an adjacent region of the nanostructure can be controlled reliably. The vertically integrated component can thus be operated as a field-effect transistor-like component, the third electrically conductive layer serving in this case as a gate electrode layer, whereas the nanostructure clearly serves as a channel region. Since the third electrically conductive layer is provided sufficiently thin according to the invention, it forms when an electrical voltage is applied to the third electrically conductive layer due to an electrostatic peak effect in an adjacent surrounding area of the nanostructure, a particularly strong electric field is produced, in other words there is a field concentration. Using the field effect, the electrical conductivity in the region of the nanostructure adjacent to the third electrically conductive layer can be controlled with very high accuracy.
Ein weiterer Vorteil ist darin zu sehen, dass die geometrische Lage der dritten elektrisch leitfähigen Schicht innerhalb der Mittel-Schicht mittels eines Abscheideverfahrens, nicht mittels eines lithographischen Verfahrens, vorgebbar ist. Mittels eines Abscheide-VerfahrensAnother advantage can be seen in the fact that the geometrical position of the third electrically conductive layer within the middle layer can be predetermined by means of a deposition method, not by means of a lithographic method. By means of a separation process
(beispielsweise ALD, "Atomic Layer Deposition") kann die Dicke einer jeweiligen Schicht mit einer Genauigkeit von bis zu einer Atomlage, das heißt bis auf wenige Angström genau eingestellt werden. Die gewünschte Lage und Dicke der dritten elektrisch leitfähigen Schicht innerhalb der Mittelschicht ist somit erfindungsgemäß sehr exakt definierbar. Somit ist bei dem erfindungsgemäßen vertikal integrierten Bauelement in seiner Ausgestaltung als Feldeffekttransistor wahlweise ein sicheres Sperren bzw. ein sicheres Leiten des Kanal-Bereichs des Feldeffekttransistors ermöglicht, wobei der jeweils gewünschte Betriebszustand mittels Anlegens oder Nichtanlegens einer Spannung an die dritte elektrisch leitfähige Schicht einstellbar ist.(for example ALD, "Atomic Layer Deposition"), the thickness of a respective layer can be set with an accuracy of up to one atomic layer, that is to say to a few angstroms. The desired position and thickness of the third electrically conductive layer within the middle layer can thus be defined very precisely according to the invention. Thus, in the case of the vertically integrated component according to the invention in its design as a field effect transistor, safe blocking or safe conduction of the channel region of the field effect transistor is optionally made possible, the desired operating state in each case being adjustable by means of applying or not applying a voltage to the third electrically conductive layer.
Anschaulich ist erfindungsgemäß die Einstellbarkeit der elektrischen Leitfähigkeit der Nanoröhre gegenüber dem Stand der Technik dadurch verbessert, dass eine räumlich exakt definierte Stelle der Nanostruktur mittels eines räumlich lokalisierten elektrischen Feldes einer großen Amplitude beeinflusst wird, statt mit einer wenig spezifischen und
Undefinierten Steuerung der Leitfähigkeit von annähernd einer gesamten Nanostruktur, wie gemäß dem Stand der Technik.According to the invention, the adjustability of the electrical conductivity of the nanotube is clearly improved compared to the prior art in that a spatially precisely defined location of the nanostructure is influenced by means of a spatially localized electrical field of a large amplitude, instead of using a less specific and Undefined control of the conductivity of almost an entire nanostructure, as according to the prior art.
Erfindungsgemäß ist es ermöglicht, eine oder mehrere vertikal angeordnete Nanostrukturen, beispielsweiseAccording to the invention it is possible to use one or more vertically arranged nanostructures, for example
Kohlenstoffnanoröhren, in einem Durchgangsloch aufzuwachsen.Carbon nanotubes growing up in a through hole.
Ein Vorteil des erfindungsgemäßen vertikal integrierten Bauelements besteht in der Miniaturisierung des Bauelements bis in den Bereich lateraler Nanometer-Abmessungen, da der Oberflächenbedarf eines vertikal integrierten Bauelements prinzipiell nur durch die Querschnittsfläche der Nanostruktur begrenzt ist. Ferner ist erfindungsgemäß die häufig empfindliche Nanostruktur in einer isolierenden und schützenden Matrix aus dem dielektrischen Material der Mittel-Schicht eingebracht. Die räumliche Anordnung von Nanostrukturen unterschiedlicher vertikal integrierter Bauelemente einer erfindungsgemäßen Bauelement-Anordnung ist mittels Vorgebens einer räumlichen Anordnung von Durchgangslöchern realisierbar, in welchen die Nanostrukturen aufgewachsen werden, so dass eine geordnete Anordnung unterschiedlicher Nanostrukturen ermöglicht ist. Ferner ist das Vorhandensein eines kristallinen Substrats entbehrlich.An advantage of the vertically integrated component according to the invention is the miniaturization of the component down to the range of lateral nanometer dimensions, since the surface requirement of a vertically integrated component is in principle only limited by the cross-sectional area of the nanostructure. Furthermore, according to the invention, the often sensitive nanostructure is incorporated in an insulating and protective matrix made of the dielectric material of the middle layer. The spatial arrangement of nanostructures of different vertically integrated components of a component arrangement according to the invention can be realized by specifying a spatial arrangement of through holes in which the nanostructures are grown, so that an orderly arrangement of different nanostructures is made possible. Furthermore, the presence of a crystalline substrate is unnecessary.
Das Herstellen von Nanostrukturen, beispielsweiseThe manufacture of nanostructures, for example
Kohlenstoffnanoröhren in einem vertikalen Kontaktloch, ist technologisch mit vertretbarem Aufwand realisierbar. Ferner ist die Länge der Nanostruktur, beispielsweise einer Kohlenstoffnanoröhre, mittels Einsteilens der Dicke der Mittel-Schicht justierbar.Carbon nanotubes in a vertical contact hole can be technologically implemented with reasonable effort. Furthermore, the length of the nanostructure, for example a carbon nanotube, can be adjusted by dividing the thickness of the middle layer.
Bevorzugte Weiterbildungen der Erfindung ergeben sich aus den abhängigen Ansprüchen.Preferred developments of the invention result from the dependent claims.
Vorzugsweise ist zwischen der ersten leitfähigen Schicht und der Nanostruktur Katalysatormaterial zum Katalysieren des
Ausbildens der Nanostruktur angeordnet. Indem Katalysatormaterial räumlich definiert abgeschieden wird, kann das Aufwachsen der Nanostruktur räumlich vorgegeben werden. Das Katalysatormaterial kann beispielsweise lokalisiert in dem Durchgangsloch abgeschieden werden, alternativ kann zwischen der ersten elektrisch leitfähigen Schicht und der Mittel-Schicht eine Katalysatormaterial- Schicht ausgebildet werden, oder es kann bei bestimmten Anwendungen die erste leitfähige Schicht aus einem solchen Material hergestellt werden, dass die erste elektrisch leitfähige Schicht als Katalysator zum Katalysieren des Ausbildens der Nanostruktur verwendet werden kann. Die erste elektrisch leitfähige Schicht kann aus Eisen-Material hergestellt sein, und daher als Katalysator zum Aufwachsen von Kohlenstoffnanoröhren verwendet werden, daBetween the first conductive layer and the nanostructure there is preferably catalyst material for catalyzing the Forming the nanostructure arranged. By depositing catalyst material in a spatially defined manner, the growth of the nanostructure can be predetermined in space. The catalyst material can, for example, be deposited locally in the through hole, alternatively a catalyst material layer can be formed between the first electrically conductive layer and the middle layer, or, in certain applications, the first conductive layer can be produced from such a material that the first electrically conductive layer can be used as a catalyst for catalyzing the formation of the nanostructure. The first electrically conductive layer can be made of iron material and can therefore be used as a catalyst for growing carbon nanotubes
Kohlenstoffnanoröhren besonders gut auf Eisen-Material aufwachsen.Carbon nanotubes grow particularly well on iron material.
Bei dem Bauelement kann die dritte elektrisch leitfähige Schicht die Nanostruktur in einem Umgebungsbereich des ersten oder des zweiten Endabschnitts umgeben. Die dritte leitfähige Schicht kann funktioneil in eine erste und in eine zweite Teilschicht aufgesplittet werden, wobei die erste Teilschicht im Bereich der ersten leitfähigen Schicht und die zweite Teilschicht im Bereich der zweiten leitfähigen Schicht lokalisiert ist. Mit Hilfe dieser aufgesplitteten dritten leitfähigen Schicht ist es möglich, an beiden Endkontakten der Nanostruktur eine optimale Gate-Steuerung der in diesen Bereichen ausgebildeten Schottky-Barrieren auszuüben.In the component, the third electrically conductive layer can surround the nanostructure in a surrounding area of the first or the second end section. The third conductive layer can be functionally split into a first and a second partial layer, the first partial layer being located in the area of the first conductive layer and the second partial layer being located in the area of the second conductive layer. With the aid of this split third conductive layer, it is possible to perform optimal gate control of the Schottky barriers formed in these areas at both end contacts of the nanostructure.
Indem die dritte elektrisch leitfähige Schicht die Nanostruktur in einem Umgebungsbereich von einem der Endabschnitte der Nanostruktur, an dem diese an die erste oder die zweite elektrisch leitfähige Schicht angrenzt, umgeben ist, ist eine zusätzliche Verbesserung derIn that the third electrically conductive layer surrounds the nanostructure in a surrounding area from one of the end sections of the nanostructure at which it adjoins the first or the second electrically conductive layer, an additional improvement of the
Steuerbarkeit der elektrischen Leitfähigkeit der Nanoröhre
realisiert. Anschaulich ist zwischen der ersten elektrisch leitfähigen Schicht und dem ersten Endabschnitt der Nanostruktur sowie zwischen der zweiten elektrisch leitfähigen Schicht und dem zweiten Endabschnitt der Nanostruktur jeweils eine Schottky-Barriere gebildet, die auf die elektrische Leitfähigkeit der Nanostruktur in Abhängigkeit von einem möglicherweise angelegten elektrischen Feld besonders sensitiv ist und die sehr stark räumlich lokalisiert ist. Wird die dritte elektrisch leitfähige Schicht nahe des ersten oder des zweiten Endabschnitts ausgebildet, so kann mittels Anlegens einer elektrischen Spannung an die dritte elektrisch leitfähige Schicht die elektrische Leitfähigkeit der Nanostruktur besonders empfindlich eingestellt werden.Controllability of the electrical conductivity of the nanotube realized. Clearly, a Schottky barrier is formed between the first electrically conductive layer and the first end section of the nanostructure, and between the second electrically conductive layer and the second end section of the nanostructure is sensitive and is very spatially localized. If the third electrically conductive layer is formed near the first or the second end section, the electrical conductivity of the nanostructure can be set particularly sensitively by applying an electrical voltage to the third electrically conductive layer.
Die Dicke der dritten elektrisch leitfähigen Schicht kann geringer, vorzugsweise wesentlich geringer, sein als die Dicke von beiden dielektrischen Teilschichten. Vorzugsweise ist das Dickenverhältnis zwischen der ersten bzw. der zweiten dielektrischen Teilschicht einerseits und der dritten elektrisch leitfähigen Schicht mindestens drei, weiter vorzugsweise mindestens fünf, und noch weiter vorzugsweise mindestens zehn. Das erfindungsgemäße Bauelement kann ferner als Feldeffekttransistor ausgebildet sein, bei welchem Bauelement der erste Endabschnitt der Nanostruktur als erster Source-/ Drain-Bereich und der zweite Endabschnitt der Nanostruktur als zweiter Source-/Drain-Bereich dient und bei welchem Bauelement in der dritten elektrisch leitfähigen Schicht, die als Gate-Elektrode des Feldeffekttransistors dient, entlang des in die dritte elektrisch leitfähige Schicht eingebrachten Durchgangslochs eine Ringstruktur aus einem elektrisch isolierenden Material als Gate-isolierender Bereich des Feldeffekttransistors angeordnet ist.
Anschaulich kann in diesem Fall die elektrische Leitfähigkeit der Nanostruktur mittels Anlegens eines geeigneten elektrischen Potentials an die dritte elektrisch leitfähige Schicht gesteuert werden, da ein derartiges elektrisches Potential die elektrische Leitfähigkeit der Nanoröhre aufgrund des Feldeffekts charakteristisch beeinflusst, welche somit in diesem Bereich als Kanal-Bereich eines Feldeffekttransistors verwendet werden kann. Das infolge des elektrischen Potentials der dritten elektrisch leitfähigen Schicht erzeugte elektrische Feld greift aufgrund der ringartigen Struktur der Gate-isolierenden Schicht ausreichend gut auf die Nanostruktur über, was auf das allseitige Umschließen der mittels der Gate-isolierenden Schicht elektrisch isolierten Gate-Elektrode zurückzuführen ist.The thickness of the third electrically conductive layer can be less, preferably significantly less, than the thickness of both dielectric sublayers. The thickness ratio between the first or the second dielectric partial layer on the one hand and the third electrically conductive layer is preferably at least three, more preferably at least five, and even more preferably at least ten. The component according to the invention can also be designed as a field effect transistor, in which component the first end section of the nanostructure serves as the first source / drain region and the second end section of the nanostructure as the second source / drain region, and in which component in the third electrically conductive region Layer, which serves as the gate electrode of the field effect transistor, is arranged along the through hole made in the third electrically conductive layer, a ring structure made of an electrically insulating material as the gate insulating region of the field effect transistor. In this case, the electrical conductivity of the nanostructure can clearly be controlled by applying a suitable electrical potential to the third electrically conductive layer, since such an electrical potential characteristically influences the electrical conductivity of the nanotube due to the field effect, which thus acts as a channel region in this area of a field effect transistor can be used. Due to the ring-like structure of the gate-insulating layer, the electrical field generated as a result of the electrical potential of the third electrically conductive layer reaches the nanostructure sufficiently well, which is due to the fact that the gate electrode is electrically insulated on all sides by means of the gate-insulating layer.
Ferner kann die Mittel-Schicht eine zusätzliche elektrisch leitfähige Schicht aufweisen, welche mindestens eine zusätzliche elektrisch leitfähige Schicht als zusätzliche Gate-Elektrode des Feldeffekttransistors dient, wobei entlang des in der zusätzlichen elektrisch leitfähigen Schicht eingebrachten Durchgangslochs eine zusätzliche Ringstruktur aus einem elektrisch isolierenden Material als zusätzlicher Gate-isolierender Bereich des Feldeffekttransistors angeordnet ist.Furthermore, the middle layer can have an additional electrically conductive layer, which serves at least one additional electrically conductive layer as an additional gate electrode of the field effect transistor, with an additional ring structure made of an electrically insulating material as an additional along the through hole made in the additional electrically conductive layer Gate insulating region of the field effect transistor is arranged.
Mit anderen Worten kann das als Feldeffekttransistor ausgestaltete Bauelement einen zusätzlichen oder mehrere zusätzliche Gate-Anschlüsse aufweisen, wodurch die Steuerbarkeit des elektrischen Widerstands der Nanostruktur weiter verbessert ist. Die Möglichkeit des Vorsehens zusätzlicher elektrisch leitfähiger Mittel-Schichten als zusätzliche Gate-Anschlüsse beruht wesentlich auf der Tatsache, dass die elektrisch leitfähige Schicht oder Schichten in der Mittel-Schicht ausreichend dünn sind.
Ferner kann das erfindungsgemäße Bauelement einen zusätzlichen Feldeffekttransistor, welcher über dem Feldeffekttransistor angeordnet ist, aufweisen.In other words, the component designed as a field effect transistor can have one or more additional gate connections, as a result of which the controllability of the electrical resistance of the nanostructure is further improved. The possibility of providing additional electrically conductive middle layers as additional gate connections is based essentially on the fact that the electrically conductive layer or layers in the middle layer are sufficiently thin. Furthermore, the component according to the invention can have an additional field effect transistor, which is arranged above the field effect transistor.
Dies bedeutet, dass mehrere Feldeffekttransistoren in der beschriebenen Weise übereinander angeordnet werden können, und dies in im Prinzip beliebig vielen Schichten. Dadurch erhält man eine vertikale Stapelschicht von Feldeffekttransistoren, wodurch komplexere Schaltungen wie beispielsweise Logikgatter in vertikaler Integration ausgebildet werden können. Es ist anzumerken, dass die Verdrahtung des erfindungsgemäßen Bauelements in mehreren übereinander angeordneten Schichten nicht auf die Anwendung eines Feldeffekttransistors beschränkt ist. Es können Bauelemente gemäß unterschiedlichen Ausgestaltungen der Erfindung übereinander angeordnet werden, um komplexere Schaltkreise aufzubauen. Dadurch ist eine dreidimensionale Anordnung der Bauelemente realisiert und die Integrationsdichte von Bauelementen, bezogen auf die Oberfläche eines Substrats erhöht.This means that several field effect transistors can be arranged one above the other in the manner described, and in principle in any number of layers. This gives a vertical stacked layer of field effect transistors, whereby more complex circuits such as logic gates can be formed in vertical integration. It should be noted that the wiring of the component according to the invention in a plurality of layers arranged one above the other is not restricted to the use of a field effect transistor. Components according to different embodiments of the invention can be arranged one above the other in order to build up more complex circuits. This realizes a three-dimensional arrangement of the components and increases the integration density of components, based on the surface of a substrate.
Hinsichtlich der Ausgestaltung des erfindungsgemäßen Bauelements als Feldeffekttransistor ist ferner anzumerken, dass kritische Parameter, wie beispielsweise die Gate-Länge eines derartigen Feldeffekttransistors erfindungsgemäß nicht mittels eines Strukturierungs-, sondern mittels eines Abscheideprozesses definiert werden. Mit einem Abscheideprozess ist eine wesentlich höhere strukturelle Genauigkeit erreichbar als mit einem Strukturierungsprozess . Beispielsweise kann unter Verwendung des ALD-VerfahrensWith regard to the configuration of the component according to the invention as a field effect transistor, it should also be noted that critical parameters, such as the gate length of such a field effect transistor, are defined according to the invention not by means of a structuring process but by means of a deposition process. A much higher structural accuracy can be achieved with a deposition process than with a structuring process. For example, using the ALD method
("atomic layer deposition") die Dicke einer abgeschiedenen Schicht bis auf die Dimension einer Atomlage, d.h. bis auf wenige Angström Genauigkeit, eingestellt werden.
Der Feldeffekttransistor und der zusätzliche("atomic layer deposition") the thickness of a deposited layer down to the dimension of an atomic layer, ie down to a few angstroms accuracy. The field effect transistor and the additional one
Feldeffekttransistor des erfindungsgemäßen Bauelements können miteinander als Inverter-Schaltkreis verschaltet sein.Field effect transistor of the component according to the invention can be connected to one another as an inverter circuit.
In einem solchen Fall sind der Feldeffekttransistor und der zusätzliche Feldeffekttransistor als Transistoren mit unterschiedlichem Leitungstyp ausgebildet, beispielsweise der Feldeffekttransistor als Transistor des p-Leitungstyps und der zusätzliche Feldeffekttransistor als Transistor des n- Leitungstyps oder vice versa.In such a case, the field effect transistor and the additional field effect transistor are designed as transistors with different conduction types, for example the field effect transistor as a transistor of the p-conduction type and the additional field effect transistor as a transistor of the n conduction type or vice versa.
Die erste und/oder die zweite elektrisch leitfähige Schicht des Bauelements kann Tantal, Tantalnitrid (TaN) , Titan, Titannitrid (TiN) , Molybdän (Mo) , Aluminium (AI) und/oder ein ferromagnetisches Material aufweisen, bzw. kann ein beliebiger Schichtstapel aus einer Kombination der angegebenen Materialien seinThe first and / or the second electrically conductive layer of the component can have tantalum, tantalum nitride (TaN), titanium, titanium nitride (TiN), molybdenum (Mo), aluminum (Al) and / or a ferromagnetic material, or can have any layer stack from a combination of the specified materials
Insbesondere ist zu betonen, dass bei einer Ausgestaltung der ersten und/oder der zweiten elektrisch leitfähigen Schicht aus ferromagnetischem Material wie beispielsweise Eisen, Kobalt oder Nickel bzw. aus einer geeigneten ferromagnetisehen Legierung, insbesondere aus einem hartmagnetischen oder einem weichmagnetischen Material, das Bauelement für Anwendungen in der "Spintronic" verwendet werden kann. In dem technologischen Gebiet der Spintronic wird die Halbleitertechnologie mit magnetischen Effekten kombiniert. Mit anderen Worten werden bei der Spintronic neben der Elektronenladung beim Stromtransport zusätzlich oder alternativ der Spin des Elektrons verwendet. Anwendungen in der Spintronic sind erfindungsgemäß besonders dann vorteilhaft, wenn die Nanostruktur als Kohlenstoffnanoröhre ausgestaltet ist, da der Ladungstransport durch eine Kohlenstoffnanoröhre über ausreichend große Dimensionen Spin- erhaltend ist, d.h. ohne einen Spin-Flip erfolgt. Als mögliches Anwendungsgebiet des erfindungsgemäßen Bauelements
mit ferromagnetischen ersten und zweiten elektrisch leitfähigen Schichten kommt beispielsweise eine MRAM- Speicherzelle ("magnetic random access emory") in Betracht. Zu diesem Zweck ist es oft vorteilhaft, entweder die erste oder die zweite elektrisch leitfähige Schicht aus einem hartmagnetischem ferromagnetischem Material und die jeweils andere Schicht aus einem weichmagnetischem ferromagnetischem Material auszubilden.In particular, it should be emphasized that when the first and / or the second electrically conductive layer is made of ferromagnetic material such as iron, cobalt or nickel or of a suitable ferromagnetic alloy, in particular of a hard magnetic or a soft magnetic material, the component for applications can be used in the "Spintronic". In the technological field of Spintronic, semiconductor technology is combined with magnetic effects. In other words, the spintronic uses, in addition to the electron charge in electricity transport, additionally or alternatively the spin of the electron. Applications in spintronic are particularly advantageous according to the invention if the nanostructure is designed as a carbon nanotube, since the charge transport through a carbon nanotube is spin-preserving over sufficiently large dimensions, that is to say takes place without a spin flip. As a possible field of application of the component according to the invention With ferromagnetic first and second electrically conductive layers, for example an MRAM memory cell ("magnetic random access memory") comes into consideration. For this purpose, it is often advantageous to form either the first or the second electrically conductive layer from a hard magnetic ferromagnetic material and the respective other layer from a soft magnetic ferromagnetic material.
In der Ausgestaltung des erfindungsgemäßen vertikal integrierten Bauelements als Feldeffekttransistor kann dieser beispielsweise als Schalttransistor einer DRAM-Speicherzelle eingerichtet sein, wobei dann ein weiterer Stapelkondensator auszubilden ist. Auch ist eine Speicherzelle realisierbar, bei der die Gate-isolierende Schicht desIn the embodiment of the vertically integrated component according to the invention as a field effect transistor, it can be set up, for example, as a switching transistor of a DRAM memory cell, in which case a further stack capacitor is to be formed. A memory cell in which the gate-insulating layer of the
Feldeffekttransistors als Ladungsspeicherschicht (z.B. als ONO-Schicht) ausgeführt ist, wobei das Einspeichern und Löschen von Information in diesem Fall mittels Injizierens von Elektronen oder Löchern in die Ladungsspeicherschicht erfolgt.Field effect transistor is designed as a charge storage layer (e.g. as an ONO layer), the storage and deletion of information in this case being carried out by injecting electrons or holes into the charge storage layer.
Vorzugsweise weist die dritte und/oder die zusätzliche elektrisch leitfähige Schicht Polysiliziu , Tantal , Titan, Niob und/oder Aluminium auf .The third and / or the additional electrically conductive layer preferably has polysilicon, tantalum, titanium, niobium and / or aluminum.
Das dielektrische Material der Mittel-Schicht kann eines oder eine Kombination der Materialien Siliziumdioxid (Si02) , Siliziumnitrid (Si3N4) oder mit Kalium-Ionen dotiertes Siliziumdioxid sein.The dielectric material of the middle layer can be one or a combination of the materials silicon dioxide (Si0 2 ), silicon nitride (Si 3 N 4 ) or silicon dioxide doped with potassium ions.
Mit Kalium-Ionen dotiertes Siliziumdioxid weist insbesondere den Vorteil auf, das Kalium-Ionen aus einer derartigen dielektrischen Schicht mittels Erwärmens ausgetrieben werden können und daher als Dotierstoff eines umgebenden Materials dienen können.
Die Nanostruktur kann eine Nanoröhre, ein Bündel von Nanoröhren oder ein Nanostäbchen (auch Nanodraht genannt) sein.Silicon dioxide doped with potassium ions has the particular advantage that potassium ions can be expelled from such a dielectric layer by means of heating and can therefore serve as a dopant for a surrounding material. The nanostructure can be a nanotube, a bundle of nanotubes or a nanorod (also called nanowire).
Insbesondere kann die Nanostruktur halbleitend sein.In particular, the nanostructure can be semiconducting.
Insbesondere kann das Nanostäbchen Silizium, Germanium, Indiumphosphid, Galliumnitrid, Galliumarsenid, Zirkoniumoxid und/oder ein Metall aufweisen.In particular, the nanorod can contain silicon, germanium, indium phosphide, gallium nitride, gallium arsenide, zirconium oxide and / or a metal.
Die Nanoröhre kann eine Kohlenstoffnanoröhre, eine Kohlenstoff-Bor-Nanoröhre, eine Kohlenstoff-Stickstoff- Nanoröhre, eine Kohlenstoff-Bor-Stickstoff-Nanoröhre, eine Wolframsulfid-Nanoröhre oder eine Chalkogenid-Nanoröhre sein.The nanotube can be a carbon nanotube, a carbon-boron nanotube, a carbon-nitrogen nanotube, a carbon-boron-nitrogen nanotube, a tungsten sulfide nanotube or a chalcogenide nanotube.
In dem Fall, in dem die Nanostruktur eineIn the case where the nanostructure is a
Kohlenstoffnanoröhre ist, kann als Katalysatormaterial Eisen, Kobalt und/oder Nickel verwendet werden. In einem Fall, in dem die Nanostruktur ein Galliu arsenid-Nanostäbchen ist, wird als Katalysatormaterial vorzugsweise Gold verwendet.Carbon nanotube, iron, cobalt and / or nickel can be used as catalyst material. In a case where the nanostructure is a gallium arsenide nanorod, gold is preferably used as the catalyst material.
Derjenige Teilbereich des Durchgangslochs, der von der Nanostruktur frei ist, kann zumindest teilweise mit einer elektrisch isolierenden Abstandshalter-Struktur gefüllt sein.The portion of the through hole that is free of the nanostructure can be at least partially filled with an electrically insulating spacer structure.
In einem solchen Fall ist sichergestellt, dass die Nanostruktur in dem Durchgangsloch vor einer mechanischen oder elektrischen Schädigung geschützt ist.In such a case, it is ensured that the nanostructure in the through hole is protected against mechanical or electrical damage.
Das Bauelement kann ausschließlich aus dielektrischem Material, metallischem Material und dem Material der Nanostruktur gebildet sein. Ferner kann das Bauelement auf und/oder in einem Substrat aus polykristallinem oder amorphem Material gebildet sein.The component can be formed exclusively from dielectric material, metallic material and the material of the nanostructure. Furthermore, the component can be formed on and / or in a substrate made of polycrystalline or amorphous material.
Mit anderen Worten kann das erfindungsgemäße Bauelement nur
aus elektrisch leitfähigem Material, dielektrischem Material und Material der Nanostruktur (vorzugsweise eine Kohlenstoffnanoröhre) bestehen. In diesem Fall kann das Bauelement ohne kostenintensive halbleitertechnologische Verfahren hergestellt werden. Ein weiterer wichtiger Vorteil in diesem Zusammenhang ist, dass ein polykristallines oder amorphes Material, das heißt ein nicht-einkristallines Material als Substrat verwendet werden kann, um das Bauelement herzustellen. Somit ist bei der Herstellung des Bauelements ein teures, einkristallines SubstratIn other words, the component according to the invention can only consist of electrically conductive material, dielectric material and material of the nanostructure (preferably a carbon nanotube). In this case, the component can be manufactured without expensive semiconductor technology processes. Another important advantage in this connection is that a polycrystalline or amorphous material, that is to say a non-single-crystalline material, can be used as the substrate in order to produce the component. It is therefore an expensive, single-crystalline substrate for the production of the component
(beispielsweise ein Silizium-Wafer) vermieden. Es kann erfindungsgemäß im Prinzip ein beliebiges Ausgangs-Substrat verwendet werden (z.B. Glas).(e.g. a silicon wafer) avoided. In principle, any starting substrate can be used according to the invention (e.g. glass).
Es ist anzumerken, dass die Ausgestaltungen, die oben bezugnehmend auf das erfindungsgemäße Bauelement beschrieben sind, auch für die erfindungsgemäße Bauelement-Anordnung bzw. für das Verfahren zum Herstellen eines vertikal integrierten Bauelements gelten.It should be noted that the configurations which are described above with reference to the component according to the invention also apply to the component arrangement according to the invention or to the method for producing a vertically integrated component.
Ferner kann bei dem Verfahren zum Herstellen eines vertikal integrierten Bauelements auf einer, optional bereits strukturierten, elektrisch leitfähigen Schicht (insbesondere einer Metall-Schicht, beispielsweise eine Tantal-, Tantalnitrid-, Titan- oder Titannitrid-Schicht) die Mittel- Schicht, welche dielektrische Teilschichten und zusätzliche leitfähige Schichten (beispielsweise aus Polysilizium, Tantal, Titan, Niob, Aluminium) aufweisen kann, abgeschieden werden. Unter Verwendung eines Lithographie- und eines Ätzverfahrens kann dann ein vertikales Durchgangsloch mit einem typischen Durchmesser zwischen 0.4nm und lOOnm und mit einer typischen Länge von zwischen O.Olμm und 3μm in die Mittel-Schicht eingebracht werden kann. Bei diesem Verfahrensschritt werden die dielektrischen und elektrisch leitfähigen Teilschichten der Mittel-Schicht strukturiert. Es ist anzumerken, dass die laterale Ausdehnung des
Durchgangslochs weiter verringert werden kann, indem die Maske sublithographisch verengt wird. Die mit dem Durchgangsloch durchsetzte dritte elektrisch leitfähige Schicht wird im Weiteren entlang des Umfang des Durchgangslochs oxidiert, beispielsweise kann eine aus Polysilizium-Material hergestellte dritte elektrisch leitfähige Schicht oxidiert werden, so dass elektrisch isolierendes Siliziumdioxid-Material in einem Umgebungsbereich des Durchgangslochs in der dritten elektrisch leitfähigen Schicht ausgebildet wird, welches Siliziumdioxid-Material als Gate-isolierende Schicht verwendbar ist.Furthermore, in the method for producing a vertically integrated component on an optionally already structured, electrically conductive layer (in particular a metal layer, for example a tantalum, tantalum nitride, titanium or titanium nitride layer), the middle layer, which is dielectric Partial layers and additional conductive layers (for example made of polysilicon, tantalum, titanium, niobium, aluminum) can be deposited. Using a lithography and an etching process, a vertical through-hole with a typical diameter between 0.4nm and 100nm and with a typical length between O.Olμm and 3μm can then be made in the middle layer. In this process step, the dielectric and electrically conductive partial layers of the middle layer are structured. It should be noted that the lateral extent of the Through hole can be further reduced by sublithographically narrowing the mask. The third electrically conductive layer interspersed with the through hole is further oxidized along the circumference of the through hole, for example a third electrically conductive layer made of polysilicon material can be oxidized, so that electrically insulating silicon dioxide material is electrically in a surrounding area of the through hole in the third Is formed conductive layer, which silicon dioxide material can be used as a gate insulating layer.
Gemäß einer alternativen Ausgestaltung der Erfindung wird eine ringförmige, Gate-isolierende Schicht unter Verwendung des CVD-Verfahrens ("chemical vapour deposition") oder des ALD-Verfahrens ("atomic layer deposition") ausgebildet, indem das Durchgangsloch gleichmäßig mit einer elektrisch isolierenden Wandschicht beschichtet wird. Anschließend kann die Nanostruktur in dem Durchgangsloch ausgebildet werden, beispielsweise wird eine Kohlenstoffnanoröhre auf einem auf der ersten elektrisch leitfähigen Schicht abgeschiedenen Katalysatormaterial aufgewachsen. Das Katalysatormaterial kann entweder als Schicht auf der ersten elektrisch leitfähigen Schicht abgeschieden werden oder kann nach dem Ausbilden der Gate-isolierenden Schicht unter Verwendung des "electroless deposition" -Verfahrens, auf der Oberfläche der ersten elektrisch leitfähigen Schicht in dem Durchgangsloch abgeschieden werden. Nach dem Ausbilden der Nanostruktur kann ein Zwischenbereich zwischen dem Durchgangsloch und der Nanostruktur versiegelt werden, beispielsweise mittels Einbringens von Siliziumdioxid-Material in zumindest einen Teil des Durchgangslochs unter Verwendung eines CVD- oder Spin-On-Verfahrens . Überschüssiges Material kann gegebenenfalls zurückgeätzt werden, um die Nanostruktur wieder freizulegen, und die zweite elektrisch leitfähige
Schicht kann auf der Oberfläche der Schichtenfolge ausgebildet und gegebenenfalls strukturiert werden.According to an alternative embodiment of the invention, an annular, gate-insulating layer is formed using the chemical vapor deposition (CVD) method or the atomic layer deposition (ALD) method, in that the through-hole is uniformly coated with an electrically insulating wall layer is coated. The nanostructure can then be formed in the through hole, for example a carbon nanotube is grown on a catalyst material deposited on the first electrically conductive layer. The catalyst material can either be deposited as a layer on the first electrically conductive layer or, after forming the gate insulating layer using the "electroless deposition" method, can be deposited on the surface of the first electrically conductive layer in the through hole. After the nanostructure has been formed, an intermediate region can be sealed between the through hole and the nanostructure, for example by introducing silicon dioxide material into at least part of the through hole using a CVD or spin-on method. Excess material can optionally be etched back to expose the nanostructure, and the second electrically conductive Layer can be formed on the surface of the layer sequence and optionally structured.
Ausführungsbeispiele der Erfindung sind in den Figuren dargestellt und werden im Weiteren näher erläutert.Exemplary embodiments of the invention are shown in the figures and are explained in more detail below.
Es zeigen:Show it:
Figur 1A eine Querschnittsansicht eines Bauelements gemäß einem ersten Ausführungsbeispiel der Erfindung,FIG. 1A shows a cross-sectional view of a component according to a first exemplary embodiment of the invention,
Figur IB eine vergrößerte Querschnittsansicht, aufgenommen entlang der Schnittlinie A-A aus Figur 1A, des in Figur 1A gezeigten Bauelements gemäß dem ersten Ausführungsbeispiel der Erfindung,FIG. IB shows an enlarged cross-sectional view, taken along the section line A-A from FIG. 1A, of the component shown in FIG. 1A according to the first exemplary embodiment of the invention,
Figur 2 eine Querschnittsansicht eines Bauelements gemäß einem zweiten Ausführungsbeispiel der Erfindung,FIG. 2 shows a cross-sectional view of a component according to a second exemplary embodiment of the invention,
Figur 3 eine Bauelement-Anordnung gemäß einem ersten Ausführungsbeispiel der Erfindung,FIG. 3 shows a component arrangement according to a first exemplary embodiment of the invention,
Figur 4A eine Querschnittsansicht einer Bauelement-Anordnung gemäß einem zweiten Ausführungsbeispiel der Erfindung,FIG. 4A shows a cross-sectional view of a component arrangement according to a second exemplary embodiment of the invention,
Figur 4B einen Ersatzschaltkreis der in Figur 4A gezeigten Bauelement-Anordnung gemäß dem zweiten Ausführungsbeispiel der Erfindung,FIG. 4B shows an equivalent circuit of the component arrangement shown in FIG. 4A according to the second exemplary embodiment of the invention,
Figur 5 eine Querschnittsansicht eines Bauelements gemäß einem dritten Ausführungsbeispiel der Erfindung.FIG. 5 shows a cross-sectional view of a component according to a third exemplary embodiment of the invention.
Gleiche oder ähnliche Komponenten in unterschiedlichen Figuren sind mit gleichen Bezugsziffern versehen.
Im Weiteren wird bezugnehmend auf Fig.lA, Fig.lB ein vertikal integriertes Bauelement 100 gemäß einem ersten Ausführungsbeispiel der Erfindung beschrieben.The same or similar components in different figures are provided with the same reference numbers. A vertically integrated component 100 according to a first exemplary embodiment of the invention is described below with reference to FIGS. 1A, 1B.
Das in Fig.lA gezeigte vertikal integrierte Bauelement 100 hat eine erste elektrisch leitfähige Schicht 101, eine teilweise aus dielektrischem Material ausgebildete Mittel- Schicht 102 auf der ersten elektrisch leitfähigen Schicht 101 und eine zweite elektrisch leitfähige Schicht 103 auf der Mittel-Schicht 102. Ferner ist eine in ein in die Mittel- Schicht 102 eingebrachtes Durchgangsloch 108 integrierte Kohlenstoffnanoröhre 104 vorgesehen, die einen ersten, mit der elektrisch leitfähigen Schicht 101 gekoppelten Endabschnitt 104a und einen zweiten, mit der zweiten elektrisch leitfähigen Schicht 103 gekoppelten Endabschnitt 104b aufweist.The vertically integrated component 100 shown in FIG. 1A has a first electrically conductive layer 101, a middle layer 102 partially formed from dielectric material on the first electrically conductive layer 101 and a second electrically conductive layer 103 on the middle layer 102. Furthermore Provided is a carbon nanotube 104 integrated into a through-hole 108 made in the middle layer 102, which has a first end section 104a coupled to the electrically conductive layer 101 and a second end section 104b coupled to the second electrically conductive layer 103.
Zwischen der ersten leitfähigen Schicht 101 und der Kohlenstoffnanoröhre 104 ist Katalysatormaterial 107 zum Katalysieren des Ausbildens der Kohlenstoffnanoröhre 104 angeordnet .Catalyst material 107 for catalyzing the formation of the carbon nanotube 104 is arranged between the first conductive layer 101 and the carbon nanotube 104.
Die Mittel-Schicht 102 ist in zwei übereinander angeordnete dielektrische Teilschichten 102a, 102b aufgeteilt. Zwischen der ersten Mittel-Teilschicht 102a und der zweiten Mittel- Teilschicht 102b ist eine dritte elektrisch leitfähige Schicht 105 angeordnet, deren Dicke wesentlich geringer ist als die Dicke von beiden dielektrischen Teilschichten 102a, 102b.The middle layer 102 is divided into two dielectric sublayers 102a, 102b arranged one above the other. A third electrically conductive layer 105 is arranged between the first middle sublayer 102a and the second middle sublayer 102b, the thickness of which is substantially less than the thickness of both dielectric sublayers 102a, 102b.
Die erste elektrisch leitfähige Schicht 101 und die zweite elektrisch leitfähige Schicht 103 sind aus Tantalnitrid hergestellt, die dritte elektrisch leitfähige Schicht 105 ist aus Polysilizium hergestellt, das dielektrische Material der Mittel-Schicht 102 ist Siliziumdioxid oder Kalium-Ionen aufweisendes Siliziumdioxid. Bei dem vertikal integrierten
Bauelement 100 ist die Nanostruktur eine Kohlenstoffnanoröhre 104 und das Katalysatormaterial 107 ist eine Legierung aus Eisen, Kobalt und Nickel. Es ist bekannt, dass diese Materialkombination eine vorteilhafte katalytische Wirkung auf das Ausbilden einer Kohlenstoffnanoröhre hat.The first electrically conductive layer 101 and the second electrically conductive layer 103 are made of tantalum nitride, the third electrically conductive layer 105 is made of polysilicon, the dielectric material of the middle layer 102 is silicon dioxide or silicon dioxide containing potassium ions. With the vertically integrated Component 100 is the nanostructure a carbon nanotube 104 and the catalyst material 107 is an alloy of iron, cobalt and nickel. It is known that this combination of materials has an advantageous catalytic effect on the formation of a carbon nanotube.
Das vertikal integrierte Bauelement 100 ist als Feldeffekttransistor ausgebildet, bei welchem Bauelement 100 der erste Endabschnitt 104a der Kohlenstoffnanoröhre 104 als erster Source-/Drain-Bereich und der zweite Endabschnitt 104b der Kohlenstoffnanoröhre 104 als zweiter Source-/Drain- Bereich dient, und wobei in der dritten elektrisch leitfähigen Schicht 105, die als Gate-Elektrode des Feldeffekttransistors dient, entlang des darin eingebrachten Durchgangslochs 108 eine Ringstruktur 106 aus einem elektrisch isolierenden Material als Gate-isolierender Bereich des Feldtransistors angeordnet ist .The vertically integrated component 100 is designed as a field effect transistor, in which component 100 the first end portion 104a of the carbon nanotube 104 serves as the first source / drain region and the second end portion 104b of the carbon nanotube 104 serves as the second source / drain region, and in of the third electrically conductive layer 105, which serves as the gate electrode of the field effect transistor, a ring structure 106 made of an electrically insulating material is arranged as a gate-insulating region of the field transistor along the through hole 108 made therein.
Das in Fig.lA gezeigte vertikal integrierte Bauelement 100 erfüllt die Funktionalität eines Feldeffekttransistors. Die Leitfähigkeit der Kohlenstoffnanoröhre 104 kann charakteristisch beeinflusst werden, indem an die dritte elektrisch leitfähige Schicht 105, welche die Funktionalität einer Gate-Elektrode aufweist, eine geeignete elektrische Spannung angelegt wird. Mittels einer solchen elektrischenThe vertically integrated component 100 shown in FIG. 1A fulfills the functionality of a field effect transistor. The conductivity of the carbon nanotube 104 can be influenced characteristically by applying a suitable electrical voltage to the third electrically conductive layer 105, which has the functionality of a gate electrode. By means of such an electrical
Spannung kann die Leitfähigkeit der Kohlenstoffnanoröhre 104 in einem räumlich scharf definierten Mitten-Bereich 104c charakteristisch beeinflusst werden. Der Mitten-Bereich 104c fungiert anschaulich als Kanal-Bereich.Voltage, the conductivity of the carbon nanotube 104 can be influenced characteristically in a spatially sharply defined central region 104c. The central area 104c clearly functions as a channel area.
Da die dritte elektrisch leitfähige Schicht 105 erfindungsgemäß ausreichend dünn vorgesehen ist, bildet sich bei -Anlegen einer elektrischen Spannung an die dritte elektrisch leitfähige Schicht 105 aufgrund eines elektrostatischen Spitzeneffekts in einem angrenzendenSince the third electrically conductive layer 105 is provided according to the invention in a sufficiently thin manner, an electrical voltage is applied to the third electrically conductive layer 105 due to an electrostatic peak effect in an adjacent one
Umgebungsbereich der Kohlenstoffnanoröhre 104 ein besonders
starkes elektrisches Feld aus. Mittels des Feldeffekts ist die elektrische Leitfähigkeit der Kohlenstoff anoröhre 104 in dem an die dritte elektrisch leitfähige Schicht 105 angrenzenden Mitten-Bereich 104c sehr genau steuerbar.Surrounding area of the carbon nanotube 104 a particularly strong electric field. The electrical conductivity of the carbon tube 104 in the central region 104c adjoining the third electrically conductive layer 105 can be controlled very precisely by means of the field effect.
In Fig.lB ist eine vergrößerte Querschnittsansicht, aufgenommen entlang der Schnittlinie A-A aus Fig.lA, des vertikal integrierten Bauelements 100 aus Fig.lA gezeigt.FIG. 1B shows an enlarged cross-sectional view, taken along the section line A-A from FIG. 1A, of the vertically integrated component 100 from FIG. 1A.
Aus Fig.lB ist ersichtlich, dass in dem Durchgangsloch 108 die Kohlenstoffnanoröhre 104 enthalten ist. Die halbleitende Kohlenstoffnanoröhre 104 ist mittels der elektrisch isolierenden Ringstruktur 106 von der dritten elektrisch leitfähigen Schicht 105 entkoppelt. Die Stärke eines elektrischen Stromflusses zwischen den als Source- /Drain- Anschlüssen fungierenden ersten und zweiten elektrisch leitfähigen Schichten 101, 103 ist davon abhängig, ob an die Gate-Elektrode 105 eine elektrische Spannung angelegt ist oder nicht. Daher erfüllt das vertikal integrierte Bauelement 100 die Funktion eines Feldeffekttransistors.It can be seen from FIG. 1B that the carbon nanotube 104 is contained in the through hole 108. The semiconducting carbon nanotube 104 is decoupled from the third electrically conductive layer 105 by means of the electrically insulating ring structure 106. The strength of an electrical current flow between the first and second electrically conductive layers 101, 103 functioning as source / drain connections depends on whether or not an electrical voltage is applied to the gate electrode 105. The vertically integrated component 100 therefore fulfills the function of a field effect transistor.
Im Weiteren wird ein Verfahren zum Herstellen des vertikal integrierten Bauelements 100 gemäß einem bevorzugten Ausführungsbeispiel der Erfindung beschrieben (nicht gezeigt in den Figuren) .A method for producing the vertically integrated component 100 according to a preferred exemplary embodiment of the invention (not shown in the figures) is described below.
Zunächst wird die erste elektrisch leitfähige Schicht 101 mittels Aufbringens von Titannitrid, beispielsweise unter Verwendung eines CVD-Ver ahrens ("chemical vapour deposition") ausgebildet. In einem nächsten Teilschritt wird eine erste Mittel-Teilschicht 102a mittels Abscheidens von Siliziumdioxid-Material ausgebildet. Auf der ersten Mittel- Teilschicht 102a wird die dritte elektrisch leitfähige Schicht 105 mittels Abscheidens von Polysilizium-Material ausgebildet. Dies kann wieder unter Verwendung eines CVD- Verfahrens erfolgen. Auf der dritten elektrisch leitfähigen
Schicht 105 wird die zweite Mittel-Teilschicht 102b mittels Absetzens von Siliziumdioxid ausgebildet. Sowohl das Siliziumdioxid-Material der ersten Mittel-Teilschicht 102a als auch das Siliziumdioxid-Material der zweiten Mittel- Teilschicht 102b kann gemäß einem modifizierten TEOS-First of all, the first electrically conductive layer 101 is formed by applying titanium nitride, for example using a CVD method (“chemical vapor deposition”). In a next sub-step, a first middle sub-layer 102a is formed by depositing silicon dioxide material. The third electrically conductive layer 105 is formed on the first middle sublayer 102a by depositing polysilicon material. Again, this can be done using a CVD process. On the third electrically conductive Layer 105, second middle sub-layer 102b is formed by depositing silicon dioxide. Both the silicon dioxide material of the first middle sublayer 102a and the silicon dioxide material of the second middle sublayer 102b can be made according to a modified TEOS
Verfahren ( "Tetra-Ethyl-Ortho-Silicat" ) ausgebildet werden, derart, dass die Mittel-Teilschichten 102a, 102b jeweils Kalium-Dotieratome aufweisen können. Mittels Durchführens der zuvor beschriebenen Verfahrensschritte wird die zumindest teilweise auf dielektrischem Material ausgebildete Mittel- Schicht 102 ausgebildet. In die Mittel-Schicht 102 wird das Durchgangsloch 108 eingebracht. Dies erfolgt unter Verwendung eines Lithographie- und eines Ätz-Verf hrens . Das Ätz- Verfahren ist vorzugsweise derart gewählt (insbesondere mittels Vorgebens des Ätzmittels) , dass der Ätzvorgang an der elektrisch leitfähigen Schicht 101 stoppt. Mittels thermischen Oxidierens der dritten elektrisch leitfähigen Schicht 105 aus Polysilizium-Material wird die elektrisch isolierende Ringstruktur 106 aus Siliziumdioxid ausgebildet. Diese wird mit einer Dicke ausgebildet, die einer typischen Dicke einer Gateoxid-Schicht in einem MOSFET entspricht, beispielsweise lOnm. In einem weiteren Verfahrensschritt wird das Katalysatormaterial 107 aus Eisen, Kobalt und Nickel in dem Durchgangsloch 108 und auf der ersten elektrisch leitfähigen Schicht 101 abgeschieden. Dies kann unter Verwendung eines Aufdampf-, Sputter-, electro- oder electroless-deposition-Verfahrens realisiert werden. Gemäß dem "electroless-deposition" -Verfahren wird ein leitfähiges Material autokatalytisch aus einer das abzuscheidende Material aufweisenden Lösung ohne Anlegen eines elektrischen Stromes auf bestimmten Oberflächen-Bereichen einer Schichtenfolge abgeschieden. Anschließend wird die Kohlenstoffnanoröhre 104 in dem Durchgangsloch 108 aufgewachsen, wobei der erste Endabschnitt 104a mit der ersten leitfähigen Struktur 101 gekoppelt wird. Das Ausbilden einer Kohlenstoffnanoröhre erfolgt unter Verwendung eines
CVD-Verf hrens, bei dem einMethan/Wasserstoffgemisch als Kohlenstoffquelle in die Verfahrenskammer eingeleitet wird. Auf diese Weise entsteht häufig eine p-dotierte Kohlenstoffnanoröhre 104. Wahlweise können mittels Temperns die eventuell eingebrachten Kaliumionen aus der erstenProcess ("tetra-ethyl-orthosilicate") are formed such that the middle sub-layers 102a, 102b can each have potassium doping atoms. By performing the previously described method steps, the middle layer 102, which is at least partially formed on dielectric material, is formed. The through hole 108 is made in the middle layer 102. This is done using a lithography and an etching process. The etching method is preferably selected in such a way (in particular by specifying the etchant) that the etching process on the electrically conductive layer 101 stops. The electrically insulating ring structure 106 is formed from silicon dioxide by means of thermal oxidation of the third electrically conductive layer 105 made of polysilicon material. This is formed with a thickness that corresponds to a typical thickness of a gate oxide layer in a MOSFET, for example 10 nm. In a further method step, the catalyst material 107 made of iron, cobalt and nickel is deposited in the through hole 108 and on the first electrically conductive layer 101. This can be implemented using a vapor deposition, sputtering, electro or electroless deposition method. According to the "electroless deposition" process, a conductive material is deposited autocatalytically from a solution containing the material to be deposited without applying an electrical current to certain surface areas of a layer sequence. The carbon nanotube 104 is then grown in the through hole 108, the first end section 104 a being coupled to the first conductive structure 101. A carbon nanotube is formed using a CVD process in which a methane / hydrogen mixture is introduced as a carbon source into the process chamber. In this way, a p-doped carbon nanotube 104 is often formed. Optionally, the possibly introduced potassium ions from the first can be tempered
Mittel-Teilschicht 102a und der zweiten Mittel-Teilschicht 102b ausgetrieben werden, diese Kalium-Ionen diffundieren in die zuvor p-dotierte Kohlenstoffnanoröhre 104 ein und wirken als n-Dotierstoff . Dadurch wird die zunächst p-dotierte Kohlenstoffnanoröhre 104 in eine Kohlenstoffnanoröhre 104 des n-Leitungstyps umgewandelt. Ferner wird die zweite elektrisch leitfähige Schicht 103 auf der Mittel-Schicht 102 ausgebildet und mit dem zweiten Endabschnitt 104b der Kohlenstoffnanoröhre 104 gekoppelt, wodurch das in Fig.lA, Fig.lB gezeigte vertikal integrierte Bauelement 100 erhalten wird.Middle sublayer 102a and the second middle sublayer 102b are expelled, these potassium ions diffuse into the previously p-doped carbon nanotube 104 and act as an n-dopant. As a result, the initially p-doped carbon nanotube 104 is converted into a carbon nanotube 104 of the n-conduction type. Furthermore, the second electrically conductive layer 103 is formed on the middle layer 102 and coupled to the second end section 104b of the carbon nanotube 104, as a result of which the vertically integrated component 100 shown in FIGS. 1A, 1B is obtained.
Im Weiteren wird bezugnehmend auf Fig.2 ein als Feldeffekttransitor ausgestaltetes, vertikal integriertes Bauelement 200 beschrieben. Im Weiteren werden lediglich die Unterschiede zwischen dem vertikal integrierten Bauelement 200 und dem vertikal integrierten Bauelement 100 beschrieben.A vertically integrated component 200 designed as a field effect transistor is described below with reference to FIG. Only the differences between the vertically integrated component 200 and the vertically integrated component 100 are described below.
Der Unterschied zwischen dem vertikal integrierten Bauelement 200 und dem vertikal integrierten Bauelement 100 ist, dass imThe difference between the vertically integrated component 200 and the vertically integrated component 100 is that in FIG
Fall des vertikal integrierten Bauelements 200 die elektrisch isolierende Ringstruktur 106 aus Fig.lA nicht vorgesehen ist.In the case of the vertically integrated component 200, the electrically insulating ring structure 106 from FIG. 1A is not provided.
Stattdessen ist das Durchgangsloch 108 des vertikal integrierten Bauelements 200 mit einer durchgehenden elektrisch isolierenden Randbeschichtung 201 versehen, welche die Funktionalität einer Gate-isolierenden Schicht wahrnimmt.Instead, the through hole 108 of the vertically integrated component 200 is provided with a continuous electrically insulating edge coating 201, which perceives the functionality of a gate insulating layer.
Mit anderen Worten erfüllt das vertikal integrierteIn other words, the vertically integrated
Bauelement 200 aus Fig.2 die Funktion einesComponent 200 from FIG. 2 has the function of a
Feldeffekttransistors, wobei die Leitfähigkeit der Kohlenstoffnanoröhre 104 mittels Anlegens einer elektrischenField effect transistor, wherein the conductivity of the carbon nanotube 104 by applying an electrical
Spannung an die dritte elektrisch leitfähige Schicht 105
gesteuert wird. Dies erfolgt unter Verwendung des Feldeffekts, für den ein den Mitten-Bereich 104c der Kohlenstoffnanoröhre 104 umgebender Teilbereich der elektrisch isolierenden Randbeschichtung 201 wesentlich ist.Voltage to the third electrically conductive layer 105 is controlled. This takes place using the field effect, for which a partial area of the electrically insulating edge coating 201 surrounding the central area 104c of the carbon nanotube 104 is essential.
Um das vertikal integrierte Bauelement 200 herzustellen, wird abweichend von dem Herstellungsverfahren zum Herstellen des vertikal integrierten Bauelements 100 vor dem Aufwachsen der Kohlenstoffnanoröhre 104 in dem Durchgangsloch 108 das Durchgangsloch 108 unter Verwendung des CVD-Verfahrens gleichmäßig mit einem elektrisch isolierenden Material beschichtet, wodurch die elektrisch isolierende Randbeschichtung 201 ausgebildet wird. Diese kann zusätzlich die Funktion eines Abstandshalters bzw. einer Führung für die Kohlenstoffnanoröhre 104 erfüllen.In order to manufacture the vertically integrated device 200, unlike the manufacturing method for manufacturing the vertically integrated device 100, prior to growing the carbon nanotube 104 in the through hole 108, the through hole 108 is coated uniformly with an electrically insulating material using the CVD method, thereby electrically insulating edge coating 201 is formed. This can additionally fulfill the function of a spacer or a guide for the carbon nanotube 104.
Im Weiteren wird bezugnehmend auf Fig.3 eine Bauelement- Anordnung 300 gemäß einem ersten Ausführungsbeispiel der Erfindung beschrieben.A component arrangement 300 according to a first exemplary embodiment of the invention is described below with reference to FIG.
Wie in Fig.3 gezeigt, weist die Bauelement-Anordnung 300 zwei übereinander angeordnete Bauelemente auf , von denen j edes ähnlich wie das vertikal integrierte Bauelement 100 ausgebildet ist . Anschaulich weist die Bauelement-Anordnung 300 einen Feldeffekttransistor, gebildet von dem vertikal integrierten Bauelement 100 , auf , welcher über einem anderen Feldeffekttransistor angeordnet ist .As shown in FIG. 3, the component arrangement 300 has two components arranged one above the other, each of which is configured similarly to the vertically integrated component 100. The component arrangement 300 clearly has a field effect transistor, formed by the vertically integrated component 100, which is arranged above another field effect transistor.
Der zusätzliche Feldeffekttransistor, der unterhalb des vertikal integrierten Bauelements 100 angeordnet ist, weist eine gemeinsame elektrisch leitfähige Schicht 301 gemeinsam mit dem vertikal integrierten Bauelement 100 auf , mit anderen Worten ist bei der Bauelement-Anordnung 300 die erste elektrisch leitfähige Schicht 101 aus Fig . lA und die obere elektrisch leitfähige Schicht des darunterliegendenThe additional field effect transistor, which is arranged below the vertically integrated component 100, has a common electrically conductive layer 301 together with the vertically integrated component 100, in other words, in the component arrangement 300, the first electrically conductive layer 101 from FIG. lA and the upper electrically conductive layer of the underlying
Feldeffekttransistors als gemeinsame Schicht ausgebildet .
Der in der Bauelement-Anordnung 300 verglichen mit dem vertikal integrierten Bauelement 100 zusätzlich vorgesehene Feldeffekttransistor weist eine zusätzliche erste elektrisch leitfähige Schicht 303 auf, auf der eine zusätzliche Mittel- Schicht 302 ausgebildet ist. Diese ist aus einer ersten Mittel-Teilschicht 302a, einer zweiten Mittel-Teilschicht 302b und einer zusätzlichen dritten elektrisch leitfähigen Schicht 305 gebildet, die zwischen den Mittel-Teilschichten 302a, 302b angeordnet ist. Die erste Mittel-Teilschicht 302a und die zweite Mittel-Teilschicht 302b der zusätzlichen Mittel-Schicht 302 sind aus Siliziumdioxid-Material hergestellt. Die zusätzliche dritte elektrisch leitfähige Schicht 305 ist ausgebildet wie die elektrisch leitfähige Schicht 105. Ferner ist von einem zusätzlichen Durchgangsloch 308 des gemäß Fig.3 unteren Bereichs der Bauelement-Anordnung 300 in einem Bereich, in dem das Durchgangsloch 308 die zusätzliche dritte elektrisch leitfähige Schicht 305 durchstößt, eine zusätzliche elektrisch isolierende Ringstruktur 306 angeordnet. Auf zusätzlichem Katalysatormaterial 307 ist eine zusätzliche Kohlenstoffnanoröhre 304 aufgewachsen, deren gemäß Fig.3 unterer Endabschnitt 304a mit dem zusätzlichen Katalysatormaterial 307 gekoppelt ist, und deren oberer Endabschnitt 304b mit der gemeinsamen elektrisch leitfähigen Schicht 301 gekoppelt ist.Field effect transistor formed as a common layer. The field effect transistor additionally provided in the component arrangement 300 compared to the vertically integrated component 100 has an additional first electrically conductive layer 303, on which an additional middle layer 302 is formed. This is formed from a first middle sublayer 302a, a second middle sublayer 302b and an additional third electrically conductive layer 305, which is arranged between the middle sublayers 302a, 302b. The first middle sublayer 302a and the second middle sublayer 302b of the additional middle layer 302 are made of silicon dioxide material. The additional third electrically conductive layer 305 is designed like the electrically conductive layer 105. Furthermore, an additional through hole 308 of the lower region of the component arrangement 300 according to FIG. 3 is in a region in which the through hole 308 is the additional third electrically conductive layer 305 penetrates, an additional electrically insulating ring structure 306 arranged. An additional carbon nanotube 304 has been grown on additional catalyst material 307, the lower end section 304a of which is coupled to the additional catalyst material 307 according to FIG. 3, and the upper end section 304b of which is coupled to the common electrically conductive layer 301.
Anschaulich ist die Nanostruktur bei der Bauelement-Anordnung 300 aus der Kohlenstoffnanoröhre 104 und der zusätzlichen Kohlenstoffnanoröhre 304 gebildet. Teilbereiche derThe nanostructure in the component arrangement 300 is clearly formed from the carbon nanotube 104 and the additional carbon nanotube 304. Subareas of
Nanostruktur, nämlich die Kohlenstoffnanoröhre 104 einerseits und die zusätzliche Kohlenstoffnanoröhre 304 andererseits, weisen eine unterschiedliche elektrische Leitfähigkeit auf. Die Kohlenstoffnanoröhre 104 der Nanostruktur ist (wie oben beschrieben) mit Ladungsträgern des n-Leitungstyps dotiert, und die zusätzliche Kohlenstoffnanoröhre 304 der Nanostruktur
ist mit Ladungsträgern des p-Leitungstyps dotiert. Die unterschiedliche Dotierung der Kohlenstoffnanoröhren 104, 304 beruht darauf, dass die Kohlenstoffnanoröhre 104 von mit Kalium-Ionen dotiertem Siliziumdioxid-Material 102a, 102b umgeben ist, wohingegen die zusätzliche Kohlenstoffnanoröhre 304 von reinem Siliziumdioxid-Material 302a, 302b umgeben ist. Beim Tempern der Schichtenfolge wird das Kalium-Material aus den Schichten 102a, 102b ausgetrieben und diffundiert in die Kohlenstoffnanoröhre 104 ein, die dadurch n-dotiert wird. Bei der Kohlenstoff anoröhre 304 erfolgt eine solcheThe nanostructure, namely the carbon nanotube 104 on the one hand and the additional carbon nanotube 304 on the other hand, have a different electrical conductivity. The carbon nanotube 104 of the nanostructure is (as described above) doped with charge carriers of the n-type, and the additional carbon nanotube 304 of the nanostructure is doped with p-type charge carriers. The different doping of the carbon nanotubes 104, 304 is based on the fact that the carbon nanotube 104 is surrounded by silicon dioxide material 102a, 102b doped with potassium ions, whereas the additional carbon nanotube 304 is surrounded by pure silicon dioxide material 302a, 302b. When the layer sequence is tempered, the potassium material is driven out of the layers 102a, 102b and diffuses into the carbon nanotube 104, which is thereby n-doped. Such is the case with the carbon anotube 304
Umdotierung nicht, da das sie umgebende Material 302a, 302b von Kalium-Dotierstoff frei ist. Dadurch verbleibt die zusätzliche Kohlenstoffnanoröhre 304 in dem p-dotierten Zustand, in welchem sie bei dem CVD-Aufwachsen erhalten wurde. Anders ausgedrückt erfüllt der gemäß Fig.3 obere Feldeffekttransistor der Bauelement-Anordnung 300 die Funktionalität eines n-MOSFETs, wohingegen der gemäß Fig.3 untere Feldeffekttransistor der Bauelement-Anordnung 300 die Funktionalität eines p-MOSFETs erfüllt.Not re-doping since the surrounding material 302a, 302b is free of potassium dopant. As a result, the additional carbon nanotube 304 remains in the p-doped state in which it was obtained during the CVD growth. In other words, the upper field effect transistor of the component arrangement 300 according to FIG. 3 fulfills the functionality of an n-MOSFET, whereas the lower field effect transistor of the component arrangement 300 according to FIG. 3 fulfills the functionality of a p-MOSFET.
Die Bauelement-Anordnung 300 wird hergestellt, indem zunächst der gemäß Fig.3 untere Feldeffekttransistor ausgebildet wird, analog wie oben bezugnehmend auf Fig.lA beschrieben. Abweichend von dem Herstellungsverfahren zum Herstellen des vertikal integrierten Bauelements 100 aus Fig.lA werden allerdings beim Herstellen der Bauelement-Anordnung 300 aus Fig.3 die erste Mittel-Teilschicht 302a und die zweite Mittel-Teilschicht 302b jeweils aus reinem, von Kalium- Dotieratomen freiem Siliziumdioxid hergestellt. Dadurch ist der untere Feldeffekttransistor der Bauelement-Anordnung 300 geschaffen, der die zusätzliche Kohlenstoffnanoröhre 304 des p-Leitungstyps aufweist. Auf dieser Schichtenfolge wird im Weiteren ein vertikal integriertes Bauelement 100, wie es in Fig.lA gezeigt ist, hergestellt. Dabei ist zu beachten, dass die gemeinsame elektrisch leitfähige Schicht 301 sowohl den gemäß Fig.3 oberen Source-/Drain-Anschluss des gemäß Fig.3
unteren Feldeffekttransistors, als auch den gemäß Fig.3 unteren Source-/Drain-Anschluss des gemäß Fig.3 oberen Feldeffekttransistors ausbildet. Sowohl die erste Mittel- Teilschicht 102a als auch die zweite Mittel-Teilschicht 102b wird gemäß dem beschriebenen Ausführungsbeispiel aus mit Kalium-Material dotiertem Siliziumdioxid-Material hergestellt, so dass die bei dem CVD-Herstellungsverfahren als p-dotierte Kohlenstoffnanoröhre erhaltene Kohlenstoffnanoröhre 104 nach dem oben beschriebenen Tempern n-dotiert ist.The component arrangement 300 is produced by first forming the lower field-effect transistor in accordance with FIG. 3, analogously to that described above with reference to FIG. 1A. In a departure from the production method for producing the vertically integrated component 100 from FIG. 1A, however, when the component arrangement 300 from FIG. 3 is produced, the first middle sublayer 302a and the second middle sublayer 302b are each made of pure potassium doping atoms Silicon dioxide manufactured. This creates the lower field-effect transistor of the component arrangement 300, which has the additional carbon nanotube 304 of the p-conduction type. A vertically integrated component 100, as shown in FIG. 1A, is subsequently produced on this layer sequence. It should be noted that the common electrically conductive layer 301 has both the upper source / drain connection according to FIG forms the lower field effect transistor, as well as the lower source / drain connection according to FIG. 3 of the upper field effect transistor according to FIG. According to the exemplary embodiment described, both the first middle sublayer 102a and the second middle sublayer 102b are produced from silicon dioxide material doped with potassium material, so that the carbon nanotube 104 obtained as a p-doped carbon nanotube in the CVD production process faces upwards described annealing is n-doped.
Zusammenfassend ist mit der Bauelement-Anordnung 300 ein n- MOS-Transistor auf einem p-MOS-Transistor bereitgestellt, daher kann die Bauelement-Anordnung 300 als CMOS-Bauelement verwendet werden. Bei der CMOS-Technologie ("complementary metal oxide semiconductor") werden wechselweise arbeitende n- Kanal und p-Kanal MOSFETs als Schalter verwendet. CMOS- Bauelemente werden in vielen hochintegrierten Schaltkreisen •verwendet, zum Beispiel sind viele moderne Mikroprozessoren in dieser Technologie aufgebaut.In summary, the component arrangement 300 provides an n-MOS transistor on a p-MOS transistor, therefore the component arrangement 300 can be used as a CMOS component. In CMOS technology ("complementary metal oxide semiconductor"), alternating n-channel and p-channel MOSFETs are used as switches. CMOS devices are used in many highly integrated circuits, for example, many modern microprocessors are built in this technology.
Im Weiteren wird bezugnehmend auf Fig.4A, Fig.4B eine Bauelement-Anordnung 400 gemäß einem zweiten Ausführungsbeispiel der Erfindung beschrieben.A component arrangement 400 according to a second exemplary embodiment of the invention is described below with reference to FIGS. 4A, 4B.
Bei der Bauelement-Anordnung 400 sind ein p-MOS-Feldeffekt- Tranistor 401, gebildet von der gemäß Fig.4A unteren Schichtenfolge und ein n-MOS-Feldtransistor 402, gebildet von der gemäß Fig.4A oberen Schichtenfolge der Bauelement- Anordnung 400 miteinander als Inverter-Schaltkreis verschaltet .In the component arrangement 400, a p-MOS field-effect transistor 401, formed by the lower layer sequence according to FIG. 4 A and an n-MOS field transistor 402, formed by the upper layer sequence of the component arrangement 400 according to FIG interconnected as an inverter circuit.
Im Weiteren wird Aufbau und Funktionalität dieses CMOS- Inverters beschrieben. Wie in Fig.4A gezeigt, ist an die zweite elektrisch leitfähige Schicht 103 des n-MOS-The structure and functionality of this CMOS inverter is described below. As shown in FIG. 4A, the second electrically conductive layer 103 of the n-MOS
Feldeffekttransistors 402 das elektrische Massepotential Vss
403 angelegt. Ferner ist an die zusätzliche erste elektrisch leitfähige Schicht 303 des p-MOS-Feldeffekttransistors 401 das elektrische Potential einer VersorgungsSpannung Vdd 404 angelegt. Darüber hinaus sind die dritte elektrisch leitfähige Schicht 105 und die zusätzliche dritte elektrisch leitfähige Schicht 305 mit einem Eingang 405 des CMOS- Inverters gekoppelt. Die gemeinsame elektrisch leitfähige Schicht 301 ist mit einem Ausgang 406 des CMOS-Inverters gekoppelt.Field effect transistor 402 the electrical ground potential V ss 403 created. Furthermore, the electrical potential of a supply voltage Vdd 404 is applied to the additional first electrically conductive layer 303 of the p-MOS field-effect transistor 401. In addition, the third electrically conductive layer 105 and the additional third electrically conductive layer 305 are coupled to an input 405 of the CMOS inverter. The common electrically conductive layer 301 is coupled to an output 406 of the CMOS inverter.
In Fig.4B ist ein Ersatzschaltkreis 410 der Bauelement- Anordnung 400 gezeigt, welche Bauelement-Anordnung 400 als CMOS-Inverter verschaltet ist. Der Eingang 405 ist mit den Gate-Bereichen des p-MOS-Feldeffekttransistors 401 und des n- MOS-Feldeffekttransistors 402 gekoppelt, das heißt mit den als jeweilige Gate-Elektrode fungierenden Komponenten der Bauelement-Anordnung 400, nämlich mit der dritten elektrisch leitfähigen Schicht 105 und mit der zusätzlichen dritten elektrisch leitfähigen Schicht 305. Die zweite elektrisch leitfähige Schicht 103 des n-MOS-Feldeffekttransistors 402 dient als erster Source-/Drain-Anschluss des n-MOS- Feldeffekttransistors 402, und an die erste elektrisch leitfähige Schicht 103 ist daher das elektrische Massepotential Vss 403 angelegt. Ferner ist ein zweiter Source-/Drain-Anschluss des n-MOS-Feldeffekttransistors 402 und ein erster Source-/Drain-Anschluss des p-MOS- Feldeffekttransistors 401 gemeinsam als gemeinsame elektrisch leitfähige Schicht 301 ausgebildet und mit dem Ausgang 406 der als CMOS-Inverter verschalteten Bauelement-Anordnung 410 gekoppelt. Ein zweiter Source-/Drain-Anschluss des p-MOS- Feldeffekttransistors 401 ist von der zusätzlichen elektrisch leitfähigen Schicht 303 gebildet, an welche das elektrische Potential der Versorgungsspannung Vd 404 angelegt ist.4B shows an equivalent circuit 410 of the component arrangement 400, which component arrangement 400 is connected as a CMOS inverter. The input 405 is coupled to the gate regions of the p-MOS field-effect transistor 401 and the n-MOS field-effect transistor 402, that is to say to the components of the component arrangement 400 functioning as the respective gate electrode, namely to the third electrically conductive layer 105 and with the additional third electrically conductive layer 305. The second electrically conductive layer 103 of the n-MOS field-effect transistor 402 serves as the first source / drain connection of the n-MOS field-effect transistor 402, and is to the first electrically conductive layer 103 therefore the electrical ground potential V SS 403 applied. Furthermore, a second source / drain connection of the n-MOS field-effect transistor 402 and a first source / drain connection of the p-MOS field-effect transistor 401 are jointly formed as a common electrically conductive layer 301 and connected to the output 406 as the CMOS Inverter connected component arrangement 410 coupled. A second source / drain connection of the p-MOS field-effect transistor 401 is formed by the additional electrically conductive layer 303, to which the electrical potential of the supply voltage V d 404 is applied.
Wird an den Eingang 405 ein elektrisches Potential mit einem logischen Wert "1" angelegt, so ist der n-MOS-
Feldeffekttransistors 402 leitend, wohingegen der p-MOS- Feldeffekttransistors 402 nichtleitend ist. Daher ist der Ausgang 406 mit dem elektrischen Massepotential Vss 403 gekoppelt. Daher liegt in diesem Falle an dem Ausgang 406 ein Signal mit einem logischen Wert "0". In einem anderen Fall, in dem an den Eingang 405 ein elektrisches Signal mit einem logischen Wert "0" angelegt wird, ist der n-MOS- Feldeffekttransistors 402 nichtleitend, wohingegen der p-MOS- Feldeffekttransistors 401 leitend ist. Daher ist der Ausgang 406 mit dem elektrischen Potential der VersorgungsSpannung Vdd 404 gekoppelt, so dass an dem Ausgang 406 ein elektrisches Signal mit einem logischen Wert "1" anliegt. Zusammenfassend ist festzustellen, dass gemäß der Funktionalität des CMOS-Inverters an dem Ausgang 406 jeweils das zu dem an dem Eingang 405 bereitgestellten Signal inverse Signal anliegt .If an electrical potential with a logic value "1" is applied to input 405, then the n-MOS Field-effect transistor 402 is conductive, whereas p-MOS field-effect transistor 402 is non-conductive. Output 406 is therefore coupled to electrical ground potential Vss 403. In this case, therefore, a signal with a logic value "0" is present at output 406. In another case, in which an electrical signal with a logic value "0" is applied to the input 405, the n-MOS field-effect transistor 402 is non-conductive, whereas the p-MOS field-effect transistor 401 is conductive. The output 406 is therefore coupled to the electrical potential of the supply voltage Vdd 404, so that an electrical signal with a logic value "1" is present at the output 406. In summary, it should be noted that, in accordance with the functionality of the CMOS inverter, the signal inverse to the signal provided at input 405 is present at output 406.
Im Weiteren wird bezugnehmend auf Fig.5 ein vertikal integriertes -Bauelement 500 gemäß einem dritten bevorzugten Ausführungsbeispiel der Erfindung beschrieben.A vertically integrated component 500 according to a third preferred exemplary embodiment of the invention is described below with reference to FIG.
Ein Unterschied zwischen dem vertikal integrierten Bauelement 500 und dem vertikal integrierten Bauelement 100 besteht darin, dass die Mittel-Schicht anders aufgebaut ist. Die Mitten-Schicht 501 des vertikal integrierten Bauelements 500 weist zusätzlich zu der ersten Mittel-Teilschicht 102a aus Kalium-dotiertem Siliziumdioxid, der zweiten Mittel- Teilschicht 102b aus Kalium-dotiertem Siliziumdioxid, der dritten elektrisch leitfähigen Schicht 105 aus Polysilizium und der elektrisch isolierenden Ringstruktur 106 eine dritte Mittel-Teilschicht 501a aus Siliziumnitrid auf, welche zwischen der dritten elektrisch leitfähigen Schicht 105 und einer vierten elektrisch leitfähigen Schicht 502 angeordnet ist. In einem Grenzbereich zwischen dem Durchgangsloch 108 und der vierten elektrisch leitfähigen Schicht 502 ist eine zusätzliche elektrisch isolierende Ringstruktur 503
angeordnet. Die vierte elektrisch leitfähige Schicht 502 ist aus Polysilizium-Material und die vierte elektrisch isolierende Ringstruktur 503 ist aus Siliziumdioxid-Material hergestellt.One difference between the vertically integrated component 500 and the vertically integrated component 100 is that the middle layer is constructed differently. The middle layer 501 of the vertically integrated component 500 has, in addition to the first middle sublayer 102a made of potassium-doped silicon dioxide, the second middle sublayer 102b made of potassium doped silicon dioxide, the third electrically conductive layer 105 made of polysilicon and the electrically insulating ring structure 106 a third middle sublayer 501a made of silicon nitride, which is arranged between the third electrically conductive layer 105 and a fourth electrically conductive layer 502. An additional electrically insulating ring structure 503 is located in a boundary area between the through hole 108 and the fourth electrically conductive layer 502 arranged. The fourth electrically conductive layer 502 is made of polysilicon material and the fourth electrically insulating ring structure 503 is made of silicon dioxide material.
Das vertikal integrierte Bauelement 500 stellt einen Feldeffekttransistor mit zwei Gate-Elektroden 105, 502 dar. Für bestimmte Anwendungen kann ein solcher Feldeffekttransistor mit mehreren Gate-Anschlüssen vorteilhaft sein, um die elektrische Leitfähigkeit derThe vertically integrated component 500 represents a field effect transistor with two gate electrodes 105, 502. For certain applications, such a field effect transistor with a plurality of gate connections can be advantageous in order to improve the electrical conductivity of the
Kohlenstoffnanoröhre 104 an unterschiedlichen Teilbereichen zu beeinflussen oder an mehreren Teilbereichen gleichzeitig.Influence carbon nanotube 104 on different partial areas or on several partial areas simultaneously.
Zusammenfassend ist erfindungsgemäß ein vertikal integriertes Bauelement geschaffen, das wahlweise alsIn summary, a vertically integrated component is created according to the invention, which is optionally available as
Feldeffekttransistor, CMOS-Bauelement, Inverter und Feldeffekttransistor mit mehreren Gate-Elektroden verwendbar ist. Aus diesen Grund-Komponenten sind eine Vielzahl komplexerer Schaltkreise aufbaubar bzw. ausbildbar, beispielsweise Logikgatter und weitere komplexe Schaltkreis- Anordnungen. Die einzelnen Bauelemente der Erfindung können aufgrund der vertikalen Orientierung in beliebiger Weise übereinander ausgebildet werden, und können ferner nebeneinander ausgebildet werden.
Field effect transistor, CMOS component, inverter and field effect transistor with multiple gate electrodes can be used. A large number of more complex circuits can be constructed or formed from these basic components, for example logic gates and further complex circuit arrangements. Due to the vertical orientation, the individual components of the invention can be formed one above the other in any way, and can also be formed side by side.
In diesem Dokument sind folgende Veröffentlichungen zitiert:The following publications are cited in this document:
[1] Harris, PJF (1999) "Carbon Nanotubes and Related[1] Harris, PJF (1999) "Carbon Nanotubes and Related
Structures - New Materials for the Twenty-first Century.", Cambridge University Press, Cambridge, pp.Structures - New Materials for the Twenty-First Century. ", Cambridge University Press, Cambridge, pp.
1 to 15, 111 to 1551 to 15, 111 to 155
[2] Derycke, V, Martel, R, Appenzeller, J, Avouris, P (2001) "Carbon Nanotube Inter- and Intramolecular Logic Gates", Nanoletters l(9):453-456[2] Derycke, V, Martel, R, Appenzeller, J, Avouris, P (2001) "Carbon Nanotube Inter- and Intramolecular Logic Gates", Nanoletters l (9): 453-456
[3] Johnson, JC, Yan, H, Schaller, RD, Haber, LH, Saykally, RJ, Yang, P (2001) "Single Nanowire Lasers" J . Phys . Che . B, im Druck, http: //www. cchem.berke1ey. edu/~pdygrp/pub.html[3] Johnson, JC, Yan, H, Schaller, RD, Haber, LH, Saykally, RJ, Yang, P (2001) "Single Nanowire Lasers" J. Phys. Che. B, in press, http: // www. cchem.berke1ey. edu / ~ pdygrp / pub.html
(Online, zitiert am 26. November 2001)(Online, cited November 26, 2001)
[4] Huang, Y, Duan, X, Cui, Y, Lauhon, LJ, Kim, KH, Lieber,[4] Huang, Y, Duan, X, Cui, Y, Lauhon, LJ, Kim, KH, dear,
CM (2001) "Logic Gates and Computation from Assembled Nanowire Building Blocks", Science 294:1313-1317CM (2001) "Logic Gates and Computation from Assembled Nanowire Building Blocks", Science 294: 1313-1317
[5] DE 100 36 897 Cl[5] DE 100 36 897 Cl
[6] US 2002/0001905 AI[6] US 2002/0001905 AI
[7] Choi, WB, Chu, JU, Jeong, KS, Bae, EJ, Lee, JW, Kim, JJ, Lee, JO (2001) "Ultrahogh-density nanotransistors by using selectively grown vertical carbon nanotubes" Applied Physics Letters, Vol.79, Nr.22, 3696-3698[7] Choi, WB, Chu, JU, Jeong, KS, Bae, EJ, Lee, JW, Kim, JJ, Lee, JO (2001) "Ultrahogh-density nanotransistors by using selectively grown vertical carbon nanotubes" Applied Physics Letters, Vol.79, No.22, 3696-3698
[8] WO 01/61753 AI
Bezugszeichenliste[8] WO 01/61753 AI LIST OF REFERENCE NUMBERS
100 Vertikal integriertes Bauelement100 Vertically integrated component
101 erste elektrisch leitfähige Schicht101 first electrically conductive layer
102 Mittel-Schicht102 middle layer
102a erste Mittel-Teilschicht 102b zweite Mittel-Teilschicht102a first middle sublayer 102b second middle sublayer
103 zweite elektrisch leitfähige Schicht103 second electrically conductive layer
104 Kohlenstoffnanoröhre 104a erster Endabschnitt 104b zweiter Endabschnitt 104c Mitten-Bereich104 carbon nanotube 104a first end section 104b second end section 104c center region
105 dritte elektrisch leitfähige Schicht105 third electrically conductive layer
106 elektrisch isolierende Ringstruktur106 electrically insulating ring structure
107 Katalysator-Material107 catalyst material
108 Durchgangsloch108 through hole
200 Vertikal integriertes Bauelement200 Vertically integrated component
201 elektrisch isolierende Randbeschichtung 300 Bauelement-Anordnung201 electrically insulating edge coating 300 component arrangement
301 gemeinsame elektrisch leitfähige Schicht301 common electrically conductive layer
302 zusätzliche Mittel-Schicht 302a erste Mittel-Teilschicht 302b zweite Mittel-Teilschicht302 additional middle layer 302a first middle sublayer 302b second middle sublayer
303 zusätzliche erste elektrisch leitfähige Schicht303 additional first electrically conductive layer
304 zusätzliche Kohlenstoffnanoröhre 304a erster Endabschnitt304 additional carbon nanotube 304a first end section
304b zweiter Endabschnitt 304c Mitten-Bereich304b second end section 304c center region
305 zusätzliche* dritte elektrisch leitfähige Schicht305 additional * third electrically conductive layer
306 zusätzliche elektrisch isolierende Ringstruktur306 additional electrically insulating ring structure
307 zusätzliches Katalysator-Material307 additional catalyst material
308 Dμrchgangsloch308 through hole
400 Bauelement-Anordnung400 component arrangement
401 p-MOS Feldeffekttransistor401 p-MOS field effect transistor
402 n-MOS Feldeffekttransistor402 n-MOS field effect transistor
403 elektrisches Massepotential
404 Versorgungsspannung403 electrical ground potential 404 supply voltage
405 Eingang405 entrance
406 Ausgang406 exit
410 Ersatzschaltbild410 equivalent circuit diagram
500 Vertikal integriertes Bauelement500 Vertically integrated component
501 Mitten-Schicht501 middle layer
501a dritte Mittel-Teilschicht501a third middle sub-layer
502 vierte elektrisch leitfähige Schicht502 fourth electrically conductive layer
503 zusätzliche elektrisch isolierende Ringstruktur
503 additional electrically insulating ring structure
Claims
1. Vertikal integriertes Bauelement1. Vertically integrated component
• mit einer ersten elektrisch leitfähigen Schicht; • mit einer teilweise aus dielektrischem Material ausgebildeten Mittel-Schicht auf der ersten elektrisch leitfähigen Schicht;With a first electrically conductive layer; With a middle layer partially formed from dielectric material on the first electrically conductive layer;
• mit einer zweiten elektrisch leitfähigen Schicht auf der Mittel-Schicht; • mit einer in ein in die Mittel-Schicht eingebrachtes Durchgangsloch integrierten Nanostruktur mit einem ersten, mit der ersten elektrisch leitfähigen Schicht gekoppelten Endabschnitt und mit einem zweiten, mit der zweiten elektrisch leitfähigen Schicht gekoppelten Endabschnitt;• with a second electrically conductive layer on the middle layer; With a nanostructure integrated into a through hole made in the middle layer, with a first end section coupled to the first electrically conductive layer and with a second end section coupled to the second electrically conductive layer;
• wobei die Mittel-Schicht zwischen zwei benachbarten dielektrischen Teilschichten eine dritte elektrisch leitfähige Schicht aufweist, deren Dicke geringer ist als die Dicke von zumindest einer- der dielektrischen Teilschichten.• The middle layer between two adjacent dielectric sub-layers has a third electrically conductive layer, the thickness of which is less than the thickness of at least one of the dielectric sub-layers.
2. Bauelement nach Anspruch 1, bei dem zwischen der ersten leitfähigen Schicht und der Nanostruktur Katalysatormaterial zum Katalysieren des Ausbildens der Nanostruktur angeordnet ist.2. The component according to claim 1, in which catalyst material for catalyzing the formation of the nanostructure is arranged between the first conductive layer and the nanostructure.
3. Bauelement nach Anspruch 1 oder 2 , bei dem die dritte elektrisch leitfähige Schicht die Nanostruktur in einem Umgebungsbereich des ersten oder des zweiten Endabschnitts umgibt.3. The component according to claim 1 or 2, wherein the third electrically conductive layer surrounds the nanostructure in a surrounding area of the first or the second end section.
4. Bauelement nach einem der Ansprüche 1 bis 3, bei dem die Dicke der dritten elektrisch leitfähigen Schicht geringer ist als die Dicke von beiden dielektrischen Teilschichten.4. The component according to one of claims 1 to 3, wherein the thickness of the third electrically conductive layer is less than the thickness of both dielectric sub-layers.
5. Bauelement nach einem der Ansprüche 1 bis 4,, ausgebildet als Feldeffekttransistor, wobei5. Component according to one of claims 1 to 4 ,, formed as a field effect transistor, wherein
• der erste Endabschnitt der Nanostruktur einen ersten Source-/Drain-Bereich und der zweite Endabschnitt der Nanostruktur einen zweiten Source-/Drain-Bereich bildet; • in der dritten elektrisch leitfähigen Schicht, welche die Gate-Elektrode des Feldef ekttransistors bildet, entlang des darin eingebrachten Durchgangslochs eine Ringstruktur aus einem elektrisch isolierenden Material als Gate-isolierender Bereich des Feldeffekttransistors angeordnet ist.• The first end section of the nanostructure forms a first source / drain region and the second end section of the nanostructure forms a second source / drain region; • In the third electrically conductive layer, which forms the gate electrode of the field effect transistor, a ring structure made of an electrically insulating material is arranged as a gate-insulating region of the field effect transistor along the through hole made therein.
6. Bauelement nach Anspruch 5 , bei dem die Mittel-Schicht eine zusätzliche elektrisch leitfähige Schicht aufweist, welche mindestens eine zusätzliche elektrisch leitfähige Schicht als zusätzliche6. The component according to claim 5, wherein the middle layer has an additional electrically conductive layer, which at least one additional electrically conductive layer as an additional
Gate-Elektrode des Feldeffekttransistors dient, wobei entlang des in der zusätzlichen elektrisch leitfähigen Schicht eingebrachten Durchgangslochs eine zusätzliche Ringstruktur aus einem elektrisch isolierenden Material- als -zusätzlicher Gate-isolierender Bereich des Feldeffekttransistors angeordnet ist.The gate electrode of the field effect transistor is used, an additional ring structure made of an electrically insulating material being arranged as an additional gate insulating region of the field effect transistor along the through hole made in the additional electrically conductive layer.
7. Bauelement nach Anspruch 5 oder 6 mit einem zusätzlichen Feldeffekttransistor über dem Feldeffekttransistor.7. The component according to claim 5 or 6 with an additional field effect transistor over the field effect transistor.
8. Bauelement nach Anspruch 7 , bei dem der Feldeffekttransistor und der zusätzliche Feldeffekttransistor miteinander als Inverter-Schaltkreis verschaltet sind.8. The component according to claim 7, wherein the field effect transistor and the additional field effect transistor are interconnected as an inverter circuit.
9. Bauelement nach einem der Ansprüche 1 bis 8, bei dem die erste und/oder die zweite elektrisch leitfähige Schicht • Tantal9. The component according to one of claims 1 to 8, wherein the first and / or the second electrically conductive layer • tantalum
• Tantalnitrid Titan Molybdän Aluminium• tantalum nitride Titanium molybdenum aluminum
Titannitrid und/oder ein ferromagnetisches Material; oder einen Schichtstapel aus diesen Materialien aufweist.Titanium nitride and / or a ferromagnetic material; or has a layer stack of these materials.
10. Bauelement nach einem der Ansprüche 6 bis 9, bei dem die dritte und/oder die zusätzliche elektrisch leitfähige Schicht10. The component according to one of claims 6 to 9, wherein the third and / or the additional electrically conductive layer
Polysilizium;polysilicon;
Tantal;tantalum;
Titan; • Niob und/oderTitanium; • niobium and / or
Aluminium aufweist.Has aluminum.
11. Bauelement nach einem der Ansprüche* 1 bis -10-, bei dem das dielektrische Material der Mittel-Schicht eines oder eine Kombination der Materialien11. The component according to any one of claims * 1 to -10-, wherein the dielectric material of the middle layer is one or a combination of the materials
• Siliziumdioxid• silicon dioxide
• Siliziumnitrid oder• silicon nitride or
• mit Kaliumionen dotiertes Siliziumdioxid aufweist.• has silicon dioxide doped with potassium ions.
12. Bauelement nach einem der Ansprüche 1 bis 11, ' bei dem die Nanostruktur12. The component according to one of claims 1 to 11, 'in which the nanostructure
• eine Nanoröhre • ein Bündel von Nanoröhren oder• a nanotube • a bundle of nanotubes or
• ein Nanostäbchen aufweist.• has a nanorod.
13. Bauelement nach Anspruch 12 , bei dem das Nanostäbchen13. The component according to claim 12, wherein the nanorod
• Silizium Germanium Indiumphosphid Galliumnitrid Galliumarsenid Zirkoniumoxid und/oder ein Metall aufweist.• silicon Germanium indium phosphide gallium nitride gallium arsenide has zirconium oxide and / or a metal.
14. Bauelement nach Anspruch 12 , bei dem die Nanoröhre eine Kohlenstoffnanoröhre eine Kohlenstoff-Bor-Nanoröhre eine Kohlenstoff-Stickstoff-Nanoröhre eine Wolframsulfid-Nanoröhre oder eine • eine Chalkogenid-Nanoröhre ist.14. The component according to claim 12, wherein the nanotube is a carbon nanotube, a carbon-boron nanotube, a carbon-nitrogen nanotube, a tungsten sulfide nanotube or a • chalcogenide nanotube.
15. Bauelement nach einem der Ansprüche 2 bis 14, bei dem die Nanostruktur eine Kohlenstoffnanoröhre ist- und bei der das Katalysatormaterial15. The component according to one of claims 2 to 14, in which the nanostructure is a carbon nanotube and in which the catalyst material
• Eisen• iron
• Kobalt und/oder• cobalt and / or
• Nickel aufweist.• Has nickel.
16. Bauelement nach einem der Ansprüche 2 bis 14, bei dem die Nanostruktur ein Galliumarsenid-Nanostäbchen ist und bei dem das Katalysatormaterial Gold au eist .16. The component according to one of claims 2 to 14, in which the nanostructure is a gallium arsenide nanorod and in which the catalyst material is gold.
17. Bauelement nach einem der Ansprüche 1 bis 16, bei dem der Teilbereich des Durchgangslochs, der von der Nanostruktur frei ist, zumindest teilweise mit einer elektrisch isolierenden Abstandshalter-Struktur gefüllt ist.17. The component according to one of claims 1 to 16, wherein the portion of the through hole that is free of the nanostructure is at least partially filled with an electrically insulating spacer structure.
18. Bauelement nach einem der Ansprüche 1 bis 17, das ausschließlich aus dielektrischem Material, metallischem Material und dem Material der Nanostruktur gebildet ist.18. Component according to one of claims 1 to 17, which consists exclusively of dielectric material, metallic Material and the material of the nanostructure is formed.
19. Bauelement nach einem der Ansprüche 1 bis 18, das auf und/oder in einem Substrat aus polykristallinem oder amorphem Material gebildet ist.19. The component according to one of claims 1 to 18, which is formed on and / or in a substrate made of polycrystalline or amorphous material.
20. Bauelement-Anordnung mit mindestens zwei nebeneinander angeordneten und/oder mit mindestens zwei übereinander angeordneten Bauelementen nach einem der Ansprüche 1 bis 19.20. Component arrangement with at least two components arranged side by side and / or with at least two components arranged one above the other according to one of claims 1 to 19.
21. Verfahren zum Herstellen eines vertikal integrierten21. Method of making a vertically integrated
Bauelements, bei demComponent in which
• eine erste elektrisch leitfähige Schicht ausgebildet wird;• a first electrically conductive layer is formed;
• eine Mittel-Schicht teilweise aus dielektrischem Material ausgebildet wird;• a middle layer is partially formed from dielectric material;
• ein Durchgangsloch in die Mittel-Schicht eingebracht wird; • eine Nanostruktur mit einem ersten Endabschnitt und mit einem zweiten Endabschnitt in dem Durchgangsloch ausgebildet wird, wobei der erste Endabschnitt mit der ersten elektrisch leitfähigen Schicht gekoppelt wird;• a through hole is made in the middle layer; A nanostructure is formed with a first end section and with a second end section in the through hole, the first end section being coupled to the first electrically conductive layer;
• eine zweite elektrisch leitfähige Schicht auf der Mittel-Schicht ausgebildet und mit dem zweiten• A second electrically conductive layer is formed on the middle layer and with the second
Endabschnitt der Nanostruktur gekoppelt wird;End portion of the nanostructure is coupled;
• die Mittel-Schicht derart ausgebildet wird, dass zwischen zwei benachbarten dielektrischen Teilschichten eine dritte elektrisch leitfähige Schicht ausgebildet wird, deren Dicke geringer ist als die Dicke von zumindest einer der dielektrischen Teilschichten. The middle layer is formed in such a way that a third electrically conductive layer is formed between two adjacent dielectric sublayers, the thickness of which is less than the thickness of at least one of the dielectric sublayers.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10250868A DE10250868B8 (en) | 2002-10-31 | 2002-10-31 | Vertically integrated field effect transistor, field effect transistor arrangement and method for producing a vertically integrated field effect transistor |
| DE10250868 | 2002-10-31 | ||
| PCT/DE2003/003587 WO2004040666A1 (en) | 2002-10-31 | 2003-10-29 | Vertical integrated component, component arrangement and method for production of a vertical integrated component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP1556909A1 true EP1556909A1 (en) | 2005-07-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP03778239A Withdrawn EP1556909A1 (en) | 2002-10-31 | 2003-10-29 | Vertical integrated component, component arrangement and method for production of a vertical integrated component |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7709827B2 (en) |
| EP (1) | EP1556909A1 (en) |
| DE (1) | DE10250868B8 (en) |
| WO (1) | WO2004040666A1 (en) |
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| CN100490180C (en) * | 2004-10-04 | 2009-05-20 | 松下电器产业株式会社 | Vertical field effect transistor and method for fabricating the same |
| US7598516B2 (en) * | 2005-01-07 | 2009-10-06 | International Business Machines Corporation | Self-aligned process for nanotube/nanowire FETs |
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| US9911743B2 (en) * | 2005-05-09 | 2018-03-06 | Nantero, Inc. | Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same |
| WO2007064334A1 (en) * | 2005-12-02 | 2007-06-07 | Advanced Micro Devices, Inc. | Polymer-based transistor devices, methods, and systems |
| EP1804286A1 (en) * | 2005-12-27 | 2007-07-04 | Interuniversitair Microelektronica Centrum | Elongate nanostructure semiconductor device |
| DE102006009721B4 (en) * | 2006-03-02 | 2011-08-18 | Qimonda AG, 81739 | Nanowire (nanowire) memory cell and method of making same |
| US8679630B2 (en) * | 2006-05-17 | 2014-03-25 | Purdue Research Foundation | Vertical carbon nanotube device in nanoporous templates |
| JP2010503981A (en) * | 2006-09-19 | 2010-02-04 | クナノ アーベー | Nanoscale field-effect transistor structure |
| US9487877B2 (en) * | 2007-02-01 | 2016-11-08 | Purdue Research Foundation | Contact metallization of carbon nanotubes |
| KR101377597B1 (en) * | 2007-03-21 | 2014-03-27 | 삼성디스플레이 주식회사 | Transistor and method of manufacturing the same |
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| US7892956B2 (en) * | 2007-09-24 | 2011-02-22 | International Business Machines Corporation | Methods of manufacture of vertical nanowire FET devices |
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| EP2161755A1 (en) * | 2008-09-05 | 2010-03-10 | University College Cork-National University of Ireland, Cork | Junctionless Metal-Oxide-Semiconductor Transistor |
| US8715981B2 (en) * | 2009-01-27 | 2014-05-06 | Purdue Research Foundation | Electrochemical biosensor |
| US8872154B2 (en) * | 2009-04-06 | 2014-10-28 | Purdue Research Foundation | Field effect transistor fabrication from carbon nanotubes |
| US8871576B2 (en) | 2011-02-28 | 2014-10-28 | International Business Machines Corporation | Silicon nanotube MOSFET |
| US9123780B2 (en) * | 2012-12-19 | 2015-09-01 | Invensas Corporation | Method and structures for heat dissipating interposers |
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| US9400862B2 (en) | 2014-06-23 | 2016-07-26 | Synopsys, Inc. | Cells having transistors and interconnects including nanowires or 2D material strips |
| US10312229B2 (en) | 2016-10-28 | 2019-06-04 | Synopsys, Inc. | Memory cells including vertical nanowire transistors |
| US10217674B1 (en) | 2017-12-13 | 2019-02-26 | International Business Machines Corporation | Three-dimensional monolithic vertical field effect transistor logic gates |
| US10325821B1 (en) * | 2017-12-13 | 2019-06-18 | International Business Machines Corporation | Three-dimensional stacked vertical transport field effect transistor logic gate with buried power bus |
| US10811322B1 (en) * | 2019-04-10 | 2020-10-20 | International Business Machines Corporation | Different gate widths for upper and lower transistors in a stacked vertical transport field-effect transistor structure |
| US11177369B2 (en) | 2019-09-25 | 2021-11-16 | International Business Machines Corporation | Stacked vertical field effect transistor with self-aligned junctions |
| CN113113356B (en) * | 2020-01-10 | 2023-05-05 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor structure and forming method thereof |
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- 2003-10-29 WO PCT/DE2003/003587 patent/WO2004040666A1/en active Application Filing
- 2003-10-29 US US10/533,550 patent/US7709827B2/en not_active Expired - Fee Related
- 2003-10-29 EP EP03778239A patent/EP1556909A1/en not_active Withdrawn
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Also Published As
| Publication number | Publication date |
|---|---|
| DE10250868B4 (en) | 2008-03-06 |
| DE10250868B8 (en) | 2008-06-26 |
| DE10250868A1 (en) | 2004-05-19 |
| WO2004040666A1 (en) | 2004-05-13 |
| US7709827B2 (en) | 2010-05-04 |
| US20060128088A1 (en) | 2006-06-15 |
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