EP1527659A1 - Method for producing electric conductive structures for use in high-frequency technology - Google Patents

Method for producing electric conductive structures for use in high-frequency technology

Info

Publication number
EP1527659A1
EP1527659A1 EP03792118A EP03792118A EP1527659A1 EP 1527659 A1 EP1527659 A1 EP 1527659A1 EP 03792118 A EP03792118 A EP 03792118A EP 03792118 A EP03792118 A EP 03792118A EP 1527659 A1 EP1527659 A1 EP 1527659A1
Authority
EP
European Patent Office
Prior art keywords
resist
etching
frequency technology
structure carrier
laser
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03792118A
Other languages
German (de)
French (fr)
Inventor
Georg Busch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP1527659A1 publication Critical patent/EP1527659A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0242—Structural details of individual signal conductors, e.g. related to the skin effect
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0179—Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles

Definitions

  • the invention relates to a method for producing high-frequency electrical line structures on a line structure carrier.
  • Chemical tin can be applied in a thickness of approx. 1 ⁇ m.
  • An amorphous resist can even be applied in a thickness of significantly less than 20 ⁇ m.
  • Previous resists had a layer thickness of significantly greater than 20 ⁇ m.
  • the much thinner resists enable lasering in a much more precise way. With an optimized manufacturing process, structures down to the 20 or 10 ⁇ m range are possible. These fine structures enable the formation of electrical line structures that can be used by high-frequency technology and replace the otherwise required conventional components with the corresponding disadvantages.
  • the line structures are designed in such a way that they form capacitors, coils and resistors that are effective in terms of high-frequency technology, each with the desired values in the smallest space.
  • the laser structuring method allows structuring z. B. compared to photo-technical processes in a relatively simple manner and still at high speed.
  • the combination of a laser structuring method with an etching method has the further advantage that entire areas can be removed simultaneously with the removal of other areas. This saves time, but is also often necessary so that the electrical line structures used in high-frequency technology are not negatively influenced by the electrical voltage fields that may be present through the full-area areas.
  • this method enables structured conductor tracks with small tolerances to be realized on the inner layers or on the outer layers of a printed circuit board as a microstrip conductor with almost any function over the entire production benefit.
  • the width of the conductor tracks can be narrowed down almost as desired. Tolerances of ⁇ +/- 5 ⁇ m are already possible today. In the past, typical tolerances were in the range of sizes of +/- 25 ⁇ m.
  • FR 4 carrier material is then used as a line structure carrier. This material is well known and inexpensive.
  • FIG. 1 shows a basic process sequence of the method according to the invention
  • Figure 2 shows a part of a larger produced by the method according to the Figure 1 circuit board structure in cross-section with a high frequency can be used industrially and a non-high-frequency-technologically usable line structure
  • Figure 3 is a ⁇ size comparison between a line structure according to the invention and according to an appropriate conventional technique
  • Figures 4 to 7 a step-by-step realization of a coil produced according to the invention
  • Figures 8 to 10 a side view of three finished
  • Figures 11 and 12 further applications according to the invention, Figures 13 to 16 application examples according to the invention with respect to a capacitor, a coil, a resistor and a moisture sensor.
  • the partial laser structured conductor pattern shown in FIG. 1 shows a line structure carrier 1 (substrate, for example an FR4 circuit board), the surface of which is pretreated in an initial coating phase in such a way that a thin layer chemical copper can be applied.
  • a further copper layer in the present exemplary embodiment with a total layer thickness of up to 20 ⁇ m, is then applied in a subsequent electrolytic coating.
  • ne thin resist layer here consisting of chemical tin with a layer thickness of approx. 1 ⁇ m, applied.
  • a structuring phase follows the coating phase.
  • the structuring is carried out according to FIG. 1 with a laser.
  • the chemical tin layer is milled away at the points at which the copper layer below the chemical tin layer is to be removed later.
  • the exposed copper layer is etched away. Finally, the chemical tin layer still present is stripped away.
  • FIG. 2 a line structure according to the invention is shown in the top left area, while a conventional line structure is shown in the middle area.
  • FIG. 3 shows size relationships when a predetermined line structure is implemented in accordance with the invention and in accordance with a conventional technique.
  • FIGS. 4 to 7 show the step-by-step realization of a coil realized with a microstrip line according to the invention.
  • a copper surface with an edge length of 1 mm is shown in FIG.
  • the copper surface is structured with a laser in the individual production steps.
  • a coil in the form of a worm can already be seen in FIG. In FIG. 6, the disruptive corner surfaces have been removed. In Figure 7 the coil is finished.
  • FIGS. 8 to 10 finished applications based on coils are shown in a respective side view.
  • the shape and size of the figures can be chosen freely. In the illustrated embodiment, the most compact form was chosen.
  • FIG. 11 shows a possible application within the circuit board below a component. In the form shown, no assembly area of the circuit board is required. The coil could also be placed anywhere in the layout.
  • FIG. 12 shows an application as capacitors below a pad (pad).
  • Layer thicknesses down z. B. up to 25 microns can capacitors in the range up to z. B. 20 pF can be realized in the smallest space. These capacitors have the additional advantage that they hardly have an inductive effect.
  • FIG. 13 shows an application with respect to an RF capacitor.
  • FIG. 14 shows an application with respect to an RF coil.
  • FIG. 15 shows an application with respect to an RF resistor and
  • FIG. 16 shows an application with regard to a moisture sensor.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metallurgy (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

The invention relates to a method for producing electric conductive structures for use in high-frequency technology on a conductive structure carrier at intervals of significantly less than 180 νm, e.g. 30 νm, using microstrip conductors. Said method combines a laser structuring method and an etching method in conjunction with a resist. The resist exhibits characteristics, at least with regard to the laser exposure during the laser structuring method, the etching exposure during the etching method and to its application on the conductive structure carrier in as thin a layer as possible, which at least correspond to those of chemical tin or an amorphic resist

Description

Beschreibungdescription
Verfahren zur Herstellung von hochfrequenztechnisch verwendbaren elektrischen LeitungsstrukturenProcess for the production of high-frequency electrical line structures
Die Erfindung betrifft ein Verfahren zur Herstellung von hochfrequenztechnisch verwendbaren elektrischen Leitungsstrukturen auf einem Leitungsstrukturtrager.The invention relates to a method for producing high-frequency electrical line structures on a line structure carrier.
In der heutigen Leiterplattentechnik sind recht große Strukturen für Resonatoren, Bandpässe, Bandsperren und auch für Spiralinduktivitäten erforderlich. Bei Anwendungen mit dünneren Isolationsschichten beispielsweise in der Größenordnung von 50 μm erlauben die bisher vorhandenen relativ hohen Lei- terbahntoleranzen für Serienprodukte oft nicht die Verwendung von Mikrostreifenleitern. Auf jeden Fall sind die Verwendungsmöglichkeiten von Mikrostreifenleitern durch die relativ hohen Leiterbahntoleranzen stark eingeschränkt. Für hochfrequenztechnische Anwendungen beispielsweise sind sie derzeit nicht geeignet. Bei Anwendungen mit Keramiken werden bei der Fertigung im Vergleich zu als Leitungsstrukturtrager dienende Leiterplatten lange Durchlaufzeiten benötigt. Außerdem ist die Ausbeute bei der Verwendung von Keramiken im Vergleich zu den Leiterplatten deutlich ungünstiger. Weiter eignet sich Keramik nicht als optischer Träger.In today's circuit board technology, quite large structures are required for resonators, bandpasses, bandstops and also for spiral inductors. In applications with thinner insulation layers, for example of the order of 50 μm, the relatively high conductor path tolerances that have been present up to now often do not allow the use of microstrip conductors for series products. In any case, the possible uses of microstrip lines are severely restricted by the relatively high conductor path tolerances. For example, they are currently not suitable for high-frequency applications. For applications with ceramics, long throughput times are required in production compared to printed circuit boards that serve as line structure supports. In addition, the yield when using ceramics is significantly less favorable compared to the printed circuit boards. Ceramic is also not suitable as an optical support.
Zur Vermeidung der großen Strukturen für Resonatoren, Bandpässe, Bandsperren und auch für Spiralinduktivitäten wurden bisher aus Platzgründen Bauteile auf der Oberfläche der Lei- terplatte eingesetzt. Durch diese Bauteile waren dann dieTo avoid the large structures for resonators, bandpasses, bandstops and also for spiral inductances, components have been used on the surface of the circuit board for reasons of space. Through these components were then
Kosten erhöht. Dazu kamen noch die Kosten für das Setzen der Bauteile auf die Leiterplatte. Ein weiterer Nachteil war, dass Bestückfläche für die Bauteile auf der Oberfläche der Leiterplatte bereitgestellt werden musste.Costs increased. Added to this was the cost of placing the components on the circuit board. Another disadvantage was that the placement area for the components had to be provided on the surface of the circuit board.
Es wurde zwar schon auf sogenannten FR4-Leiterplatten bei genügend großen vorhandenen Flächen im HF-Teil Mikrostreifen- leiter verwendet. Dies beschränkte sich aber insbesondere auf Flächenstellen, die einen vergleichsweise großen Lagenabstand von z. B.> 100 μm zu den HF-Strukturen hatten. Toleranzen in den Leiterbahnen konnten bei diesen Lagenabständen akzeptiert werden.Although it was already on so-called FR4 printed circuit boards with sufficiently large available areas in the HF section microstrip head used. However, this was particularly limited to surface areas that have a comparatively large layer spacing of z. B.> 100 microns to the RF structures. Tolerances in the conductor tracks could be accepted with these layer spacings.
Aufgabe der vorliegenden Erfindung ist es, ein Verfahren zur Herstellung von hochfrequenztechnisch verwendbaren elektrischen Leitungsstrukturen auf einem Leitungsstrukturtrager mit Lageabständen wesentlich kleiner als 100 μm unter Verwendung von Mikrostreifenleitern anzugeben.It is an object of the present invention to provide a method for producing high-frequency electrical line structures on a line structure carrier with layer spacings significantly smaller than 100 μm using microstrip lines.
Diese Aufgabe wird erfindungsgemäß durch ein Verfahren gelöst, dass die im Anspruch 1 angegebenen Verfahrensschritte aufweist.This object is achieved according to the invention by a method which has the method steps specified in claim 1.
Danach erfolgt eine Kombination von Laserstrukturierungsme- thode und Ätzmethode in Verbindung mit einem Resist mit hoher Haftfestigkeit, das zumindest bezüglich des Laserns bei der Laserstrukturierungsmethode, des Ätzens bei der Ätzmethode und seiner maximal dünnen Aufbringbarkeit auf den Leitungsstrukturtrager Eigenschaften hat, die mindestens denen von chemisch Zinn oder einem amorphen Resist entsprechen.This is followed by a combination of the laser structuring method and the etching method in conjunction with a resist with high adhesive strength which, at least with regard to lasering in the case of the laser structuring method, etching in the etching method and its maximum thin applicability to the line structure carrier, has properties which are at least those of chemical tin or an amorphous resist.
Chemisch Zinn kann in einer Stärke von ca. 1 μm aufgetragen werden. Ein amorphes Resist kann sogar nur in einer Stärke von deutlich kleiner 20um aufgetragen werden. Je dünner ein Resist aufgetragen werden kann, umso besser ist es für das vorliegende Verfahren. Bisherige Resiste wiesen eine Schicht- stärke von deutlich größer 20 μm auf. Die wesentlich dünneren Resiste ermöglichen das Lasern in einer wesentlich exakteren Weise. Bei einem optimierten Fertigungsprozess sind damit Strukturen bis in den 20- bzw. 10 μm-Bereich und kleiner möglich. Diese feinen Strukturen ermöglichen das Ausbilden von hochfrequenztechnisch verwendbaren elektrischen Leitungsstrukturen, die ansonsten benötigte herkömmliche Bauteile mit den entsprechenden Nachteilen ersetzen. Im Einzelnen können die Leitungsstrukturen in der Weise ausgebildet werden, dass sie hochfrequenztechnisch wirksame Kondensatoren, Spulen und Widerstände mit jeweils gewünschten Werten auf kleinstem Raum bilden. Die Laserstrukturierungsmethode erlaubt dabei eine Strukturierung z. B. gegenüber fototechnischen Verfahren in relativ einfacher Weise und trotzdem mit hoher Geschwindigkeit. Die Kombination von einer Laserstrukturierungsmethode mit einer Ätzmethode hat weiter den Vorteil, dass vollflächige Bereiche gleichzeitig mit dem Wegnehmen- anderer Bereiche entfernt werden können. Dies erspart Zeit, ist aber auch häufig nötig, damit die hochfrequenztechnisch verwendeten elektrischen Leitungsstrukturen durch die möglicherweise durch die vollflächigen Bereiche vorhandenen elektrischen Spannungsfelder nicht negativ beeinflusst werden.Chemical tin can be applied in a thickness of approx. 1 μm. An amorphous resist can even be applied in a thickness of significantly less than 20 μm. The thinner a resist can be applied, the better it is for the present method. Previous resists had a layer thickness of significantly greater than 20 μm. The much thinner resists enable lasering in a much more precise way. With an optimized manufacturing process, structures down to the 20 or 10 μm range are possible. These fine structures enable the formation of electrical line structures that can be used by high-frequency technology and replace the otherwise required conventional components with the corresponding disadvantages. In detail can the line structures are designed in such a way that they form capacitors, coils and resistors that are effective in terms of high-frequency technology, each with the desired values in the smallest space. The laser structuring method allows structuring z. B. compared to photo-technical processes in a relatively simple manner and still at high speed. The combination of a laser structuring method with an etching method has the further advantage that entire areas can be removed simultaneously with the removal of other areas. This saves time, but is also often necessary so that the electrical line structures used in high-frequency technology are not negatively influenced by the electrical voltage fields that may be present through the full-area areas.
Insgesamt lassen sich durch dieses Verfahren strukturierte Leiterbahnen mit geringen Toleranzen auf den Innenlagen oder auch auf den Außenlagen einer Leiterplatte als Mikrostreifen- leiter mit nahezu beliebigen Funktionen über den gesamten Fertigungsnutzen realisieren. Die Leiterbahnenbreite lässt sich fast beliebig eingrenzen. Heute sind bereits Toleranzen von < +/- 5 μm möglich. Früher lagen typische Toleranzen im Bereich der Größen von +/-25 μm.Overall, this method enables structured conductor tracks with small tolerances to be realized on the inner layers or on the outer layers of a printed circuit board as a microstrip conductor with almost any function over the entire production benefit. The width of the conductor tracks can be narrowed down almost as desired. Tolerances of <+/- 5 μm are already possible today. In the past, typical tolerances were in the range of sizes of +/- 25 μm.
Vorteilhafte Ausgestaltungen der Erfindung sind Gegenstand von Unteransprüchen.Advantageous embodiments of the invention are the subject of dependent claims.
Danach wird als ein Leitungsstrukturtrager ein FR 4-Träger- material verwendet. Dieses Material ist bekannt und kosten- günstig.An FR 4 carrier material is then used as a line structure carrier. This material is well known and inexpensive.
Der Vorteil von chemisch Zinn oder von einem amorphen Resist ist, dass in Verbindung mit. einer Kombination aus einer Laserstrukturierungsmethode und einer Ätzmethode hochfrequenz- technisch verwendbare elektrische .Leitungsstrukturen realisierbar sind. Nachfolgend wird die Erfindung anhand einer Zeichnung näher erläutert. Darin zeigen:The advantage of chemical tin or of an amorphous resist is that in connection with. a combination of a laser structuring method and an etching method that can be used for high-frequency technical electrical line structures. The invention is explained in more detail below with reference to a drawing. In it show:
Figur 1 einen prinzipiellen Verfahrensablauf des Verfahrens gemäß der Erfindung,FIG. 1 shows a basic process sequence of the method according to the invention,
Figur 2 einen Teil einer größeren nach dem Verfahren gemäß der Figur 1 hergestellten Leiterplattenstruktur im Querschnitt mit einer hochfrequenztechnisch verwendbaren und einer nicht hochfrequenztechnisch verwendbaren Leitungsstruktur, Figur 3 einen ■ Größenvergleich zwischen einer Leitungsstruktur gemäß der Erfindung und gemäß einer entsprechenden herkömmlichen Technik,2 shows a part of a larger produced by the method according to the Figure 1 circuit board structure in cross-section with a high frequency can be used industrially and a non-high-frequency-technologically usable line structure, Figure 3 is a ■ size comparison between a line structure according to the invention and according to an appropriate conventional technique,
Figuren 4 bis 7 eine schrittweise Realisierung einer erfindungsgemäß hergestellten Spule, Figuren 8 bis 10 eine seitliche Darstellung dreier fertigerFigures 4 to 7 a step-by-step realization of a coil produced according to the invention, Figures 8 to 10 a side view of three finished
Anwendungen in einer Leiterplatte, die ge- maß der Erfindung realisiert worden sind,Applications in a printed circuit board which have been implemented in accordance with the invention
Figuren 11 und 12 weitere Anwendungen gemäß der Erfindung, Figuren 13 bis 16 Anwendungsbeispiele gemäß der Erfindung bezüglich eines Kondensators, einer Spule, eines Widerstandes und eines Feuchtesen- sors.Figures 11 and 12 further applications according to the invention, Figures 13 to 16 application examples according to the invention with respect to a capacitor, a coil, a resistor and a moisture sensor.
Das in der Figur 1 gezeigte partielle Laser strukturierte Leiterbild (PHDI: Partial High Density Interconnection) zeigt einen Leitungsstrukturtrager 1 (Substrat, z.B. eine FR4- Leiterplatte) , dessen Oberfläche in einer anfänglichen Beschichtungphase in einer solchen entsprechenden Weise vorbehandelt wird, dass eine dünne Lage chemisch Kupfer aufgebracht werden kann. In einer nachfolgenden elektrolytischen Beschichtung wird dann eine weitere Kupferschicht, in dem vorliegenden Ausführungsbeispiel mit einer Gesamtschichtstärke von bis zu 20 μm, aufgebracht. Im Anschluss daran wird ei- ne dünne Resist-Schicht, hier bestehend aus chemisch Zinn mit einer Schichtstärke von ca. 1 μm, aufgebracht.The partial laser structured conductor pattern shown in FIG. 1 (PHDI: Partial High Density Interconnection) shows a line structure carrier 1 (substrate, for example an FR4 circuit board), the surface of which is pretreated in an initial coating phase in such a way that a thin layer chemical copper can be applied. A further copper layer, in the present exemplary embodiment with a total layer thickness of up to 20 μm, is then applied in a subsequent electrolytic coating. Following this, ne thin resist layer, here consisting of chemical tin with a layer thickness of approx. 1 μm, applied.
Nach der Beschichtungsphase folgt eine Strukturierungsphase. Die Strukturierung wird gemäß der Figur 1 mit einem Laser durchgeführt. In der Strukturierungsphase wird mit dem Laser an denjenigen Stellen, an denen später die unterhalb der chemisch Zinn-Schicht liegende Kupferschicht abgetragen werden soll, die chemisch Zinn-Schicht weggefräst.A structuring phase follows the coating phase. The structuring is carried out according to FIG. 1 with a laser. In the structuring phase, the chemical tin layer is milled away at the points at which the copper layer below the chemical tin layer is to be removed later.
Nach der Strukturierungsphase wird, wie gerade angedeutet, die freigelegte Kupfer-Schicht weggeätzt. Abschließend wird die noch vorhandene chemisch Zinn-Schicht weggestrippt.After the structuring phase, as just indicated, the exposed copper layer is etched away. Finally, the chemical tin layer still present is stripped away.
In der Figur 2 ist im linken oberen Bereich eine erfindungsgemäße Leitungsstruktur gezeigt, während im mittleren Bereich eine herkömmliche Leitungsstruktur gezeigt ist.In FIG. 2, a line structure according to the invention is shown in the top left area, while a conventional line structure is shown in the middle area.
Figur 3 zeigt Größenverhältnisse, wenn eine vorgegebene Lei- tungsstruktur gemäß der Erfindung und gemäß einer herkömmlichen Technik realisiert ist.FIG. 3 shows size relationships when a predetermined line structure is implemented in accordance with the invention and in accordance with a conventional technique.
In den Figuren 4 bis 7 ist die schrittweise Realisierung einer mit einem Mikrostreifenleiter realisierte Spule gemäß der Erfindung wiedergegeben. Dabei ist in der Figur 4 eine Kupferfläche mit einer Kantenlänge von 1 mm dargestellt. Die Kupferfläche wird in den einzelnen Fertigungsschritten mit einem Laser strukturiert. In der Figur 5 ist bereits eine Spule in Form einer Schnecke zu erkennen. In der Figur 6 wur- den die störenden Eckflächen entfernt. In der Figur 7 ist die Spule fertig.FIGS. 4 to 7 show the step-by-step realization of a coil realized with a microstrip line according to the invention. A copper surface with an edge length of 1 mm is shown in FIG. The copper surface is structured with a laser in the individual production steps. A coil in the form of a worm can already be seen in FIG. In FIG. 6, the disruptive corner surfaces have been removed. In Figure 7 the coil is finished.
In den Figuren 8 bis 10 sind nochmals in einer jeweiligen seitliche Darstellung fertige Anwendungen basierend hier je- weils auf Spulen dargestellt. Die Form und Größe der Figuren können beliebig gewählt werden. In den dargestellten Ausführungsbeispiel wurde jeweils die kompakteste Form gewählt. In der Figur 11 ist eine mögliche Anwendung innerhalb der Leiterplatte unterhalb eines Bauteils gezeigt. Bei der dargestellten Form wird keine Bestückfläche der Leiterplatte benö- tigt. Die Spule könnte auch an beliebigen anderen Stellen im Layout untergebracht sein.In FIGS. 8 to 10, finished applications based on coils are shown in a respective side view. The shape and size of the figures can be chosen freely. In the illustrated embodiment, the most compact form was chosen. FIG. 11 shows a possible application within the circuit board below a component. In the form shown, no assembly area of the circuit board is required. The coil could also be placed anywhere in the layout.
In der Figur 12 ist eine Anwendung als Kondensatoren unterhalb eines Anschlussflächenstückes (Pad) gezeigt. Durch die Verwendung von geeigneten Isolierschichten und geringenFIG. 12 shows an application as capacitors below a pad (pad). By using suitable insulating layers and low
Schichtdicken herunter z. B. bis zu 25 μm können so Kondensatoren im Bereich bis zu z . B. 20 pF auf kleinstem Raum realisiert sein. Diese Kondensatoren haben zusätzlich den Vorteil, dass sie kaum induktiv wirken.Layer thicknesses down z. B. up to 25 microns can capacitors in the range up to z. B. 20 pF can be realized in the smallest space. These capacitors have the additional advantage that they hardly have an inductive effect.
Figur 13 zeigt eine Anwendung bezüglich eines HF- Kondensators. Figur 14 zeigt eine Anwendung bezüglich einer HF-Spule. Figur 15 zeigt eine Anwendung bezüglich eines HF- Widerstandes und Figur 16 zeigt eine Anwendung bezüglich ei- nes Feuchtesensors. FIG. 13 shows an application with respect to an RF capacitor. FIG. 14 shows an application with respect to an RF coil. FIG. 15 shows an application with respect to an RF resistor and FIG. 16 shows an application with regard to a moisture sensor.

Claims

Patentansprüche claims
1. Verfahren zur Herstellung von hochfrequenztechnisch verwendbaren elektrischen Leitungsstrukturen auf einem Leitungs- strukturträger, dadurch gekennzeichnet, dass eine Kombination von Laserstrukturierungsmethode und Ätzmethode angewandt wird unter Einsatz eines Resistes, das zumindest bezüglich des Laserns bei der Laserstrukturierungsmethode, des Ätzens bei der Ätzmethode und seiner maximal dünnen Auf- bringbarkeit auf den Leitungsstrukturtrager Eigenschaften hat, die mindestens denen von chemisch Zinn oder einem amorphen Resist entsprechen.1. A method for producing high-frequency technical usable electrical line structures on a line structure carrier, characterized in that a combination of laser structuring method and etching method is used using a resist, at least with respect to lasering in the laser structuring method, etching in the etching method and its maximum thin applicability on the line structure carrier has properties which at least correspond to those of chemical tin or an amorphous resist.
2. Verfahren nach Anspruch 1, dadurch gekennzeich- net, dass als Leitungsstrukturtrager ein FR4-2. The method according to claim 1, characterized in that an FR4-
Trägermaterial verwendet wird.Backing material is used.
3. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass als Resist chemisch Zinn oder ein amor- phes Resist verwendet wird.3. The method according to claim 1 or 2, characterized in that tin or an amorphous resist is used chemically as a resist.
4. Verfahren nach einem der vorherigen Ansprüche, dadurch gekennzeichnet, dass zumindest in einem Umfeld von hochfrequenztechnisch verwendbaren elektrischen Leitungs- Strukturen zumindest großflächig verbleibende elektrische Leitungsstrukturen beseitigt werden. 4. The method according to any one of the preceding claims, characterized in that at least in a surrounding area of electrical line structures which can be used by high-frequency technology, electrical line structures remaining at least over a large area are eliminated.
EP03792118A 2002-08-08 2003-07-03 Method for producing electric conductive structures for use in high-frequency technology Withdrawn EP1527659A1 (en)

Applications Claiming Priority (3)

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DE10236466 2002-08-08
DE10236466A DE10236466A1 (en) 2002-08-08 2002-08-08 Production of high frequency electrical conducting structures on a conducting structure support comprises using a combination of laser structuring methods and etching methods with a resist which is thinly applied during the methods
PCT/DE2003/002227 WO2004019665A1 (en) 2002-08-08 2003-07-03 Method for producing electric conductive structures for use in high-frequency technology

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CN103917052B (en) * 2013-12-30 2017-06-13 天津市德中技术发展有限公司 A kind of method of use laser direct structuring technique processing circuit board
CN112822853A (en) * 2020-12-30 2021-05-18 深圳市百柔新材料技术有限公司 Method for manufacturing circuit board circuit by laser etching
DE102021211807A1 (en) 2021-10-20 2023-04-20 Zf Friedrichshafen Ag Device and method for detecting moisture on a printed circuit board
JP7461437B1 (en) 2022-10-21 2024-04-03 旭東 陳 Subtractive method for manufacturing circuit boards with fine interconnections

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DE3732249A1 (en) * 1987-09-24 1989-04-13 Siemens Ag Method for fabricating three-dimensional printed-circuit boards
EP0530564A1 (en) * 1991-09-05 1993-03-10 Siemens Aktiengesellschaft Method for producing circuit boards
US5474956A (en) * 1995-03-14 1995-12-12 Hughes Aircraft Company Method of fabricating metallized substrates using an organic etch block layer
US5929729A (en) * 1997-10-24 1999-07-27 Com Dev Limited Printed lumped element stripline circuit ground-signal-ground structure
ATE228753T1 (en) * 1999-03-16 2002-12-15 Siemens Ag METHOD FOR MAKING THROUGH-CONTACT HOLES IN AN ELECTRICALLY INSULATING BASE MATERIAL PROVIDED WITH METAL LAYERS ON BOTH SIDES

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DE10236466A1 (en) 2004-02-19

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