EP1522101A1 - Method for the production of mos transistors - Google Patents

Method for the production of mos transistors

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Publication number
EP1522101A1
EP1522101A1 EP03720179A EP03720179A EP1522101A1 EP 1522101 A1 EP1522101 A1 EP 1522101A1 EP 03720179 A EP03720179 A EP 03720179A EP 03720179 A EP03720179 A EP 03720179A EP 1522101 A1 EP1522101 A1 EP 1522101A1
Authority
EP
European Patent Office
Prior art keywords
extremely low
transistors
low leakage
spacers
leakage currents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP03720179A
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German (de)
French (fr)
Inventor
Stefan Guenther
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STMicroelectronics NV
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STMicroelectronics NV
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Filing date
Publication date
Application filed by STMicroelectronics NV filed Critical STMicroelectronics NV
Publication of EP1522101A1 publication Critical patent/EP1522101A1/en
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Definitions

  • the invention relates to a method both for the production of MOS transistors with extremely low leakage currents at the pn junctions and of logic switching transistors whose gates are laterally delimited by spacers in a p-substrate or a p-well in an n-substrate.
  • the poly / silicide / salicide gates are provided with spacers in order to limit the leakage currents.
  • Different materials meet in the restricted areas. As a rule, however, these materials are not exclusively silicon, polysilicon, silicon oxides and silicon nitrides. These materials naturally have different material properties, such as different coefficients of expansion.
  • mechanical stress occurs at the spacer edges, which ultimately leads to increased leakage currents.
  • These increased leakage currents are additionally initiated or reinforced by the implantation of high (eg> El5 / cm 2 ) As doses.
  • the invention is therefore based on the object of providing a method for producing MOS transistors which have extremely low leakage currents and which permits n-channel switching transistors in parallel.
  • the object on which the invention is based is achieved in a method of the type mentioned at the outset by first performing an LDD ion implantation over the gate edges in order to form an LDD region, followed by spacer formation on all gate edges or in another Execution only selectively on the n-channel switching transistors, in which case the spacers are removed by a masked anisotropic etching step, which is characterized by a high selectivity towards the gate and substrate materials including their cover layers, the n-channel transistors extremely low leakage currents only connected via LDD prayer, the associated pn areas not with an (As- High-dose implantation and covered with an oxide layer.
  • Phosphorus or boron / arsenic are preferably implanted in a double implantation with the LDD ion implantation.
  • a second embodiment of the invention provides that the n-channel switching transistors are free of photoresist before the etching step.
  • the spacer formation is thus carried out only for them, via which a high-dose S / D implantation can take place at a later point in the process.
  • the surface of the entire transistor structure is covered with a thermal oxide or a CVD layer in order to ensure adequate protection of the transistor structure in subsequent manufacturing steps.
  • This layer can be used for conventional S / D implantations for the switching transistors.
  • the contacting of the S / D regions (source / drain regions) of the n-channel transistors with extremely low leakage currents takes place via the opening of the insulation layer gate / metal-1, contact, and the subsequent metal deposition and structuring.
  • a contact implantation can take place before or after the contact opening.
  • the packing density is increased, the parasitic Reduced effects, increased performance, and increased scalability and thus reduced costs.
  • FIG. 6 the structure corresponding to FIG. 4 with an oxide cover
  • n-channel transistors 1, 2 with a typical CMOS structure after the LDD implantation, with phosphorus implanted over the edges of the gates 3, 4 or also in a boron / arsenic double implantation and thus LDD- Areas 6 were formed.
  • Both a p-type substrate and a p-type well in an n-type substrate can be considered as the base material 5.
  • Transistors 2 e.g. to be used for normal digital / switching functions.
  • the area in which the n-channel switching transistors 2 are located is covered, for example with a first photoresist 9 or another suitable etching protection layer (FIG. 3).
  • FIG. 5 shows a subsequent cover 10 with a CVD layer. Another variant is shown in FIG. 6, where a cover 11 with a thermal oxide has been reached.
  • the MOS transistor with extremely low leakage current is connected exclusively via LDD regions 6 within the active regions.
  • N-channel switching transistors are implemented in parallel
  • the transistor structures are covered with an oxide layer 11 before subsequent implantations or depositions, or there is a (moist) thermal oxidation of the surface of the transistor structures.
  • n-channel transistor with extremely low leakage current "normal” n-channel transistor / n-channel switching transistor gate
  • n-channel transistor with extremely low leakage current gate "normal” n-channel transistor / n-channel switching transistor base material / p-substrate or p-well in n-substrate LDD area nt-S / D area of "normal” n-channel transistor / n-channel switching transistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention relates to a method for the production of MOS transistors with extremely low leakage currents at the pn junctions and logic/switching transistors (2), whose gates (3) are laterally defined by spacers (8), a p- substrate or a p-trough in an n-substrate (5). The aim of the invention is to provide a method for the production of MOS transistors with extremely low leakage currents and allows for parallel logic/switching transistors. This is achieved by initially carrying out an LDD ion implementation via the edges of the gates in order to form an LDD area (6) and by subsequently removing the spacers (8) by means of an anistropic etching step exhibiting high selectivity in relation to the gate and substrate materials including the covering layers thereof or by covering the MOS transistors with extremely low leakage currents prior to isotropic spacer production such that the spacers (8) are formed exclusively on the edges of the gates of the logic/switching transistors (2) whereby the MOS transistors with extremely low leakage currents remain exclusively connected via the LDD area (6) and no high dose implantation (As) in the S/D areas of said MOS transistors with extremely low leakage currents occurs.

Description

Verfahren zur Herstellung von MOS-Transistoren Process for the production of MOS transistors
Die Erfindung betrifft ein Verfahren sowohl zur Herstellung von MOS-Transistoren mit extrem geringen Leckströmen an den pn-Übergängen als auch von Logik- Schalttransistoren deren Gates seitlich mit Spacern begrenzt sind in einem p- Substrat oder einer p- Wanne in einem n-Substrat.The invention relates to a method both for the production of MOS transistors with extremely low leakage currents at the pn junctions and of logic switching transistors whose gates are laterally delimited by spacers in a p-substrate or a p-well in an n-substrate.
Bei den Standard DSM-MOS-Transistoren (DSM: Deep Submicron Silicon Technology) werden die Poly/Silizide/Salizide-Gates mit Spacern versehen, um die Leckströme zu begrenzen. Dabei treffen verschiedene Materialien in den Sperrgebieten auf- einander. Diese Materialien sind in der Regel aber nicht ausschließlich Silizium, Polysilizium, Siliziumoxide und Siliziumnitride. Diese Materialien besitzen naturgemäß unterschiedliche Materialeigenschaften, wie beispielsweise unterschiedliche Ausdehnungskoeffizienten. Im Zusammenhang mit den Abscheidete peraturen und den Temperaturbelastungen welche insbesondere die Spacer im Laufe des Gesamtherstellungs- prozesses erfahren, tritt an den Spacerkanten u.a. ein mechanischer Stress auf, der schließlich zu erhöhten Leckströmen führt. Diese erhöhten Leckströme werden zusätzlich ini- tiiert bzw. verstärkt durch die Implantation von hohen (z.B.>El5/cm2) As-Dosen.With the standard DSM-MOS transistors (DSM: Deep Submicron Silicon Technology), the poly / silicide / salicide gates are provided with spacers in order to limit the leakage currents. Different materials meet in the restricted areas. As a rule, however, these materials are not exclusively silicon, polysilicon, silicon oxides and silicon nitrides. These materials naturally have different material properties, such as different coefficients of expansion. In connection with the deposited temperatures and the temperature loads which the spacers in particular experience in the course of the overall manufacturing process, mechanical stress occurs at the spacer edges, which ultimately leads to increased leakage currents. These increased leakage currents are additionally initiated or reinforced by the implantation of high (eg> El5 / cm 2 ) As doses.
Darüber hinaus können Gitterdefekte durch das begrenzte thermische Budget des Herstellungsprozesses nicht vollstän- dig ausgeheilt werden, wodurch ebenfalls Leckströme generiert werden können. Die pn-Leckströme sind für digitale CMOS-Applikationen durchaus akzeptabel, nicht jedoch für a- nalog dynamische Speicher (z.B. Bildsensoren). Diese Leckströme würden bei den Bildsensoren die Bildinformation er- heblich verfälschen. Um diese Leckströme zu reduzieren, ist es bekannt, bei Beibehaltung der Spacer und der As-Hochdosisimplantation eine zusätzliche tiefe P-Diffusion auszuführen. Damit werden die Ursachen für den Leckstrom nicht beseitigt, aber die Auswir- kungen des Leckstromes reduziert. Die Defekte liegen nun innerhalb von n-Gebieten, wo sie größtenteils inaktiv sind. Eine statistische Anzahl dieser Defekte „wächst" allerdings aus den zusätzlichen P-Diffusionsgebieten heraus und ist damit wieder aktiv. Dies zu verhindern ist schwer beherrsch- bar, so dass signifikante und wenig kalkulierbare Ausbeuterisiken verbleiben und eintreten.In addition, lattice defects cannot be completely cured due to the limited thermal budget of the manufacturing process, which can also generate leakage currents. The pn leakage currents are perfectly acceptable for digital CMOS applications, but not for analog dynamic memories (eg image sensors). These leakage currents would significantly distort the image information in the image sensors. In order to reduce these leakage currents, it is known to carry out an additional deep P-diffusion while maintaining the spacers and the high-dose implantation. This does not eliminate the causes of the leakage current, but it does reduce the effects of the leakage current. The defects are now within n-areas, where they are mostly inactive. However, a statistical number of these defects "grows" out of the additional P diffusion areas and is thus active again. It is difficult to prevent this from being controlled, so that significant and unpredictable exploitation risks remain and occur.
Da die Diffusion aber nicht nur vertikal, sondern auch lateral verläuft, führt das zu größeren Kanallängen, geringeren Packungsdichten, zur Vergrößerung parasitärer Elemente (z.B. Kapazitäten, Laufzeiten) , geringerer Performance und letztendlich zu höheren Kosten.However, since the diffusion is not only vertical, but also lateral, this leads to longer channel lengths, lower packing densities, increased parasitic elements (e.g. capacities, run times), lower performance and ultimately higher costs.
Der Erfindung liegt daher die Aufgabe zugrunde, ein Verfah- ren zur Herstellung von MOS-Transistoren zu schaffen, die extrem geringe Leckströmen aufweisen und das parallel n- Kanal-Schalttransistoren zuläßt.The invention is therefore based on the object of providing a method for producing MOS transistors which have extremely low leakage currents and which permits n-channel switching transistors in parallel.
Die der Erfindung zugrunde liegende Aufgabenstellung wird bei einem Verfahren der eingangs genannten Art dadurch gelöst, dass zunächst eine LDD-Ionenimplantation über die Gatekanten durchgeführt wird, um ein LDD-Gebiet zu bilden, anschließend erfolgt die Spacerbildung an allen Gatekanten o- der in einer anderen Ausführung nur selektiv an den n-Kanal- Schalttransistoren wobei im ersteren Fall die Spacer durch einen maskierten anisotropen Ätzschritt, der sich durch eine hohe Selektivität gegenüber den Gate- und Substratmaterialien einschließlich ihrer Abdeckschichten auszeichnet ist, entfernt werden, die n-Kanal-Transistoren mit extrem niedri- gen Leckströmen ausschließlich über LDD-Geb ete angeschlossen, die zugehörigen pn-Gebiete nicht mit einer (As- Hochdosis-Implantation versehen und mit einer Oxidschicht abgedeckt sind.The object on which the invention is based is achieved in a method of the type mentioned at the outset by first performing an LDD ion implantation over the gate edges in order to form an LDD region, followed by spacer formation on all gate edges or in another Execution only selectively on the n-channel switching transistors, in which case the spacers are removed by a masked anisotropic etching step, which is characterized by a high selectivity towards the gate and substrate materials including their cover layers, the n-channel transistors extremely low leakage currents only connected via LDD prayer, the associated pn areas not with an (As- High-dose implantation and covered with an oxide layer.
Vorzugsweise werden mit der LDD-Ionenimplantation Phosphor oder Bor/Arsen in einer DoppelImplantation implantiert.Phosphorus or boron / arsenic are preferably implanted in a double implantation with the LDD ion implantation.
Eine zweite Ausgestaltung der Erfindung sieht vor, dass die n-Kanal-Schalt-Transistoren vor dem Ätzschritt frei von Photoresist sind. Damit erfolgt nur für sie die Spacerbil- düng, über die zu einem späteren Prozeßzeitpunkt eine Hochdosis-S/D- Implantation erfolgen kann.A second embodiment of the invention provides that the n-channel switching transistors are free of photoresist before the etching step. The spacer formation is thus carried out only for them, via which a high-dose S / D implantation can take place at a later point in the process.
Nach dem Ätzschritt wird die Oberfläche der gesamten Transistorstruktur mit einer thermischen Oxid- oder einer CVD- Schicht abgedeckt, um einen ausreichenden Schutz der Transistorstruktur bei nachfolgenden Fertigungsschritten sicher zu stellen.After the etching step, the surface of the entire transistor structure is covered with a thermal oxide or a CVD layer in order to ensure adequate protection of the transistor structure in subsequent manufacturing steps.
Durch diese Schicht können konventionelle S/D-Implantationen für die Schalttransistoren erfolgen.This layer can be used for conventional S / D implantations for the switching transistors.
Die Kontaktierung der S/D-Gebiete (Source/Drain-Gebiete) der n-Kanal-Transistoren mit extrem niedrigen Leckströmen erfolgt über die Öffnung der Isolationsschicht Gate/Metall-1, Kontakt, und der nachfolgenden Matallabscheidung und Strukturierung. Zur besseren Kontaktierung kann eine Kontaktimplantation vor oder nach der Kontaktöffnung erfolgen.The contacting of the S / D regions (source / drain regions) of the n-channel transistors with extremely low leakage currents takes place via the opening of the insulation layer gate / metal-1, contact, and the subsequent metal deposition and structuring. For better contacting, a contact implantation can take place before or after the contact opening.
Vorteile der Erfindung sind insbesondere darin zu sehen, dass mit einfachen Mitteln die störenden pn-Leckstöme beseitigt werden und damit eine verlässliche Lösung der der Erfindung zugrunde liegenden Aufgabenstellung im Sinne von Prozessstabilität, Reproduzierbarkeit und Ausbeute geschaffen wird.Advantages of the invention are to be seen in particular in that the disruptive pn leakage currents are eliminated with simple means and thus a reliable solution to the problem underlying the invention in terms of process stability, reproducibility and yield is created.
Weiterhin wird die Packungsdichte erhöht, die parasitären Effekte verringert, die Performance erhöht, sowie die weitere Skalierungsfähigkeit erhöht und damit die Kosten reduziert.Furthermore, the packing density is increased, the parasitic Reduced effects, increased performance, and increased scalability and thus reduced costs.
Die Erfindung soll nachfolgend an einem Ausführungsbeispiel näher erläutert werden.The invention will be explained in more detail using an exemplary embodiment.
In den zugehörigen Zeichnungsfiguren zeigen:In the associated drawing figures show:
Fig. 1: eine schematische Darstellung von n-Kanal-1: a schematic representation of n-channel
Transistoren mit einer typischen CMOS-Struktur nach der LDD-Implantation;Transistors with a typical CMOS structure after LDD implantation;
Fig. 2: eine schematische Darstellung von n-Kanal- Transistoren mit einer typischen CMOS-Struktur nach der LDD-I plantation und Spacerrealisierung an allen Gatekanten2: a schematic representation of n-channel transistors with a typical CMOS structure after the LDD-I plantation and spacer implementation on all gate edges
Fig. 3: einen mit einer Photolackschicht abgedeckten „kon- ventionellen" n-Kanaltransistor (n-kanal-3: a "conventional" n-channel transistor covered with a photoresist layer (n-channel
Schalttransistor) ;Switching transistor);
Fig. 4: die Struktur entsprechend Fig. 2 nach der anisotropen Ätzung der Spacer;4: the structure corresponding to FIG. 2 after the anisotropic etching of the spacers;
Fig. 5: die Struktur entsprechend Fig. 4 mit einer CVD- Abdeckung;5: the structure corresponding to FIG. 4 with a CVD cover;
Fig. 6: die Struktur entsprechend Fig. 4 mit einer Oxidab- deckung;FIG. 6: the structure corresponding to FIG. 4 with an oxide cover;
Fig. 7: die Struktur entsprechend Fig. 5 mit einer Oxidisolation Gate/Metall, Kontakten und Kontaktfensterimplantation; und7: the structure corresponding to FIG. 5 with a gate / metal oxide insulation, contacts and contact window implantation; and
Fig. 8: die Struktur entsprechend Fig. 7 mit Metallisie- rung,8: the structure corresponding to FIG. 7 with metallized tion,
Fig. 1 zeigt n-Kanaltransistoren 1, 2 mit einer typischen CMOS-Struktur nach der LDD-Implantation, mit über die Kanten der Gates 3 , 4 Phosphor oder auch in einer Bor / Arsen Doppelimplantation in das Basismaterial 5 implantiert wurde und somit LDD-Gebiete 6 gebildet wurden. Als Basismaterial 5 kommt dabei sowohl ein p-Substrat oder auch eine p-Wanne in einem n-Substrat in Betracht.1 shows n-channel transistors 1, 2 with a typical CMOS structure after the LDD implantation, with phosphorus implanted over the edges of the gates 3, 4 or also in a boron / arsenic double implantation and thus LDD- Areas 6 were formed. Both a p-type substrate and a p-type well in an n-type substrate can be considered as the base material 5.
Fig. 2 zeigt die Struktur nac der Spacerrealisierung an den Gates 3 , 4.2 shows the structure according to the spacer implementation at the gates 3, 4.
Häufig ist es sinnvoll, neben den n-Kanal-Transistoren 1 mit extrem geringen pn-Leckströmen auch „normale" n-Kanal-It is often advisable to use "normal" n-channel transistors 1 with extremely low pn leakage currents in addition to the n-channel transistors 1.
Transistoren 2 z.B. für normale Digital/ Schaltfunktionen zu verwenden.Transistors 2 e.g. to be used for normal digital / switching functions.
Aus diesem Grund wird der Bereich, in dem sich die n-Kanal- Schalttransistoren 2 befinden,- beispielsweise mit einem ersten Photoresist 9, oder einer anderen geeigneten Ätzschutzschicht, abgedeckt (Fig. 3) .For this reason, the area in which the n-channel switching transistors 2 are located is covered, for example with a first photoresist 9 or another suitable etching protection layer (FIG. 3).
Anschließend erfolgt ein anisotroper Ätzschritt mit hoher Selektivität gegenüber den Gate- μnd Substratmaterialien einschließlich ihrer Abdeckschichten, um die Spacer 8 in den gewünschten Gebieten zu entfernen (Fig. 4) , in denen geringste pn-Leckströme erforderlich sind. Anstelle der nachträglichen Entfernung der Spacer 8 kann auch selektiv bei vorhergehenden Herstellungsschritten bei den n-Kanal- Transistoren 1 die einen niedrigen Leckstrom ausfweisen sollen, darauf verzichtet werden, Spacer 8 herzustellen.This is followed by an anisotropic etching step with high selectivity towards the gate and substrate materials, including their cover layers, in order to remove the spacers 8 in the desired areas (FIG. 4) in which the lowest pn leakage currents are required. Instead of the subsequent removal of the spacers 8, it is also possible to selectively dispense with the production of spacers 8 in the case of previous production steps for the n-channel transistors 1 which are to have a low leakage current.
In Fig. 5 ist eine nachfolgende Abdeckung 10 mit einer CVD- Schicht dargestellt. Eine andere Variante zeigt Fig. 6, wo eine Abdeckung 11 mit einem thermischen Oxid erreicht worden ist.5 shows a subsequent cover 10 with a CVD layer. Another variant is shown in FIG. 6, where a cover 11 with a thermal oxide has been reached.
Fig. 7 zeigt die Struktur nach S/D-Implantation 7, Oxidisolation 18, Kontaktöffnung 16 und Kontaktfensterimplantation 15.7 shows the structure after S / D implantation 7, oxide insulation 18, contact opening 16 and contact window implantation 15.
Fig. 8 stellt die Struktur nach der ersten Metallstrukturie- rung und Kontaktierung dar.8 shows the structure after the first metal structuring and contacting.
Das erfindungsgemäße Verfahren lässt sich wie folgt zusammenfassen:The method according to the invention can be summarized as follows:
Der Anschluss des MOS-Transistors mit extrem niedrigem Leck- ström erfolgt ausschließlich über LDD-Gebiete 6 innerhalb der aktiven Gebiete.The MOS transistor with extremely low leakage current is connected exclusively via LDD regions 6 within the active regions.
Es erfolgt eine selektive Entfernung / Nichtrealisierung der Spacer 8 an den Gatekanten des MOS-Transistors mit extrem niedrigem LeckstromThere is a selective removal / non-implementation of the spacers 8 at the gate edges of the MOS transistor with an extremely low leakage current
Es erfolgt keine As-Hochdosisimplantationen an den oder in der Nähe der Gatekanten sowie in den pn-Gebieten des MOS- Transistors mit extrem niedrigem LeckstromThere is no high-dose As implantation at or near the gate edges and in the pn regions of the MOS transistor with extremely low leakage current
Parallel werden n-Kanal-Schalttransistoren realisiertN-channel switching transistors are implemented in parallel
Die Transistorstrukturen werden vor nachfolgenden Implantationen oder Abscheidungen mit einer Oxidschicht 11 bedeckt, oder es erfolgt eine (feuchte) thermische Oxidation der 0- berflache der Transistorstrukturen. Verfahren zur Herstellung von MOS-TransistorenThe transistor structures are covered with an oxide layer 11 before subsequent implantations or depositions, or there is a (moist) thermal oxidation of the surface of the transistor structures. Process for the production of MOS transistors
BezugszeichenlisteLIST OF REFERENCE NUMBERS
n-Kanal-Transistor mit extrem niedrigem Leckstrom „normaler" n-Kanal-Transistor / n-Kanal- Schalttransistor Gate n-Kanal-Transistor mit extrem niedrigem Leckstrom Gate „normaler" n-Kanal-Transistor / n-Kanal- Schalttransistor Basismaterial / p-Substrat oder p-Wanne in n-Substrat LDD-Gebiet n-t- S/D- Gebiet von „normaler" n-Kanal-Transistor / n- Kanal-Schalttransistoren Spacer Photoresistl / erster Photoresist CVD-Schicht Oxidschicht Metallleitbahn Feldoxid Kontaktfenster Kontaktfensterimplantation Kontakt Gateoxid Oxidisolation Gate/Metalll n-channel transistor with extremely low leakage current "normal" n-channel transistor / n-channel switching transistor gate n-channel transistor with extremely low leakage current gate "normal" n-channel transistor / n-channel switching transistor base material / p-substrate or p-well in n-substrate LDD area nt-S / D area of "normal" n-channel transistor / n-channel switching transistors Spacer photoresist / first photoresist CVD layer oxide layer metal interconnect field oxide contact window contact window implantation contact Gate oxide oxide insulation gate / metal

Claims

Verfahren zur Herstellung von MOS-TransistorenPatentansprüche Process for the production of MOS transistors
1. Verfahren zur Herstellung von MOS-Transistoren (1) mit extrem geringen Leckströmen an den pn-Übergängen in einem p- Substrat oder einer p-Wanne in n-Substrat, einem mit Spacern (8) seitlich begrenzten Gate (4) von n-1. A method for producing MOS transistors (1) with extremely low leakage currents at the pn junctions in a p-type substrate or a p-type well in n-type substrate, a gate (4) of n laterally delimited with spacers (8) -
Kanal-Schalt-transistoren (2) und über Gatekanten realisierter LDD- Implantation, d a du r c h g e- k e n n z e i c hn e t, dass die Spacer (8) hergestellt und danach durch einen anisotropen Ätzschritt, der eine hohe Selektivität gegenüber den Gate- und Substratmaterialien einschließlich ihrer Abdeckschichten aufweist, selektiv für MOS-Transistoren (1) mit extrem geringen Leckströmen entfernt werden, diese ausschließlich über das LDD- Gebiet angeschlossen sind und keine, vorzugsweise As-, Hochdosisimplantation in ihre S/D- Gebiete erfolgt.Channel switching transistors (2) and LDD implantation implemented over gate edges, since you can see that the spacers (8) are produced and then by an anisotropic etching step, which includes a high selectivity towards the gate and substrate materials of their cover layers, are selectively removed for MOS transistors (1) with extremely low leakage currents, these are connected exclusively via the LDD area and no, preferably As, high-dose implantation takes place in their S / D areas.
2. Verfahren nach Anspruch 1 , d a d u r c h g e - k e n n z e i c h n e t, dass die n-Kanal-Schalt- transistoren (2), z.B. für normale Digitalfunktionen, vor dem anisotropen Spacerätzschritt abgedeckt werden.2. The method of claim 1, d a d u r c h g e - k e n n z e i c h n e t that the n-channel switching transistors (2), e.g. for normal digital functions, are covered before the anisotropic spacer etching step.
3. Verfahren nach Anspruch 2, d a du r c h g ek e nn z e i c h n e t, dass das Abdecken der n- Kanal-Schalttransistoren mit einem Photoresist erfolgt.3. The method according to claim 2, since the covering of the n-channel switching transistors is carried out with a photoresist.
4. Verfahren zur Herstellung von MOS-Transistoren (1) mit extrem geringen Leckströmen an den pn-Übergängen in einem p- Substrat oder einer p-Wanne in n-Substrat, einem mit Spacern (8) seitlich begrenzten Gate ( 4) von n- kanal-Schalttransistoren (2) und über Gatekanten realisierter LDD- Implantation, d a du r c h g e k e n nz e i c h n e t, dass durch Abdeckung der n-Kanal- Transistoren mit extrem niedrigen Leckstrom bei der isotropen Spacerätzung der Spacer (8) nur selektiv für die n-kanal-Schalttransistoren (2) entsteht, die n- Kanal-Transistoren mit extrem niedrigen Leckstrom ausschließlich über das LDD- Gebiet angeschlossen sind und keine, vorzugsweise As-, Hochdosisimplantation in ihre S/D- Gebiete erfolgt.4. Method for producing MOS transistors (1) with extremely low leakage currents at the pn junctions in a p-type substrate or a p-type well in n-type substrate, a gate (4) of n laterally delimited with spacers (8) - channel switching transistors (2) and LDD implantation implemented via gate edges, since you can see that by covering the n-channel transistors with extremely low leakage current in the isotropic spacer etching, the spacers (8) are only selective for the n-channel Switching transistors (2) are formed, the n-channel transistors with extremely low leakage current are connected exclusively via the LDD area and no, preferably As, high-dose implantation into their S / D areas.
5. Verfahren nach einem der Ansprüche 1 bis 4 , d adu r c h g e k e n n z e i c h n e t, dass nach dem Ätzschritt die Oberfläche der gesamten Struktur mit ei- ner Oxidschicht (11) abgedeckt wird.5. The method according to any one of claims 1 to 4, such that after the etching step the surface of the entire structure is covered with an oxide layer (11).
6. Verfahren nach einem der Ansprüche 1 bis 4, d adu r c h g e k e n n z e i c h n e t, dass nach dem Ätzschritt die Oberfläche der gesamten Struktur mit ei- ner CVD-Schicht (10) abgedeckt wird. 6. The method according to any one of claims 1 to 4, such that after the etching step the surface of the entire structure is covered with a CVD layer (10).
EP03720179A 2002-06-28 2003-03-14 Method for the production of mos transistors Withdrawn EP1522101A1 (en)

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US7807555B2 (en) * 2007-07-31 2010-10-05 Intersil Americas, Inc. Method of forming the NDMOS device body with the reduced number of masks
US9269709B2 (en) 2013-02-25 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. MOS transistor structure and method
US9472651B2 (en) 2013-09-04 2016-10-18 Globalfoundries Inc. Spacerless fin device with reduced parasitic resistance and capacitance and method to fabricate same

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US5416036A (en) * 1993-10-04 1995-05-16 United Microelectronics Corporation Method of improvement ESD for LDD process
US5654213A (en) * 1995-10-03 1997-08-05 Integrated Device Technology, Inc. Method for fabricating a CMOS device
US5869866A (en) * 1996-12-06 1999-02-09 Advanced Micro Devices, Inc. Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions
US6274887B1 (en) * 1998-11-02 2001-08-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method therefor
US6238967B1 (en) * 1999-04-12 2001-05-29 Motorola, Inc. Method of forming embedded DRAM structure
US6579751B2 (en) * 1999-09-01 2003-06-17 Micron Technology, Inc. Semiconductor processing methods of forming integrated circuitry

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Title
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