EP1504342A2 - Method and arrangement for power efficient control of processors - Google Patents

Method and arrangement for power efficient control of processors

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Publication number
EP1504342A2
EP1504342A2 EP03729889A EP03729889A EP1504342A2 EP 1504342 A2 EP1504342 A2 EP 1504342A2 EP 03729889 A EP03729889 A EP 03729889A EP 03729889 A EP03729889 A EP 03729889A EP 1504342 A2 EP1504342 A2 EP 1504342A2
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EP
European Patent Office
Prior art keywords
slice
processors
vliw
register
pcu
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EP03729889A
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German (de)
French (fr)
Inventor
Wolfram Drescher
Uwe Porst
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NXP BV
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Philips Semiconductors Dresden AG
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Publication of EP1504342A2 publication Critical patent/EP1504342A2/en
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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Definitions

  • the invention relates to a method for the functional control of the program and / or data flow in digital signal processors and processors, each with separate and separate modules for program and data flow control, which operate in parallel arithmetic units.
  • DSP digital signal processors
  • the results obtained can usually only be provided at different times or after a different number of processor cycles in the respective slice.
  • the regime of command processing compliant with the other SIMD slices can either not be implemented at all or only with great effort.
  • this high expenditure in hardware occurs as a strong processor and memory utilization, which reduces the processor performance.
  • This reduction can e.g. be averted by a memory expansion, which means an increase in hardware expenditure.
  • the task according to the invention thus consists in realizing a power-efficient individual adaptation of the signal processing for the SIMD instruction type used in the individual data paths and in particular in minimizing the occurrence of NOP instructions with which the VLIW architecture of the processor are supplied.
  • the task according to the invention is achieved in that the SIMD implemented by the PCU Commands parallel signal processing of the processor in a respective data path (DP) of a first and second slice is individually controlled by a "single-slice half" state output by an SSM register bank for each slice.
  • DP data path
  • the controlling effect of the output "single slice half" state is achieved in that the bits of the SSM register bank assigned for the first and second slice switch the register clock supply via the respectively associated first and second gated clock cell ,
  • the register file unit (RFU) and the memory access register of the processor remain functional.
  • the SSM register bank of the PCU can be written to by the PCU at any time.
  • the aim of this solution is to start the calculations in parallel in the slices of the data paths of the processor in accordance with the SIMD command type.
  • the intermediate and / or final results are provided in the slices at different times in the pipeline control registers, accumulators or result registers of the associated data paths.
  • a supplementary embodiment of the solution of the task according to the invention is that the clock supply for the VLIW unit is controlled by a software-related status output from the program flow of the processor in such a way that partial instruction words that are currently available in the VLIW unit are subsequently used in the latter Multiple use can be provided on the functional units.
  • This solution according to the invention is advantageously effective if a necessary adaptation of the algorithm to the SIMD command type during signal processing requires that the data paths or the associated VLIW architecture of the processor with no-operation commands (NOP) or the like Instructions with a high repetition rate must be supplied.
  • NOP no-operation commands
  • the avoided generation of the same VLIW reduces the storage space consumption and keeps the processor's computing load low, so that the computing power is efficiently available for the important calculations.
  • An advantageous variant of the additional embodiment of the solution according to the invention is that the generation of further VILWs in the VLIW unit is interrupted by the PCU being announced a VLIW-WAIT command via a distant signal line and this command to the PCU in the next cycle is applied, the PCU subsequently switching the clock supply for the VLIW unit by means of a “VLIW-WAIT” signal line and a third gated clock cell.
  • debug routines can be implemented in software tests by setting and starting software break points in the program code.
  • results are provided in the associated accumulator 8 at different times. In this case, one for the first and second slice 18; 19 assigned bit of the SSM register bank 13 set.
  • the signal assignment of this bit is at the first and second slice 18; 19 respectively associated data path 14 via the first and / or second gated clock cell 3; 4 fed and controls the signal processing in the first and second slice 18; 19 individually, in that if there is a result in this slice, the clock supply at the associated input register and thus also the signal processing is prevented.
  • the signal processing in the individual slices of the data paths 14 is thus advantageously adapted to the requirements of parallel processing of the SIMD commands.
  • VLIW unit very long instruction word
  • first gated clock cell second gated clock cell AGU address generating unit
  • PCU processing controlling unit
  • clock supply line accumulator further processing unit (with gated Clock cell)
  • Register of the further processing unit RFU (register file unit)
  • SIMD control bus SSM register bank (single slice mode)
  • Data path SIMD data path control line Distortion signal line VLIW-WAIT signal line first slice second slice third gated Clock-cell

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Power Sources (AREA)

Abstract

The invention relates to a method for the functional control of program and/or data flows in digital signal processors and processors which have respective closed and separated modules for program and data flow control, working in parallel with computers. The aim of the invention is to carry out a power-efficient adaptation of the signal process with the applied SIMD command-type in the individual paths and minimize the emergence of the appearance of NOP-commands with which the VLIW-architecture of the processor must be supplied. This is achieved by individually controlling the parallel signal processing of the processor in the data paths (DP) which respectively belong to the first and second slice. This is carried out by causing a single slice halt outputted from an SSM register bank to switch the register clockline according to state-dependent signal processing.

Description

Verfahren und Anordnung zur leistungseffizienten Steuerung von Prozessoren Method and arrangement for the efficient control of processors
Die Erfindung betrifft ein Verfahren zur funktionalen Steuerung des Programm- und/oder Datenflusses in digitalen Signalprozessoren und Prozessoren mit jeweils abgeschlossenen und voneinander getrennten Modulen zur Programm- und zur Datenfluss- kontrolle, die in parallelen Rechenwerken arbeiten.The invention relates to a method for the functional control of the program and / or data flow in digital signal processors and processors, each with separate and separate modules for program and data flow control, which operate in parallel arithmetic units.
Bei den digitalen Signal-Prozessoren (DSP) bekommen zunehmend Prozessoren Bedeutung, bei denen ihre Architektur eine Slice- Struktur aufweist. Hierbei werden Datenpfade zu Slices zusam- mengefasst, wobei in einem ersten Slice eine Signalverarbeitung unabhängig von der in einem zweiten Slice parallel ablaufenden Signalverarbeitung abgearbeitet wird.With digital signal processors (DSP), processors are becoming increasingly important in which their architecture has a slice structure. In this case, data paths are combined into slices, signal processing being processed in a first slice independently of the signal processing running in parallel in a second slice.
Wird in den parallelen Rechenwerken dieser digitalen Signalprozessoren in der Befehlsart SIMD gearbeitet, ergibt sich beim Stand der Technik das Problem, dass oftmals die dabei angewendeten Algorithmen nicht zur parallelen Signal erarbeitung in allen Slices geeignet sind.If the SIMD instruction type is used in the parallel arithmetic units of these digital signal processors, the problem with the prior art arises that the algorithms used are often not suitable for parallel signal processing in all slices.
So lassen sich beispielsweise bei der Signalverarbeitung in den einzelnen Slices, bedingt durch die jeweils dort angewendeten unterschiedlichen Algorithmen, die anfallenden Ergebnisse meist nur zu unterschiedlichen Zeitpunkten bzw. nach einer unterschiedlichen Anzahl von Prozessortakten im jeweiligen Slice bereitstellen. Das Regime der mit den anderen SIMD Slices konformen Befehlsab- ärbeitung kann entweder gar nicht oder nur mit hohem Aufwand durchgesetzt werden.For example, in signal processing in the individual slices, due to the different algorithms used in each case, the results obtained can usually only be provided at different times or after a different number of processor cycles in the respective slice. The regime of command processing compliant with the other SIMD slices can either not be implemented at all or only with great effort.
Dieser erforderlich hohe Aufwand fällt einerseits softwaremäßig als zusätzliche abzuarbeitende Programme, die die unterschiedlichen Wartezeiten für die Slices organisieren an, um die parallele Bereitstellung der Ergebnisse zu realisieren.On the one hand, this high effort is required in software as additional programs to be processed, which organize the different waiting times for the slices in order to realize the parallel provision of the results.
Anderseits tritt dieser hohe Aufwand in der Hardware als starke Prozessor- und Speicherauslastung auf, die die Prozessorleistungsfähigkeit vermindert. Diese Verminderung kann z.B. durch eine Speichererweiterung abgewendet werden, was jedoch eine Vergrößerung des Hardwareaufwandes bedeutet .On the other hand, this high expenditure in hardware occurs as a strong processor and memory utilization, which reduces the processor performance. This reduction can e.g. be averted by a memory expansion, which means an increase in hardware expenditure.
Beim Stand der Technik erweist es sich als Nachteil, dass zur notwendigen Anpassung der Algorithmen an die Befehlsart SIMD bei der SignalVerarbeitung, vornehmlich in den Slices mit ihren zugehörigen Datenpfaden, diese Slices und weitere zugehörige VLIW-Architektur des Prozessors in erheblichem Umfang mit No- Operation-Befehlen (NOP) versorgt werden müssen.In the prior art, it proves to be a disadvantage that, in order to adapt the algorithms to the SIMD instruction type during signal processing, primarily in the slices with their associated data paths, these slices and other associated VLIW architecture of the processor to a considerable extent with no operation Commands (NOP) must be supplied.
Auf diese Weise wird die leistungssteigernde Effekte der Anwendung der SIMD-Befehlsart nicht nur unwirksam gemacht, sondern es ist darüber hinaus zur Algorithmen-Anpassung zusätzlicher hardware- und softwaremäßiger Aufwand notwendig.In this way, the performance-increasing effects of using the SIMD instruction type are not only rendered ineffective, but additional hardware and software expenditure is also required for adapting the algorithms.
Somit besteht die erfindungsgemäße Aufgabenstellung darin, eine leistungseffiziente individuelle Anpassung der Signalverarbei- tung bei der angewandten Befehlsart SIMD in den einzelnen Datenpfaden zu realisieren und insbesondere das Aufkommen an NOP- Befehlen, mit denen die VLIW-Architektur des Prozessors versorgt werden uss, zu minimieren.The task according to the invention thus consists in realizing a power-efficient individual adaptation of the signal processing for the SIMD instruction type used in the individual data paths and in particular in minimizing the occurrence of NOP instructions with which the VLIW architecture of the processor are supplied.
Die erfindungsgemäße Lösung der Aufgabenstellung wird dadurch erreicht, dass die infolge der von der PCU umgesetzten SIMD- Befehle parallele Signalverarbeitung des Prozessors in einem jeweiligen Datenpfad (DP) eines ersten und zweiten Slice durch ein von einer SSM-Registerbank je Slice ausgegebenen "Single- Slice-Half'-Zustandes individuell gesteuert wird.The task according to the invention is achieved in that the SIMD implemented by the PCU Commands parallel signal processing of the processor in a respective data path (DP) of a first and second slice is individually controlled by a "single-slice half" state output by an SSM register bank for each slice.
Hierbei wird die steuernde Wirkung des ausgegebenen "Single- Slice-Half'-Zustandes dadurch erreicht, dass die für den ersten und zweiten Slice zugeordneten Bits der SSM-Registerbank über die jeweilig zugehörige erste und zweite Gated-Clock-Zelle die Register-Taktversorgung schalten.The controlling effect of the output "single slice half" state is achieved in that the bits of the SSM register bank assigned for the first and second slice switch the register clock supply via the respectively associated first and second gated clock cell ,
Dadurch wird das zugehörige Eingangsregister und/oder Akkumulator und/oder Pipeline-Steuerregister je nach dem Stand der in dem Slice des Datenpfades anfallenden Signalverarbeitung zwi- schenzeitlich gestoppt.As a result, the associated input register and / or accumulator and / or pipeline control register is temporarily stopped, depending on the state of the signal processing occurring in the slice of the data path.
Erst durch den Wegfall des ausgegebenen "Single-Slice-Halt"- Zustandes wird diese Funktion bei einer Umsetzung eines weiteren SIMD Befehles freigegeben.This function is only released when another SIMD command is implemented when the "single slice stop" status is no longer output.
Unabhängig vom ausgegebenen "Single-Slice-Half'-Zustand bleiben die Register-File-Einheit (RFU) und das Speicherzugriffsregister des Prozessors in Funktion. Die SSM-Registerbank der PCU ist dabei jederzeit durch die PCU beschreibbar.Regardless of the "single slice half" state, the register file unit (RFU) and the memory access register of the processor remain functional. The SSM register bank of the PCU can be written to by the PCU at any time.
Diese Lösung zielt darauf ab, dass in den Slices der Datenpfade des Prozessors entsprechend der Befehlsart SIMD parallel mit den einzelnen Berechnungen begonnen wird.The aim of this solution is to start the calculations in parallel in the slices of the data paths of the processor in accordance with the SIMD command type.
Aber durch die unterschiedlichen Berechnungsabläufe erfolgt die Bereitstellung der Zwischen- und/oder Endergebnisse in den Slices zu unterschiedlichen Zeitpunkten in den Pipeline- Steuerregistern, Akkumulatoren bzw. Ergebnisregistern der zugehörigen Datenpfade.However, due to the different calculation processes, the intermediate and / or final results are provided in the slices at different times in the pipeline control registers, accumulators or result registers of the associated data paths.
Somit wird nach der Bereitstellung der Zwischen- und/oder End- ergebniswerte eine weitere Signalverarbeitung in den zu den einzelnen Slices zugehörigen Datenpfaden, die nicht mehr ergebnisträchtig ist, unterbunden.Thus, after the provision of the intermediate and / or final further signal processing in the data paths associated with the individual slices, which is no longer relevant, is prevented.
Die SignalVerarbeitung wird parallel in allen Datenpfaden der Slices fortgesetzt, wenn begonnen wird, einen weiteren SIMD- Befehl abzuarbeiten.Signal processing is continued in parallel in all data paths of the slices when another SIMD command is started to be processed.
Eine ergänzende Ausführung der erfindungsgemäßen Lösung der Aufgabenstellung besteht darin, dass die Taktversorgung für die VLIW-Einheit durch eine softwarebedingte Zustandsausgäbe aus dem Programmfluss des Prozessors so gesteuert wird, dass dadurch Teilinstruktionsworte, die in der VLIW-Einheit aktuell vorliegen, in dieser anschließend für eine Mehrfachverwendung an den Funktionseinheiten bereitgestellt werden.A supplementary embodiment of the solution of the task according to the invention is that the clock supply for the VLIW unit is controlled by a software-related status output from the program flow of the processor in such a way that partial instruction words that are currently available in the VLIW unit are subsequently used in the latter Multiple use can be provided on the functional units.
Diese erfindungsgemäße Lösung wird vorteilhaft wirksam, falls es eine notwendige Algorithmen-Anpassung an die SIMD-Befehlsart bei der Signalverarbeitung erforderlich macht, dass die Daten- pfade bzw. die zugehörige VLIW-Architektur des Prozessors mit No-Operation-Befehlen (NOP) oder ähnlichen Befehlen mit hoher Wiederholrate versorgt werden müssen. Dabei werden durch die vermiedene Generierung von gleichen VLIW der Speicherplatzverbrauch reduziert und die Rechenbelastung des Prozessors ge- ring gehalten, so dass die Rechenleistung effizient für die wichtigen Berechnungen zur Verfügung steht.This solution according to the invention is advantageously effective if a necessary adaptation of the algorithm to the SIMD command type during signal processing requires that the data paths or the associated VLIW architecture of the processor with no-operation commands (NOP) or the like Instructions with a high repetition rate must be supplied. The avoided generation of the same VLIW reduces the storage space consumption and keeps the processor's computing load low, so that the computing power is efficiently available for the important calculations.
Eine vorteilhafte Variante der ergänzenden Ausführung der erfindungsgemäßen Lösung besteht darin, dass das Generieren von weiteren VILW in der VLIW-Einheit dadurch unterbrochen wird, indem der PCU ein VLIW-WAIT-Kommando über eine Vorsignalleitung angekündigt wird und im nächsten Takt dieses Kommando an die PCU angelegt wird, wobei nachfolgend die PCU mittels einer "VLIW-WAIT"-Signalleitung und einer dritten Gated Clock-Zelle die Taktversorgung für die VLIW-Einheit schaltet. bAn advantageous variant of the additional embodiment of the solution according to the invention is that the generation of further VILWs in the VLIW unit is interrupted by the PCU being announced a VLIW-WAIT command via a distant signal line and this command to the PCU in the next cycle is applied, the PCU subsequently switching the clock supply for the VLIW unit by means of a “VLIW-WAIT” signal line and a third gated clock cell. b
Diese Lösung zielt darauf ab, dass Debug-Routinen bei Softwareprüfungen realisiert werden können, indem Software-Break-Points im Programmcode gesetzt und angefahren werden können.The aim of this solution is that debug routines can be implemented in software tests by setting and starting software break points in the program code.
Die Erfindung soll nachfolgend anhand eines Ausführungsbei- spieles für die Ausgabe eines Single-Slice-Halt-Zustandes näher erläutert werden. In der Zeichnungsfigur liegt ein Blockschaltbild des Prozessors vor, in dem die Teile mit den zugehörigen Funktionseinheiten aufgeführt werden, welche die erfindungsge- mäße Lösung betreffen.The invention will be explained in more detail below on the basis of an exemplary embodiment for the output of a single slice stop state. In the drawing figure there is a block diagram of the processor in which the parts with the associated functional units are listed which relate to the solution according to the invention.
Für den Fall, dass die Ausgabe des "Single-Slice-Halt"- Zustandes wirkt, ist es Voraussetzung, dass ein SIMD-Befehl ü- ber den SIMD-Steuer-Bus 12 von der VLIW-Einheit 2 ausgegeben wird. Dieser einzelne SIMD-Befehl löst eine mehrfache Datenverarbeitung in dem jeweiligen Datenpfad 14 des ersten und zweiten Slice 18; 19 aus.In the event that the output of the "single slice stop" state is effective, it is a prerequisite that a SIMD command is output by the VLIW unit 2 via the SIMD control bus 12. This single SIMD instruction triggers multiple data processing in the respective data path 14 of the first and second slice 18; 19 out.
Die Ergebnisse werden in dem zugehörigen Akkumulator 8 zu un- terschiedlichen Zeitpunkten bereitgestellt. Hierbei wird ein jeweils zum ersten und zweiten Slice 18; 19 zugeordnetes Bit der SSM-Registerbank 13 gesetzt.The results are provided in the associated accumulator 8 at different times. In this case, one for the first and second slice 18; 19 assigned bit of the SSM register bank 13 set.
Die Signalbelegung dieses Bits wird an den zum ersten und zwei- ten Slice 18; 19 jeweilig zugehörigen Datenpfad 14 über die erste und/oder zweite Gated-Clock-Zelle 3; 4 zugeführt und steuert die Signalverarbeitung im ersten und zweiten Slice 18; 19 individuell, indem bei einem vorliegendem Ergebnis in diesem Slice die Taktversorgung am zugehörigen Eingangsregister und damit auch die Signalverarbeitung unterbunden wird.The signal assignment of this bit is at the first and second slice 18; 19 respectively associated data path 14 via the first and / or second gated clock cell 3; 4 fed and controls the signal processing in the first and second slice 18; 19 individually, in that if there is a result in this slice, the clock supply at the associated input register and thus also the signal processing is prevented.
Bei der Ausgabe eines weiteren SIMD-Befehl auf dem SIMD-Steuer- Bus 12, z.B. nach Bereitstellung des letzten in einem der Slices erarbeiteten Ergebnisses, wird das jeweilige Bit der SSM- Registerbank 13 zurückgesetzt und alle Datenpfade beginnen die nächste Signalverarbeitung indem sie an ihren Eingangsregistern die von der RFU 11 bereitgestellten Daten einlesen.When another SIMD command is issued on the SIMD control bus 12, for example after the last result generated in one of the slices has been provided, the respective bit of the SSM register bank 13 is reset and all data paths begin Next signal processing by reading the data provided by the RFU 11 at their input registers.
Damit wird die Signalverarbeitung in den einzelnen Slices der Datenpfade 14 vorteilhaft an die Erfordernisse paralleler Abarbeitung der SIMD-Befehle angepasst. The signal processing in the individual slices of the data paths 14 is thus advantageously adapted to the requirements of parallel processing of the SIMD commands.
Verfahren und Anordnung zur leistungseffizienten Steuerung von ProzessorenMethod and arrangement for the efficient control of processors
Bezugszeichenliste Prozessor VLIW-Einheit (Very-Long-Instruction-Word) erste Gated-Clock-Zelle zweite Gated-Clock-Zelle AGU (Address-Generating-Unit) PCU (Process-Controlling-Unit) Taktversorgungsleitung Akkumulator weitere Verarbeitungseinheit (mit Gated-Clock-Zelle) Register der weiteren Verarbeitungseinheit RFU (Register-File-Einheit) SIMD-Steuer-Bus SSM-Registerbank (Single-Slice-Mode) Datenpfad SIMD-Datenpfad-Steuerleitung Vorsignalleitung VLIW-WAIT-Signallleitung erster Slice zweiter Slice dritte Gated-Clock-Zelle Processor VLIW unit (very long instruction word) first gated clock cell second gated clock cell AGU (address generating unit) PCU (process controlling unit) clock supply line accumulator further processing unit (with gated Clock cell) Register of the further processing unit RFU (register file unit) SIMD control bus SSM register bank (single slice mode) Data path SIMD data path control line Distortion signal line VLIW-WAIT signal line first slice second slice third gated Clock-cell

Claims

Verfahren und Anordnung zur leistungseffizienten Steuerung von ProzessorenPatentansprüche Method and arrangement for the efficient control of processors
1. Verfahren zur funktionalen Steuerung des Programmund/oder Datenflusses in digitalen Signalprozessoren und Prozessoren mit jeweils abgeschlossenen und voneinander getrennten Modulen zur Programm- und zur Datenflusskon- trolle, die in parallelen Rechenwerken arbeiten, dadurch gekennzeichnet, dass infolge der von der PCU (6) umgesetzten SIMD Befehle die parallele SignalVerarbeitung des Prozessors (1) in einem zum ersten und zweiten Slice (18) ; (19) jeweils zugehörigen Datenpfad DP (14) durch ein von einer SSM-Registerbank (13) ausgegebenen "Single- Slice-Halt"-Zustandes individuell gesteuert wird, wobei die steuernde Wirkung des ausgegebenen "Single-Slice- Halt"-Zustandes dadurch erreicht wird, indem die für jeden Slice zugeordneten Bits der SSM-Registerbank (13) über die jeweilige erste und zweite Gated-Clock-Zelle (3); (4) die Register-Taktversorgung schalten und dadurch je nach dem Stand der anfallenden Signalverarbeitung in dem zum jeweiligen Slice zugehörigen DP (14) das zugeordnete Eingangs- register und/oder Akkumulator und/oder Pipeline-1. Method for the functional control of the program and / or data flow in digital signal processors and processors, each with separate and separate modules for program and data flow control, which work in parallel arithmetic units, characterized in that as a result of the PCU (6) implemented SIMD commands the parallel signal processing of the processor (1) in a to the first and second slice (18); (19) each associated data path DP (14) is controlled individually by a "single-slice-stop" state output by an SSM register bank (13), the controlling effect of the output "single-slice-stop" state thereby is achieved by the bits of the SSM register bank (13) assigned for each slice via the respective first and second gated clock cells (3); (4) switch the register clock supply and, depending on the state of the signal processing involved, in the DP (14) belonging to the respective slice the assigned input register and / or accumulator and / or pipeline
Steuerregister in seiner Funktion zwischenzeitlich gestoppt wird und diese Funktion erst durch den Wegfall des ausgegebenen "Single-Slice-Halt"-Zustandes infolge einer Umsetzung eines weiteren SIMD Befehls wieder freigegeben wird, dass unabhängig vom ausgegebenen "Single-Slice-Half'- Zustand die Register-File-Einheit (RFU) (11) und das Speicherzugriffsregister des Prozessors (1) in Funktion bleiben, und die SSM-Registerbank (13) der PCU (6) ist dabei jederzeit durch die PCU beschreibbar.Control register in its function is stopped in the meantime and this function is only released again after the output of the "single slice stop" state as a result of the implementation of a further SIMD command, that the register file unit (RFU) (11) and the memory access register of the processor (1) remain functional, and the SSM register bank (13) of the PCU (6), regardless of the output "single slice half" state can be written to at any time by the PCU.
2. Verfahren zur funktionalen Steuerung des Programmund/oder Datenflusses in digitalen Signalprozessoren und Prozessoren mit jeweils abgeschlossenen und voneinander getrennten Modulen zur Programm- und zur Datenflusskon- trolle, die in parallelen Rechenwerken arbeiten, dadurch gekennzeichnet, dass die Taktversorgung für die VLIW- Einheit (2) durch eine softwarebedingte Zustandsausgäbe aus dem Programmfluss des Prozessors (1) so gesteuert wird, dass dadurch Teilinstruktionsworte die in der VLIW- Einheit (2) aktuell vorliegen, in dieser anschließend für eine Mehrfachverwendung an den Funktionseinheiten bereitgestellt werden.2. Method for the functional control of the program and / or data flow in digital signal processors and processors, each with separate and separate modules for program and data flow control, which work in parallel arithmetic units, characterized in that the clock supply for the VLIW unit ( 2) is controlled by a software-related status output from the program flow of the processor (1) in such a way that partial instruction words that are currently available in the VLIW unit (2) are then made available in this for multiple use on the functional units.
3. Verfahren nach Anspruch 2, dadurch gekennzeichnet, dass das Generieren von weiteren VILW in der VLIW-Einheit (2) dadurch unterbrochen wird, in dem der PCU (6) ein VLIW- WAIT-Kommando über eine Vorsignalleitung (16) angekündigt wird und im nächsten Takt dieses Kommando an die PCU (6) angelegt wird, wobei nachfolgend die PCU (6) mittels einer "VLIW-WAIT"-Signalleitung (17) und einer dritten Gated Clock-Zelle (20) die Taktversorgung für die VLIW-Einheit (2) schaltet. 3. The method according to claim 2, characterized in that the generation of further VILW in the VLIW unit (2) is interrupted by the PCU (6) announcing a VLIW-WAIT command via a distant signal line (16) and in the next cycle this command is applied to the PCU (6), the PCU (6) subsequently using a "VLIW-WAIT" signal line (17) and a third gated clock cell (20) to supply the clock for the VLIW unit (2) switches.
EP03729889A 2002-05-14 2003-05-13 Method and arrangement for power efficient control of processors Withdrawn EP1504342A2 (en)

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