EP1469367A2 - Voltage regulator circuit with oscillation suppression - Google Patents

Voltage regulator circuit with oscillation suppression Download PDF

Info

Publication number
EP1469367A2
EP1469367A2 EP04251107A EP04251107A EP1469367A2 EP 1469367 A2 EP1469367 A2 EP 1469367A2 EP 04251107 A EP04251107 A EP 04251107A EP 04251107 A EP04251107 A EP 04251107A EP 1469367 A2 EP1469367 A2 EP 1469367A2
Authority
EP
European Patent Office
Prior art keywords
transistor
output
voltage
regulator circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04251107A
Other languages
German (de)
French (fr)
Other versions
EP1469367A3 (en
Inventor
Youichi c/o Mitsumi Electric Co. Ltd. Takano
Mitsufusa c/o Mitsumi Electric Co. Ltd. Narita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsumi Electric Co Ltd
Original Assignee
Mitsumi Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsumi Electric Co Ltd filed Critical Mitsumi Electric Co Ltd
Publication of EP1469367A2 publication Critical patent/EP1469367A2/en
Publication of EP1469367A3 publication Critical patent/EP1469367A3/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • This invention relates to a regulator circuit, in particular, to a series regulator integrated circuit which can prevent oscillation thereof regardless of an output capacitor connected thereto.
  • a regulator circuit regulates an input voltage supplied to a power supply terminal thereof from the outside and supplies a regulated voltage as an output voltage to an output terminal thereof. While the output terminal is connected to a load, an output capacitor is also connected to the output terminal. The output capacitor smoothes the output voltage supplied to the output terminal prior to supplying the output voltage to the load. Thus, the load receives the smoothed regulated voltage from a combination of the regulator circuit and the output capacitor.
  • the various capacitors have different values of equivalent series resistance (ESR).
  • ESR equivalent series resistance
  • the electrolytic capacitor, the tantalum capacitor and the ceramic capacitor have the ESR between 0.1 and 100 [ ⁇ ], 0.01 to 1 [ ⁇ ] and 0.001 to 0.1 [ ⁇ ], respectively, though the ESR varies according to a frequency of an input signal supplied to each capacitor and/or an ambient temperature thereof.
  • the output capacitor When the output capacitor has the ESR inappropriate for a phase secure range of the regulator circuit connected thereto, it causes the regulator circuit oscillation. Concretely, the regulator circuit oscillates when the output capacitor has too low ESR for the regulator circuit. Accordingly, some preventive measures are necessary for preventing oscillation of the regulator circuit when an output capacitor with a smaller capacitance is used.
  • a related regulator circuit is manufactured by advanced micro processing to adapt to reduction of the capacitance and the ESR of the output capacitor. That is, the related regulator circuit secures a necessary oscillation margin by means of miniaturizing devices included therein to improve frequency characteristic thereof.
  • Each transistor included in the related regulator circuit for example, has a channel length of 0.6 [ ⁇ m].
  • the related regulator is expensive because it is manufactured by the advanced micro processing as mentioned above.
  • a regulator circuit is used with an output capacitor connected to an output terminal thereof.
  • the regulator circuit comprises a phase correcting capacitor for preventing oscillation thereof.
  • the regulator circuit is characterized in that the phase correcting capacitor is provided to be independent of the output capacitor connected to the output terminal.
  • the regulator circuit further comprises a power supply terminal and an output transistor connected between the power supply terminal and the output terminal.
  • the phase correcting capacitor is included in a phase correcting circuit portion provided at a side of the power supply terminal in relation to the output transistor in the regulator circuit.
  • a regulator circuit comprises an error amplifier for producing an error signal according to a difference between a reference voltage and a divided voltage derived from an output voltage supplied to an output terminal.
  • An output circuit is for producing the output voltage according to the error signal.
  • a feedback voltage producing portion is for producing a feedback voltage equivalent to the output voltage from the input voltage.
  • a phase correcting portion is connected to both of the feedback voltage producing portion and the error amplifier and has a phase correcting capacitor to correct phase of the error signal according to the feedback output voltage.
  • a regulator circuit regulates an input voltage to produce an output voltage according to an error signal based on difference between a reference voltage and a divided voltage derived from the output signal.
  • a method for preventing the regulator circuit from oscillating is characterized by the steps of producing a feedback voltage equivalent to the output voltage, and correcting a phase of the error signal according to the feedback voltage.
  • Fig. 1 is a circuit diagram of a related regulator circuit.
  • the regulator circuit comprises a power supply terminal V DD for being connected to a power supply P W , a grounding terminal GND for being grounded, and an output terminal V OUT for being connected to an load RL together with an output capacitor C1.
  • the regulator circuit is called a three terminal regulator circuit or a series regulator integrated circuit (IC).
  • the regulator circuit further comprises a constant current source 11, first to tenth transistors M1-M10, first to third resistors R1-R3 and a phase correcting capacitor C1.
  • the constant current source 11 and the first to the eighth transistors M1-M8 form an error amplifier connected between the power supply terminal V DD and the grounding terminal GND.
  • the error amplifier is connected to a connection point between the first and the second resistors R1 and R2 to receive a divided voltage produced by a combination of the first and the second resistors R1 and R2.
  • the error amplifier is further connected to a reference voltage producing circuit (not shown) to receive a reference voltage supplied from the reference voltage producing circuit.
  • the error amplifier produces an error signal according to a difference between the divided voltage and the reference voltage.
  • the ninth transistor M9 has a gate, a drain and a source which are connected to the error amplifier, a gate of the tenth transistor M10 and the grounding terminal GND respectively.
  • the ninth transistor M9 receives the error signal from the error amplifier to vary a gate voltage of the tenth transistor M10 according to the error signal.
  • the tenth transistor M10 has a source and a drain which are connected to the power supply terminal V DD and the output terminal V OUT respectively.
  • the tenth transistor M10 serves as an output transistor (or a power transistor). That is, the tenth transistor M10 regulates an input voltage supplied to the power supply terminal V DD to supply a regulated voltage as an output voltage to the output terminal V OUT .
  • the first and the second resistor R1 and R2 are connected to each other between the output terminal V OUT and the grounding terminal GND.
  • the first and the second resistor R1 and R2 divide the output voltage to produce the divided voltage at the connection point between them.
  • the third resistor R3 is connected between the gate and the source of the tenth transistor M10 to produce a control voltage (i.e. the gate voltage) at the gate of tenth transistor M10 according to an operation of the ninth transistor M9.
  • the phase correcting capacitor C1 is connected between the output terminal V OUT and a gate of the first transistor M1 (or the connection point between the first and the second resistors R1 and R2). Alternatively, as shown by broken lines in Fig. 1, the phase correcting capacitor C1 is connected between the output terminal V OUT and a gate of the eighth transistor M8.
  • Supplying the power supply voltage (e.g. 3-7 [V]) to the power supply terminal V DD causes currents flowing through the first and the second transistors M1 and M2. Values of the currents flowing through the first and the second transistors M1 and M2 depend on the difference between the divided voltage and the reference voltage.
  • the reference voltage for example, is equal to 1.2 [V].
  • the third and the fourth transistors M3 and M4 form a first current mirror circuit while the fifth and the sixes transistors M5 and M6 form a second current mirror circuit.
  • the first and the second current mirror circuits supply currents equivalent to the currents flowing through the first and the second transistors M1 and M2 to the seventh and the eighth transistors M7 and M8 respectively.
  • a difference between the currents supplied to the seventh and the eighth transistors M7 and M8 generates a voltage (i.e. the error signal) at the gate of the ninth transistor M9.
  • the ninth transistor M9 varies a current flowing therein according to the error signal. Consequently, the gate voltage of the tenth transistor M10 is varied according to the error signal.
  • the tenth transistor M10 regulates the input voltage and supplies the output voltage to the output terminal V OUT .
  • the output voltage for example, is equal to 2-5 [V].
  • the output voltage is smoothed by the output capacitor Co prior to supplying it to the load RL.
  • the phase correcting capacitor C1 enlarges a phase secure range of the regulator circuit to prevent the regulator circuit from oscillating. In other words, the phase correcting capacitor C1 secures phase advance of the output voltage against the input voltage.
  • the phase correcting capacitor C1 for example, has a capacitance of 30 [pF].
  • the regulator circuit having the phase correcting capacitor C1 does not oscillate, even if it is connected to the output capacitor Co with relative high ESR (e.g. 100 [ ⁇ ]).
  • Fig. 2 shows open loop characteristics of the regulator circuit of Fig. 1 in a case where the output capacitor Co having the ESR of 100 [ ⁇ ] is connected to the regulator circuit.
  • phase difference between input and output signals is larger than a necessary phase margin (e.g. 45°) in a frequency range from 0.01 to 10000 [kHz]. Accordingly, the regulator circuit does not oscillate in the case of Fig. 2.
  • a necessary phase margin e.g. 45°
  • phase correcting capacitor C1 is effective in the case where the output capacitor Co has the relative high ESR, it is ineffective in a case where the output capacitor Co has relative low ESR (e.g. equal to or less than 0.1 [ ⁇ ]).
  • Fig. 3 shows open loop characteristics of the regulator circuit of Fig. 1 in a case where the output capacitor Co having the ESR of 0.01 [ ⁇ ] is connected to the regulator circuit.
  • the phase difference between the input and the output signals is lower than the necessary phase margin (45°) in a frequency range over 20 [kHz].
  • the regulator circuit has a positive gain. Therefore, the regulator oscillates in the case of Fig. 3.
  • the open loop characteristics of the regulator circuit can be improved by miniaturizing components (or devices) of the regulator circuit.
  • the necessary oscillation margin can be secured. Accordingly, the regulator circuit having miniaturized components does not oscillate even if the output capacitor connected thereto has the relative low ESR.
  • Fig. 4 is a circuit diagram of the regulator circuit (or a series regulator IC).
  • the regulator circuit is basically similar to the related regulator circuit of Fig. 1 and different in having a phase correcting circuit portion 40 including a phase correcting capacitor C1'.
  • the regulator circuit comprises a constant current source 11, first to tenth transistors M1-M10, first to third resistors R1-R3 and the phase correcting circuit portion 40.
  • the phase correcting circuit portion 40 comprises an eleventh transistor M11, forth and fifth resistors R4 and R5, and the phase correcting capacitor C1'.
  • the forth and the fifth resistors R4 and R5 has resistance of 60 [k ⁇ ] and 100 [k ⁇ ] respectively, while the phase correcting capacitor C1' has capacitance of 5 [pF].
  • the constant current source 11 and the first to the eighth transistors M1-M8 form an error amplifier (as an error amplifying means) to produce an error signal according to two input signals (i.e. a divided voltage and a reference voltage as mentioned below).
  • the first and the second transistors M1 and M2 comprise N channel FETs (e.g. MOS FETs) which are identical to each other.
  • the first and the second transistors M1 and M2 have sources connected to the constant current source 11 in common, and drains connected to those of the third and the fifth transistors M3 and M5.
  • a gate of the first transistor M1 is connected to a connection point between the first and the second resistors R1 and R2.
  • a gate of the second transistor M2 is connected to a reference voltage producing circuit (not shown) to receive the reference voltage produced by the reference voltage producing circuit.
  • the first and the second transistors M1 and M2 divides a constant current produced by the constant current source 11 according to the difference between voltages supplied to the gates of the first and the second transistors M1 and M2.
  • the third and the fourth transistors M3 and M4 comprise P channel FETs (e.g. MOS FETs) which are identical to each other.
  • the third and the fourth transistors M3 and M4 have sources connected to a power supply terminal V DD , and gates connected to a drain of the third transistor M3.
  • the drain of the third transistor M3 is connected to the drain of the first transistor M1.
  • a drain of the fourth transistor M4 is connected to a drain of the seventh transistor M7.
  • the third and the fourth transistors M3 and M4 form a first current mirror circuit to supply a current equivalent to that flowing through the first transistor M1 to the seventh transistor M7.
  • the fifth and the sixth transistors M5 and M6 are similar to the third and the fourth transistor M3 and M4. That is, the fifth and the sixth transistors M5 and M6 comprise P channel FETs (e.g. MOS FETs) which are identical to each other.
  • the fifth and the sixth transistors M5 and M6 have sources connected to a power supply terminal V DD , and gates connected to a drain of the fifth transistor M5.
  • the drain of the fifth transistor M5 is connected to the drain of the first transistor M1.
  • a drain of the sixth transistor M6 is connected to a drain of the eighth transistor M8.
  • the fifth and the sixth transistors M5 and M6 form a second current mirror circuit to supply a current equivalent to that flowing through the second transistor M2 to the eighth transistor M8.
  • the seventh and the eighth transistors M7 and M8 comprise N channel FETs (e.g. MOS FETs) which are identical to each other.
  • the seventh transistor M7 has a source connected to the grounding terminal GND, and a gate connected to both of the drain thereof and one of the terminals of the fifth resistor R5 of the phase correcting circuit portion 40.
  • the eighth transistor M8 has a source connected to the grounding terminal GND, and a gate connected to the other terminal of the fifth resistor R5 of the phase correcting circuit portion 40.
  • the eighth transistor M8 is referred to as an error signal producing transistor.
  • the seventh and the eighth transistors M7 and M8 form a third current mirror circuit to generate a voltage (i.e. the error signal) at the drain of the eighth transistor M8 according to a difference between currents supplied from the fourth and the sixth transistors M4 and M6.
  • the ninth transistor M9 comprises an N channel FET.
  • the ninth transistor M9 has a source connected to the grounding terminal GND, a drain connected to a gate of the tenth transistor M10, and a gate connected to the drain of the eighth transistor M8 (and to the drain of the sixth transistor M6).
  • the ninth transistor M9 cooperates with a third resistor R3 to generate a voltage (i.e. a control voltage) at the gate of the tenth transistor M10 according to a gate voltage (i.e. the error signal supplied from the error amplifier) of the ninth transistor M9.
  • the tenth transistor M10 comprises a P channel FET.
  • the tenth transistor M10 has a source connected to the power supply terminal V DD and to the gate thereof through the third resistor R3.
  • a drain of the tenth transistor M10 connected to the output terminal V OUT .
  • the tenth transistor M10 regulates an input voltage (or a power supply voltage) supplied to the power supply terminal V DD from the power supply P W to produce an output voltage (or a regulated voltage) supplied to the output terminal V OUT .
  • the tenth transistor M10 is referred to as an output transistor.
  • the ninth and the tenth transistors M9 and M10 and the third resistor R3 serve as an output circuit means.
  • the first and the second resistors R1 and R2 are connected to each other between the output terminal V OUT and the grounding terminal GND. As mentioned above, the connection point between the first and the second resistors R1 and R2 is connected to the gate of the first transistor M1. The first and the second resistor R1 and R2 divide the output voltage supplied to the output terminal V OUT to produce the divided voltage supplied to the gate of the first transistor M1.
  • the eleventh transistor M11 comprises a P channel transistor.
  • the eleventh transistor M11 together with the tenth transistor M10, forms a current mirror circuit.
  • the eleventh transistor M11 is referred to as a correcting circuit transistor or a feedback transistor.
  • the eleventh transistor M11 has a source connected to the power supply terminal V DD , a drain connected to the grounding terminal GND through the fourth resistor R4, and a gate connected to the gate of the tenth transistor M10.
  • the fourth resistor R4 is referred to as a current-voltage-converting resistor.
  • the fourth resistor R4 cooperates with the eleventh transistor M11 produces a feedback voltage proportional to (or equivalent to) the output voltage at a connection point between the fourth resistor R4 and the eleventh transistor M11. That is, the fourth resistor R4 and the eleventh transistor M11 serves as a feedback voltage producing means.
  • the feedback voltage is not influenced by an output capacitor Co (especially, its ESR) connected to the output terminal V OUT . This is because the source of the eleventh transistor M11 is not connected to the output terminal V OUT but to the power supplying terminal V DD .
  • the phase correcting capacitor C1' has a pair of terminals, one of which is connected to the connection point between the eleventh transistor M11 and the fourth resistor R4, and the other of which is connected to the gate of the eighth transistor M8. IN other words, the other of the terminals of the phase correcting capacitor is connected to both of the resistor R5 and the eighth transistor M8.
  • the phase correcting capacitor C1' varies the gate voltage of the eighth transistor M8 according to the feedback voltage to correct the error signal output from the error amplifier.
  • the phase correcting capacitor C1' and the resistor R5 serve as a phase correcting means.
  • the regulator circuit of Fig. 4 regulates the input voltage supplied to the power supply terminal V DD to produce the regulated voltage.
  • the regulator circuit supplies the regulated voltage to the output terminal V OUT as the output voltage.
  • the phase correcting circuit 40 is connected between the input terminal V DD and the output transistor M10 as mentioned above. That is, the phase correcting circuit 40 is provided at a power supplying terminal side of the output terminal 10. Accordingly, the phase correcting circuit 40 can execute phase correction without influence of the output capacitor Co (or its ESR) when the regulator circuit regulates the power supply voltage. That is, the phase correcting circuit 40 feeds the feedback voltage proportional to the output voltage to the error amplifier regardless of the output capacitor Co (or the ESR) and corrects the error signal output from the error amplifier to suppress variation of the output voltage.
  • the regulator circuit of this embodiment can execute the phase correction between the input and the output voltages regardless of the ESR of the output capacitor Co. Therefore, the regulator circuit secures the necessary phase margin regardless of a frequency of variation of the power supply voltage. At least, the necessary phase margin is secured for the ESR from 10 [m ⁇ ] to 100 [ ⁇ ].
  • Fig. 5 shows open loop characteristics of the regulator circuit of Fig. 4 in a case where the output capacitor Co having the ESR of 100 [ ⁇ ] is connected to the regulator circuit.
  • the regulator circuit is manufactured by means of normal fine processing while each transistor included in the regulator circuit has a channel length of 1.2 [ ⁇ m].
  • phase difference between input and output signals is larger than the necessary phase margin (e.g. 45°) over a frequency range from 0.01 to 10000 [kHz]. Accordingly, the regulator circuit does not oscillate in the case of Fig. 5.
  • Fig. 6 shows open loop characteristics of the regulator circuit of Fig. 4 in a case where the output capacitor Co has the ESR of 0.01 [ ⁇ ].
  • the necessary phase margin (45°) is secured in a frequency range under 1000 [Hz].
  • the regulator circuit has negative gain in a frequency range over 1000 [Hz]. Accordingly, the regulator circuit does not oscillate over a frequency range from 0.01 to 10000 [kHz].
  • the regulator circuit of this embodiment can be used with the output capacitor having a small capacitance and low ESR, even if it is manufactured by the normal fine processing. Therefore, the regulator circuit is inexpensive.
  • a regulator circuit comprises a phase correcting circuit portion.
  • the phase correcting circuit portion comprises a current correcting transistor M11 combined with an output transistor to form a current mirror circuit.
  • An I-V converting resistor R4 is connected to the current correcting transistor M11 to convert a current flowing through the phase correcting circuit portion into a feedback voltage which is proportional to an output voltage and independent of an output capacitor Co.
  • a phase correcting capacitor C1 and a resistor R5 corrects the error signal according to the feedback voltage.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

A regulator circuit comprises a phase correcting circuit portion (40). The phase correcting circuit portion (40) comprises a current correcting transistor (M11) combined with an output transistor to form a current mirror circuit. An I-V converting resistor (R4) is connected to the current correcting transistor (M11) to convert a current flowing through the phase correcting circuit portion (40) into a feedback voltage which is proportional to an output voltage and independent of an output capacitor (Co). A phase correcting capacitor (C1) and a resistor (R5) correct the error signal according to the feedback voltage.

Description

This application claims priority to prior Japanese application JP 2003-110435, the disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION:
This invention relates to a regulator circuit, in particular, to a series regulator integrated circuit which can prevent oscillation thereof regardless of an output capacitor connected thereto.
A regulator circuit regulates an input voltage supplied to a power supply terminal thereof from the outside and supplies a regulated voltage as an output voltage to an output terminal thereof. While the output terminal is connected to a load, an output capacitor is also connected to the output terminal. The output capacitor smoothes the output voltage supplied to the output terminal prior to supplying the output voltage to the load. Thus, the load receives the smoothed regulated voltage from a combination of the regulator circuit and the output capacitor.
Though an electrolytic capacitor or a tantalum capacitor is generally used as the output capacitor, a ceramic capacitor with smaller capacitance is coming into use to meet a demand for miniaturizing.
Now, it is known that the various capacitors have different values of equivalent series resistance (ESR). For instance, the electrolytic capacitor, the tantalum capacitor and the ceramic capacitor have the ESR between 0.1 and 100 [Ω], 0.01 to 1 [Ω] and 0.001 to 0.1 [Ω], respectively, though the ESR varies according to a frequency of an input signal supplied to each capacitor and/or an ambient temperature thereof.
When the output capacitor has the ESR inappropriate for a phase secure range of the regulator circuit connected thereto, it causes the regulator circuit oscillation. Concretely, the regulator circuit oscillates when the output capacitor has too low ESR for the regulator circuit. Accordingly, some preventive measures are necessary for preventing oscillation of the regulator circuit when an output capacitor with a smaller capacitance is used.
A related regulator circuit is manufactured by advanced micro processing to adapt to reduction of the capacitance and the ESR of the output capacitor. That is, the related regulator circuit secures a necessary oscillation margin by means of miniaturizing devices included therein to improve frequency characteristic thereof. Each transistor included in the related regulator circuit, for example, has a channel length of 0.6 [µm].
The related regulator is expensive because it is manufactured by the advanced micro processing as mentioned above.
SUMMARY OF THE INVENTION:
It is therefore an object of at least the preferred embodiments of this invention to provide a regulator circuit which inexpensively can prevent oscillation thereof regardless of an output capacitor.
Other such objects of this invention will become clear as the description proceeds.
According to an aspect of this invention, a regulator circuit is used with an output capacitor connected to an output terminal thereof. The regulator circuit comprises a phase correcting capacitor for preventing oscillation thereof. The regulator circuit is characterized in that the phase correcting capacitor is provided to be independent of the output capacitor connected to the output terminal.
The regulator circuit further comprises a power supply terminal and an output transistor connected between the power supply terminal and the output terminal. The phase correcting capacitor is included in a phase correcting circuit portion provided at a side of the power supply terminal in relation to the output transistor in the regulator circuit.
According to another aspect of this invention, a regulator circuit comprises an error amplifier for producing an error signal according to a difference between a reference voltage and a divided voltage derived from an output voltage supplied to an output terminal. An output circuit is for producing the output voltage according to the error signal. A feedback voltage producing portion is for producing a feedback voltage equivalent to the output voltage from the input voltage. A phase correcting portion is connected to both of the feedback voltage producing portion and the error amplifier and has a phase correcting capacitor to correct phase of the error signal according to the feedback output voltage.
According to still another aspect of this invention, a regulator circuit regulates an input voltage to produce an output voltage according to an error signal based on difference between a reference voltage and a divided voltage derived from the output signal. A method for preventing the regulator circuit from oscillating is characterized by the steps of producing a feedback voltage equivalent to the output voltage, and correcting a phase of the error signal according to the feedback voltage.
BRIEF DESCRIPTION OF THE DRAWING:
  • Fig. 1 is a circuit diagram of a related regulator circuit;
  • Fig. 2 is a graph showing open loop characteristics of the regulator circuit of Fig. 1 in a case where an output capacitor having ESR of 100 [Ω] is connected to the regulator circuit;
  • Fig. 3 is a graph showing open loop characteristics of the regulator circuit of Fig. 1 in a case where an output capacitor having ESR of 0.01 [Ω] is connected to the regulator circuit;
  • Fig. 4 is a circuit diagram of a regulator circuit according to a preferred embodiment of this invention;
  • Fig. 5 is a graph showing open loop characteristics of the regulator circuit of Fig. 4 in a case where an output capacitor having ESR of 100 [Ω] is connected to the regulator circuit; and
  • Fig. 6 is a graph showing open loop characteristics of the regulator circuit of Fig. 4 in a case where an output capacitor having ESR of 0.01 [Ω] is connected to the regulator circuit.
    • DESCRIPTION OF THE PREFERRED EMBODIMENT:
    Referring to Figs. 1 to 3, description will be at first directed to a related regulator circuit for a better understanding of this invention.
    Fig. 1 is a circuit diagram of a related regulator circuit. The regulator circuit comprises a power supply terminal VDD for being connected to a power supply PW, a grounding terminal GND for being grounded, and an output terminal VOUT for being connected to an load RL together with an output capacitor C1. The regulator circuit is called a three terminal regulator circuit or a series regulator integrated circuit (IC).
    The regulator circuit further comprises a constant current source 11, first to tenth transistors M1-M10, first to third resistors R1-R3 and a phase correcting capacitor C1.
    The constant current source 11 and the first to the eighth transistors M1-M8 form an error amplifier connected between the power supply terminal VDD and the grounding terminal GND. The error amplifier is connected to a connection point between the first and the second resistors R1 and R2 to receive a divided voltage produced by a combination of the first and the second resistors R1 and R2. The error amplifier is further connected to a reference voltage producing circuit (not shown) to receive a reference voltage supplied from the reference voltage producing circuit. The error amplifier produces an error signal according to a difference between the divided voltage and the reference voltage.
    The ninth transistor M9 has a gate, a drain and a source which are connected to the error amplifier, a gate of the tenth transistor M10 and the grounding terminal GND respectively. The ninth transistor M9 receives the error signal from the error amplifier to vary a gate voltage of the tenth transistor M10 according to the error signal.
    The tenth transistor M10 has a source and a drain which are connected to the power supply terminal VDD and the output terminal VOUT respectively. The tenth transistor M10 serves as an output transistor (or a power transistor). That is, the tenth transistor M10 regulates an input voltage supplied to the power supply terminal VDD to supply a regulated voltage as an output voltage to the output terminal VOUT.
    The first and the second resistor R1 and R2 are connected to each other between the output terminal VOUT and the grounding terminal GND. The first and the second resistor R1 and R2 divide the output voltage to produce the divided voltage at the connection point between them.
    The third resistor R3 is connected between the gate and the source of the tenth transistor M10 to produce a control voltage (i.e. the gate voltage) at the gate of tenth transistor M10 according to an operation of the ninth transistor M9.
    The phase correcting capacitor C1 is connected between the output terminal VOUT and a gate of the first transistor M1 (or the connection point between the first and the second resistors R1 and R2). Alternatively, as shown by broken lines in Fig. 1, the phase correcting capacitor C1 is connected between the output terminal VOUT and a gate of the eighth transistor M8.
    Next, an operation of the regulator circuit will be described below.
    Supplying the power supply voltage (e.g. 3-7 [V]) to the power supply terminal VDD causes currents flowing through the first and the second transistors M1 and M2. Values of the currents flowing through the first and the second transistors M1 and M2 depend on the difference between the divided voltage and the reference voltage. The reference voltage, for example, is equal to 1.2 [V].
    The third and the fourth transistors M3 and M4 form a first current mirror circuit while the fifth and the sixes transistors M5 and M6 form a second current mirror circuit. The first and the second current mirror circuits supply currents equivalent to the currents flowing through the first and the second transistors M1 and M2 to the seventh and the eighth transistors M7 and M8 respectively. A difference between the currents supplied to the seventh and the eighth transistors M7 and M8 generates a voltage (i.e. the error signal) at the gate of the ninth transistor M9. The ninth transistor M9 varies a current flowing therein according to the error signal. Consequently, the gate voltage of the tenth transistor M10 is varied according to the error signal. The tenth transistor M10 regulates the input voltage and supplies the output voltage to the output terminal VOUT. The output voltage, for example, is equal to 2-5 [V]. The output voltage is smoothed by the output capacitor Co prior to supplying it to the load RL.
    The phase correcting capacitor C1 enlarges a phase secure range of the regulator circuit to prevent the regulator circuit from oscillating. In other words, the phase correcting capacitor C1 secures phase advance of the output voltage against the input voltage. The phase correcting capacitor C1, for example, has a capacitance of 30 [pF]. The regulator circuit having the phase correcting capacitor C1 does not oscillate, even if it is connected to the output capacitor Co with relative high ESR (e.g. 100 [Ω]).
    Fig. 2 shows open loop characteristics of the regulator circuit of Fig. 1 in a case where the output capacitor Co having the ESR of 100 [Ω] is connected to the regulator circuit.
    As shown in Fig. 2, phase difference between input and output signals is larger than a necessary phase margin (e.g. 45°) in a frequency range from 0.01 to 10000 [kHz]. Accordingly, the regulator circuit does not oscillate in the case of Fig. 2.
    Though the phase correcting capacitor C1 is effective in the case where the output capacitor Co has the relative high ESR, it is ineffective in a case where the output capacitor Co has relative low ESR (e.g. equal to or less than 0.1 [Ω]).
    Fig. 3 shows open loop characteristics of the regulator circuit of Fig. 1 in a case where the output capacitor Co having the ESR of 0.01 [Ω] is connected to the regulator circuit.
    As illustrated in Fig. 3, the phase difference between the input and the output signals is lower than the necessary phase margin (45°) in a frequency range over 20 [kHz]. In addition, when the phase difference is equal to 0° (or 360°), the regulator circuit has a positive gain. Therefore, the regulator oscillates in the case of Fig. 3.
    The open loop characteristics of the regulator circuit can be improved by miniaturizing components (or devices) of the regulator circuit. When the frequency characteristics of the regulator circuit are improved, the necessary oscillation margin can be secured. Accordingly, the regulator circuit having miniaturized components does not oscillate even if the output capacitor connected thereto has the relative low ESR.
    However, an advanced micro processing is necessary to manufacture the regulator circuit having the miniaturized components. Therefore, the regulator circuit having the miniaturized components is expensive.
    Referring to Figs. 4 to 6, the description will be proceed to a regulator circuit according to a preferred embodiment of this invention.
    Fig. 4 is a circuit diagram of the regulator circuit (or a series regulator IC). The regulator circuit is basically similar to the related regulator circuit of Fig. 1 and different in having a phase correcting circuit portion 40 including a phase correcting capacitor C1'.
    In detail, the regulator circuit comprises a constant current source 11, first to tenth transistors M1-M10, first to third resistors R1-R3 and the phase correcting circuit portion 40.
    The phase correcting circuit portion 40 comprises an eleventh transistor M11, forth and fifth resistors R4 and R5, and the phase correcting capacitor C1'. For example, the forth and the fifth resistors R4 and R5 has resistance of 60 [kΩ] and 100 [kΩ] respectively, while the phase correcting capacitor C1' has capacitance of 5 [pF].
    The constant current source 11 and the first to the eighth transistors M1-M8 form an error amplifier (as an error amplifying means) to produce an error signal according to two input signals (i.e. a divided voltage and a reference voltage as mentioned below).
    The first and the second transistors M1 and M2 comprise N channel FETs (e.g. MOS FETs) which are identical to each other. The first and the second transistors M1 and M2 have sources connected to the constant current source 11 in common, and drains connected to those of the third and the fifth transistors M3 and M5. A gate of the first transistor M1 is connected to a connection point between the first and the second resistors R1 and R2. A gate of the second transistor M2 is connected to a reference voltage producing circuit (not shown) to receive the reference voltage produced by the reference voltage producing circuit. The first and the second transistors M1 and M2 divides a constant current produced by the constant current source 11 according to the difference between voltages supplied to the gates of the first and the second transistors M1 and M2.
    The third and the fourth transistors M3 and M4 comprise P channel FETs (e.g. MOS FETs) which are identical to each other. The third and the fourth transistors M3 and M4 have sources connected to a power supply terminal VDD, and gates connected to a drain of the third transistor M3. The drain of the third transistor M3 is connected to the drain of the first transistor M1. A drain of the fourth transistor M4 is connected to a drain of the seventh transistor M7. The third and the fourth transistors M3 and M4 form a first current mirror circuit to supply a current equivalent to that flowing through the first transistor M1 to the seventh transistor M7.
    The fifth and the sixth transistors M5 and M6 are similar to the third and the fourth transistor M3 and M4. That is, the fifth and the sixth transistors M5 and M6 comprise P channel FETs (e.g. MOS FETs) which are identical to each other. The fifth and the sixth transistors M5 and M6 have sources connected to a power supply terminal VDD, and gates connected to a drain of the fifth transistor M5. The drain of the fifth transistor M5 is connected to the drain of the first transistor M1. A drain of the sixth transistor M6 is connected to a drain of the eighth transistor M8. The fifth and the sixth transistors M5 and M6 form a second current mirror circuit to supply a current equivalent to that flowing through the second transistor M2 to the eighth transistor M8.
    The seventh and the eighth transistors M7 and M8 comprise N channel FETs (e.g. MOS FETs) which are identical to each other. The seventh transistor M7 has a source connected to the grounding terminal GND, and a gate connected to both of the drain thereof and one of the terminals of the fifth resistor R5 of the phase correcting circuit portion 40. On the other hand, the eighth transistor M8 has a source connected to the grounding terminal GND, and a gate connected to the other terminal of the fifth resistor R5 of the phase correcting circuit portion 40. The eighth transistor M8 is referred to as an error signal producing transistor. The seventh and the eighth transistors M7 and M8 form a third current mirror circuit to generate a voltage (i.e. the error signal) at the drain of the eighth transistor M8 according to a difference between currents supplied from the fourth and the sixth transistors M4 and M6.
    The ninth transistor M9 comprises an N channel FET. The ninth transistor M9 has a source connected to the grounding terminal GND, a drain connected to a gate of the tenth transistor M10, and a gate connected to the drain of the eighth transistor M8 (and to the drain of the sixth transistor M6). The ninth transistor M9 cooperates with a third resistor R3 to generate a voltage (i.e. a control voltage) at the gate of the tenth transistor M10 according to a gate voltage (i.e. the error signal supplied from the error amplifier) of the ninth transistor M9.
    The tenth transistor M10 comprises a P channel FET. The tenth transistor M10 has a source connected to the power supply terminal VDD and to the gate thereof through the third resistor R3. A drain of the tenth transistor M10 connected to the output terminal VOUT. The tenth transistor M10 regulates an input voltage (or a power supply voltage) supplied to the power supply terminal VDD from the power supply PW to produce an output voltage (or a regulated voltage) supplied to the output terminal VOUT. The tenth transistor M10 is referred to as an output transistor.
    The ninth and the tenth transistors M9 and M10 and the third resistor R3 serve as an output circuit means.
    The first and the second resistors R1 and R2 are connected to each other between the output terminal VOUT and the grounding terminal GND. As mentioned above, the connection point between the first and the second resistors R1 and R2 is connected to the gate of the first transistor M1. The first and the second resistor R1 and R2 divide the output voltage supplied to the output terminal VOUT to produce the divided voltage supplied to the gate of the first transistor M1.
    The eleventh transistor M11 comprises a P channel transistor. The eleventh transistor M11, together with the tenth transistor M10, forms a current mirror circuit. The eleventh transistor M11 is referred to as a correcting circuit transistor or a feedback transistor. The eleventh transistor M11 has a source connected to the power supply terminal VDD, a drain connected to the grounding terminal GND through the fourth resistor R4, and a gate connected to the gate of the tenth transistor M10.
    The fourth resistor R4 is referred to as a current-voltage-converting resistor. The fourth resistor R4 cooperates with the eleventh transistor M11 produces a feedback voltage proportional to (or equivalent to) the output voltage at a connection point between the fourth resistor R4 and the eleventh transistor M11. That is, the fourth resistor R4 and the eleventh transistor M11 serves as a feedback voltage producing means. The feedback voltage is not influenced by an output capacitor Co (especially, its ESR) connected to the output terminal VOUT. This is because the source of the eleventh transistor M11 is not connected to the output terminal VOUT but to the power supplying terminal VDD.
    The phase correcting capacitor C1' has a pair of terminals, one of which is connected to the connection point between the eleventh transistor M11 and the fourth resistor R4, and the other of which is connected to the gate of the eighth transistor M8. IN other words, the other of the terminals of the phase correcting capacitor is connected to both of the resistor R5 and the eighth transistor M8. The phase correcting capacitor C1' varies the gate voltage of the eighth transistor M8 according to the feedback voltage to correct the error signal output from the error amplifier. Thus, the phase correcting capacitor C1' and the resistor R5 serve as a phase correcting means.
    With the above mentioned structure, the regulator circuit of Fig. 4 regulates the input voltage supplied to the power supply terminal VDD to produce the regulated voltage. The regulator circuit supplies the regulated voltage to the output terminal VOUT as the output voltage.
    The phase correcting circuit 40 is connected between the input terminal VDD and the output transistor M10 as mentioned above. That is, the phase correcting circuit 40 is provided at a power supplying terminal side of the output terminal 10. Accordingly, the phase correcting circuit 40 can execute phase correction without influence of the output capacitor Co (or its ESR) when the regulator circuit regulates the power supply voltage. That is, the phase correcting circuit 40 feeds the feedback voltage proportional to the output voltage to the error amplifier regardless of the output capacitor Co (or the ESR) and corrects the error signal output from the error amplifier to suppress variation of the output voltage. Thus, the regulator circuit of this embodiment can execute the phase correction between the input and the output voltages regardless of the ESR of the output capacitor Co. Therefore, the regulator circuit secures the necessary phase margin regardless of a frequency of variation of the power supply voltage. At least, the necessary phase margin is secured for the ESR from 10 [mΩ] to 100 [Ω].
    Fig. 5 shows open loop characteristics of the regulator circuit of Fig. 4 in a case where the output capacitor Co having the ESR of 100 [Ω] is connected to the regulator circuit. The regulator circuit is manufactured by means of normal fine processing while each transistor included in the regulator circuit has a channel length of 1.2 [µm].
    As shown in Fig. 5, phase difference between input and output signals is larger than the necessary phase margin (e.g. 45°) over a frequency range from 0.01 to 10000 [kHz]. Accordingly, the regulator circuit does not oscillate in the case of Fig. 5.
    Fig. 6 shows open loop characteristics of the regulator circuit of Fig. 4 in a case where the output capacitor Co has the ESR of 0.01 [Ω].
    As illustrated in Fig. 6, the necessary phase margin (45°) is secured in a frequency range under 1000 [Hz]. In addition, the regulator circuit has negative gain in a frequency range over 1000 [Hz]. Accordingly, the regulator circuit does not oscillate over a frequency range from 0.01 to 10000 [kHz].
    As mentioned above, the regulator circuit of this embodiment can be used with the output capacitor having a small capacitance and low ESR, even if it is manufactured by the normal fine processing. Therefore, the regulator circuit is inexpensive.
    Each feature disclosed in this specification (which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.
    Statements in this specification of the "objects of the invention" relate to preferred embodiments of the invention, but not necessarily to all embodiments of the invention falling within the claims.
    The description of the invention with reference to the drawings is by way of example only.
    The text of the abstract filed herewith is repeated here as part of the specification
    A regulator circuit comprises a phase correcting circuit portion. The phase correcting circuit portion comprises a current correcting transistor M11 combined with an output transistor to form a current mirror circuit. An I-V converting resistor R4 is connected to the current correcting transistor M11 to convert a current flowing through the phase correcting circuit portion into a feedback voltage which is proportional to an output voltage and independent of an output capacitor Co. A phase correcting capacitor C1 and a resistor R5 corrects the error signal according to the feedback voltage.

    Claims (9)

    1. A regulator circuit for use with an output capacitor connected to an output terminal thereof, comprising a phase correcting capacitor for preventing oscillation of the circuit, characterized in that:
      said phase correcting capacitor is isolated from said output capacitor.
    2. A regulator circuit as claimed in Claim 1, comprising a power supply terminal and an output transistor connected between said power supply terminal and said output terminal, wherein
         said phase correcting capacitor is included in a phase correcting circuit portion provided on the power supply terminal side of said output transistor.
    3. A regulator circuit as claimed in Claim 2, wherein said phase correcting circuit portion comprises:
      a feedback transistor combined with said output transistor to form a current mirror circuit; and
      an I-V converting resistor connected to said feedback transistor at a connection point for converting a current flowing through said correcting transistor into a feedback voltage;
      said phase correcting capacitor having a terminal connected to said connection point.
    4. A regulator circuit as claimed in Claim 3, comprising an error amplifier for producing an error signal according to difference between a divided voltage derived from an output voltage and a reference voltage by the use of an error signal producing transistor, wherein
         another terminal of said phase correcting capacitor is connected to said error signal producing transistor.
    5. A regulator circuit as claimed in Claim 4, comprising another transistor combined with said error signal producing transistor to form another current mirror circuit, wherein
         said phase correcting circuit portion further comprises another resistor connected between said error signal producing transistor and the other transistor,
         the said other terminal of said phase correcting capacitor is connected to both of said resistor and said error signal producing transistor.
    6. A regulator circuit claimed in Claim 1, comprising:
      an error amplifying means for producing an error signal according to a difference between a reference voltage and a divided voltage derived from an output voltage supplied to said output terminal;
      an output circuit means for producing the output voltage according to the error signal;
      a feedback voltage producing means for producing a feedback voltage equivalent to the output voltage from the input voltage; and
      a phase correcting means connected to both of said feedback voltage producing means and said error amplifying means and including said phase correcting capacitor for correcting phase of the error signal according to the feedback output voltage.
    7. A regulator circuit as claimed in Claim 6, wherein
         said output circuit means comprises an output transistor, and wherein
         said feedback voltage producing means comprises a feedback transistor combined with said output transistor for forming a current mirror circuit; and
         a resistor connected to said feedback transistor at a connection point for converting a current flowing through said feedback transistor into the feedback voltage, and wherein
         said phase correcting capacitor is connected between said connection point and said error amplifying means.
    8. A method for preventing a regulator circuit from oscillating, said regulator circuit regulating an input voltage to produce an output voltage according to an error signal based on difference between a reference voltage and a divided voltage derived from the output signal, characterized by the steps of:
      producing a feedback voltage equivalent to said output voltage, and
      correcting the phase of said error signal according to said feedback voltage.
    9. A regulator circuit configured to regulate an input voltage to produce an output voltage according to an error signal based on a difference between a reference voltage and a divided voltage derived from the output signal, characterized by means for producing a feedback voltage equivalent to the output voltage and means for correcting the phase of the error signal according to the feedback voltage.
    EP04251107A 2003-04-15 2004-02-27 Voltage regulator circuit with oscillation suppression Withdrawn EP1469367A3 (en)

    Applications Claiming Priority (2)

    Application Number Priority Date Filing Date Title
    JP2003110435 2003-04-15
    JP2003110435A JP4016273B2 (en) 2003-04-15 2003-04-15 Regulator circuit

    Publications (2)

    Publication Number Publication Date
    EP1469367A2 true EP1469367A2 (en) 2004-10-20
    EP1469367A3 EP1469367A3 (en) 2005-07-06

    Family

    ID=32906016

    Family Applications (1)

    Application Number Title Priority Date Filing Date
    EP04251107A Withdrawn EP1469367A3 (en) 2003-04-15 2004-02-27 Voltage regulator circuit with oscillation suppression

    Country Status (2)

    Country Link
    EP (1) EP1469367A3 (en)
    JP (1) JP4016273B2 (en)

    Cited By (1)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    CN115857617A (en) * 2022-11-24 2023-03-28 佛山科学技术学院 Radiation-resistant self-bias low dropout regulator circuit based on CAFVF

    Families Citing this family (4)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    JP2006099500A (en) * 2004-09-30 2006-04-13 Mitsumi Electric Co Ltd Regulator circuit
    JP2006127225A (en) 2004-10-29 2006-05-18 Torex Device Co Ltd Power circuit
    JP4527592B2 (en) * 2005-04-18 2010-08-18 株式会社リコー Constant voltage power circuit
    KR100923706B1 (en) 2007-07-09 2009-10-27 인티그런트 테크놀로지즈(주) Differential phase compensator and amplification circuit including the same

    Family Cites Families (3)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    US5182526A (en) * 1991-07-18 1993-01-26 Linear Technology Corporation Differential input amplifier stage with frequency compensation
    JP3442942B2 (en) * 1996-10-08 2003-09-02 シャープ株式会社 Output drive circuit of DC stabilized power supply circuit
    US6300749B1 (en) * 2000-05-02 2001-10-09 Stmicroelectronics S.R.L. Linear voltage regulator with zero mobile compensation

    Cited By (1)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    CN115857617A (en) * 2022-11-24 2023-03-28 佛山科学技术学院 Radiation-resistant self-bias low dropout regulator circuit based on CAFVF

    Also Published As

    Publication number Publication date
    JP4016273B2 (en) 2007-12-05
    JP2004318407A (en) 2004-11-11
    EP1469367A3 (en) 2005-07-06

    Similar Documents

    Publication Publication Date Title
    US7986188B2 (en) Non-inverting amplifier circuit, semiconductor integrated circuit, and phase compensation method of non-inverting amplifier circuit
    US7242169B2 (en) Method and apparatus for voltage compensation for parasitic impedance
    US7038530B2 (en) Reference voltage generator circuit having temperature and process variation compensation and method of manufacturing same
    US7030686B2 (en) Constant voltage circuit with phase compensation
    US9152164B2 (en) Constant current source circuit
    JP2003015750A (en) Dynamic input stage bias for low quiescent current amplifier
    US9395730B2 (en) Voltage regulator
    JP5864086B2 (en) Differential amplifier circuit
    CN113448372A (en) Compensation of low dropout voltage regulator
    US10775822B2 (en) Circuit for voltage regulation and voltage regulating method
    US7538537B2 (en) Constant-voltage circuit and controlling method thereof
    US7224208B2 (en) Voltage regulator which outputs a predetermined direct-current voltage with its extreme variation restrained
    JP3106216B2 (en) Reference voltage generator for integrated circuits
    US7420414B2 (en) Amplifier, and step-down regulator and operational amplifier using the amplifier
    US12487621B2 (en) Low dropout regulator
    US7289308B2 (en) Overcurrent protection circuit
    US8089326B2 (en) PVT-independent current-controlled oscillator
    EP1469367A2 (en) Voltage regulator circuit with oscillation suppression
    JP2003177829A (en) Regulator circuit
    WO2020250349A1 (en) Constant voltage circuit and electronic device
    EP1510897B1 (en) Noise filter circuit
    JP2010277192A (en) Voltage regulator
    JP5198971B2 (en) Oscillator circuit
    JP2007140755A (en) Voltage regulator
    US20250306620A1 (en) Voltage regulator and semiconductor device

    Legal Events

    Date Code Title Description
    PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

    Free format text: ORIGINAL CODE: 0009012

    AK Designated contracting states

    Kind code of ref document: A2

    Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

    AX Request for extension of the european patent

    Extension state: AL HR LT LV MK

    PUAL Search report despatched

    Free format text: ORIGINAL CODE: 0009013

    AK Designated contracting states

    Kind code of ref document: A3

    Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

    AX Request for extension of the european patent

    Extension state: AL LT LV MK

    AKX Designation fees paid
    REG Reference to a national code

    Ref country code: DE

    Ref legal event code: 8566

    STAA Information on the status of an ep patent application or granted ep patent

    Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

    18D Application deemed to be withdrawn

    Effective date: 20060110