EP1457096B1 - Electronic ballast and operating method for a gas discharge lamp - Google Patents

Abstract

The device has a d.c. voltage converter (3) supplied by a d.c. voltage source (1,2) with a clocked switch and a regulated output voltage to an inverter (4) and a regulating circuit (7) producing a pulse width modulated switch-on pulse for the switch. The regulating circuit has two counters (Z1,Z2). The first counter has at least as many stages as the second and is reversible depending on whether an actual signal exceeds a desired signal.

Description

The invention relates to an electronic ballast and an operating method for a gas discharge lamp, with a fed from a DC voltage DC converter with clocked switch and regulated output voltage, fed from the DC output voltage of the DC converter inverter, and a control circuit which a setpoint signal and a DC output voltage of the DC converter corresponding Actual signal is supplied, and generates as a control value pulse width modulated turn-on for the clocked switch.

Such an electronic ballast is known, for example, according to US 5,705,897.

The DC voltage source for such an electronic ballast is normally a rectifier connected to the mains. The DC converter then forms a PFC (PFC = power factor correction), whose task is to appear to the network as quasi ohmic load. At the input of the DC converter are the mains half-waves. The input current is formed by pulses whose amplitude also represent sine half-waves. There is no phase shift between the half-waves of the input voltage and the half-waves formed by the amplitudes of the current pulses, so that a blind load of the network avoided and a generation of interfering harmonics is reduced to an acceptable level.

Various types of DC converters are known, which are described, for example, in the book by U. Tietze and Ch. Schenk "Halbleiterschaltungstechnik", Springer-Verlag 1991, 9th edition, pages 561 to 586. Common to all is that they contain at least one clocked switch and at least two memory elements. For electronic ballasts usually an up-converter type is used, which - seen from the input to the output - from a charge choke in a first longitudinal branch, a clocked switch in a first shunt branch, a diode in a second longitudinal branch and a storage capacitor in a second shunt branch consists.

There has been a tendency for some time now to use electronic ballasts where possible in integrated circuit technology, i. ASIC (application specific integrated circuit).

US Pat. No. 5,748,460 discloses a power supply for imaging devices. The device has a first counter A and a second counter B.

The invention has for its object to provide a design for the control circuit for the clocked switch, which is also suitable for implementation in the context of an ASIC.

The object is achieved by the features of the independent claims. The dependent claims further advantageously form the central idea of the invention.

Fig. 1

ein Blockschaltbild eines elektronisches Vorschaltgerätes mit einer ersten Ausführungsform der erfindungsgemäßen Regelschaltung;

Fig. 2

Zeitdiagramme

• (a) des Zählverhaltens des zweiten Zählers,
• (b) des Verlaufs des durch die Ladedrossel fließenden Stromes,
• (c) des Rücksetzssignals (U_n) für den zweiten Zähler,
• (d) der Einschaltimpulse für den getakteten Schalter, und
• (e) der Systemtaktimpulse, die den Zählern zugeführt werden;

Fig. 3

ein Blockschaltbild einer verallgemeinerten Ausführungsform der erfindungsgemäßen Regelschaltung;

Fig. 4

eine vergrößerte Darstellung des FIR-Filters in der Schaltung von Fig. 3,

Fig.5a-c

den Verlauf des Strom durch die Ladespule in verschiedenen Szenarien, und

Fig.6a-c

verschiedene Möglichkeiten zum Start bzw. Reset des zweiten Zählers in Figuren 1 und 3.

Embodiments of the invention are described below with reference to the drawing. Show it:

Fig. 1

a block diagram of an electronic ballast with a first embodiment of the control circuit according to the invention;

Fig. 2

time charts

• (a) the counting behavior of the second counter,
• (b) the course of the current flowing through the charge throttle,
• (c) the reset signal (U _n ) for the second counter,
• (d) the turn-on pulses for the clocked switch, and
• (e) the system clock pulses supplied to the counters;

Fig. 3

a block diagram of a generalized embodiment of the control circuit according to the invention;

Fig. 4

an enlarged view of the FIR filter in the circuit of Fig. 3,

5a-c

the course of the current through the charging coil in different scenarios, and

6a-c

various options for starting or resetting the second counter in Figures 1 and 3.

The ballast shown in Fig. 1 comprises the circuit parts explained below. An RF filter 1 is connected to the network and supplies the filtered mains voltage to a rectifier circuit 2. The rectifier circuit 2 generates at its output half-waves of the mains voltage, which are supplied to the DC voltage converter 3. The DC voltage converter 3 generates at its output a voltage U, which is kept constant by regulation independent of changes in the load. The DC output voltage U of the DC converter 3 is supplied to an inverter 4, to which a load 5 is connected. The load 5 contains the gas discharge lamp to be operated with the electronic ballast.

It should be noted in advance that all components of the scheme described in more detail below can be performed by software, hardware or a hybrid solution. In particular, the (slow) counter Z1 can be implemented by means of software. The counter Z2 can preferably be formed by a hardware module.

The DC voltage converter 3 consists of a charging choke L in a first longitudinal branch, a clocked switch S in a first shunt branch, a diode D in a second longitudinal branch and a storage capacitor C in a second shunt branch.

The clocked switch S is turned on with pulse width modulated switch-on pulses. The turn-on pulses are shown in Fig. 2 (d). The switch-on time is designated there by t _on . The time interval between the input edges of the switch-on pulses is denoted by T.

When the switch S is switched to passage, flows through the charging inductor L, an increasing charging current i _L. When the switch S is switched to interruption, the energy stored in the choke (charging coil) L discharges via the diode D to the storage capacitor C. In the discharge phase, the current flowing through the charging choke L drops - as in FIG. 2 (b). recognizable - and finally reaches the zero point.

The longer the turn-on time t _{on of} the switch in comparison to the total time T, the higher the DC output voltage U of the DC converter 3 increases. If the switch-on pulses are shortened, the DC output voltage U decreases accordingly. By selective variation of the on-time t _on , it is thus possible to keep the output DC voltage U constant.

The Einschaltimpulansteuerung for the clocked switch S is carried out by the control circuit 7. The control circuit 7 is, for example, from an external reference value generator 13, the analog reference value U supplied _to the DC output voltage U. To produce the actual value U of the DC output voltage _U is a dc voltage sensor 14 ', the DC output voltage U measures the dc voltage converter. 3

With a zero-crossing detector 13 '(for example, a DC sensor as shown or a voltage divider), the point in time at which the DC current flowing through the charging inductor L reaches the zero point in the decaying phase is detected. To the mentioned In the present embodiment, the reset signal U _{n is} generated (see Fig. 2 (c)).

Moreover, it can also be concluded from the voltage applied at point 13 'to the zero point of the current through the charging throttle.

The control circuit 7 includes a first counter Z1 and a second counter Z2. The two counters Z1 and Z2 are connected to a system clock 11 which generates the system clock pulses CLK shown in FIG. 2 (e).

The second counter Z2 is operated only in the count-up direction and has, for example, 2 ⁹ counting stages, which are represented by the bits 0-8. The reset input of the second counter Z2 is connected to the DC current sensor 13 in the present embodiment. If the reset signal U _n occurs at the reset input, the current counting process of the second counter Z2 is aborted. At the same time, as shown in Fig. 2 (a), the second counter Z2 is reset, and a new counting operation is started. The reset operation of the second counter Z2 thus takes place at the time at which the DC current flowing through the charge inductor L reaches the zero point in the decaying phase (see above).

The first counter Z1 has, for example, 2 ²⁴ counting stages, which are represented by the bits 0-23. He can count in both directions, ie up and down.

With the first counter Z1 is the output of a further (here) 1-bit A connected / D converter 10, whose two inputs _is the analog feedback signal U and the analog reference value signal U _to be supplied. At the output of the 1-bit A / D converter, a digital signal is output in the form of ONE or ZERO. The digital value ONE is generated while if the feedback signal U _is greater than or equal to the desired value signal U _soll is. The digital value becomes zero generated accordingly, if the feedback signal U _is less than _to the reference signal U.

When the digital counter NULL is supplied to the first counter Z1, it counts up. If the digital value ONE is supplied to him, he counts down.

The counter readings of the 2 ⁹ counting stages of the second counter Z 2 are compared by a comparator 12 with the corresponding 2 ⁹ higher-order counting stages of the first counter Z 1. The 2 ⁹ higher-order counting stages of the first counter Z1 are represented by the bits 15-23. The digital comparator 12 determines the point in time at which the bits of the two counters Z1 and Z2 to be compared match and reports this coincidence to a control circuit 14 for the switch S. The control circuit 14 also receives the reset signal U _n generated by the DC voltage sensor 13 fed. The control circuit 14 turns on the switch S, that is, in the conductive state when it receives the reset signal U _n , and turns off the switch S, that is, in the off state when the comparator 12 compares the counter readings of the comparators Bits of the two counters Z1 and Z2 reports.

The control of the inverter 4 via a circuit block 9, which takes over the lamp frequency management.

Due to the high number of counter stages of the counter Z1, the control frequency is relatively low, and the rule changes are made in small steps. Due to the fact that the number of counting stages of the counter Z2 is considerably lower than that of the counter Z1, oversampling is ensured. For example, if the system clock operates at a clock frequency of 10 MHz, the switch S is switched at a switching frequency between 5 MHz and 39 kHz. By contrast, the control frequency determined by counter Z1 is only 75 Hz.

The low-order counting stages of the counter Z1, which are represented by the bits 0-14, practically serve as a digital integrator. The higher-order counting stages represented by bits 15-23, on the other hand, determine the on-time t _on for the switch S.

The DC voltage converter 3 forms a PFC intermediate circuit for the electronic ballast. It ensures that the ballast acts as an ohmic load to the mains.

Fig. 1 shows, as mentioned, a specific embodiment of the circuit principle according to the invention, while Fig. 3 shows a general representation of the inventive concept. In FIG. 3, only elements of the control circuit are shown for the sake of clarity, identical components in FIG. 3 to the components of the circuit shown in FIG. 1 being provided with the same reference numerals.

In general, the difference between the target value U _REF and the DC output voltage U of the direct-voltage converter corresponding actual value _U is passed through an A / D converter 15 as an n-bit information X _IS 3 is shown according to the invention as shown in Fig.. _{Is intended,} instead of a simple comparison between the reference value U and the actual value _U is now therefore also through which, in the circuit according to Fig. 1 provided comparator nor the amount of the control deviation between the two input values U _REF and U _is detected and taken into account in the further course of the control loop. These n-bit information X _IS is supplied to the first counter Z1, which in turn - depending on whether the reference value U _REF is _greater than the actual value U or vice versa - with proportional to the difference increment counts up or down.

The step size of this counter Z1 is thus variable and depends on the absolute value of the difference X _IST . If, for example, there is a high deviation between the setpoint U _REF and actual value U _is present, the step size is increased, as a result of this a faster adaptation of the switch-on time for the switch S is obtained. Conversely, _should with only slight variations between the setpoint value and actual value U U _is the increment of the counter are reduced Z1.

The step size is controlled via a digital filter, in particular an input block of the counter Z1 designed as a so-called FIR filter (FIR = Finite Impulse Response) 17. The digital filter can also be, for example, an IIR (Infinite Impulse Response) filter.

The upstream FIR filter 17 in the present embodiment is a linear time discrete system whose output represents the weighted sum of the current input signal as well as a certain number of past samples. The specific properties of the FIR filter can be adjusted by appropriate selection of the weighting coefficients.

According to the implementation in FIG. 3, this FIR filter 17 has an adder 18 which subtracts a predetermined digital reference value X _SOLL from the supplied value X _IST . The output of the adder 18 is supplied to two proportional terms 19, 20, which perform a multiplication by constants K1 and K2, respectively. The output of the proportional element 20 is supplied to a delay element 21, which delays the signal by one clock (z-1). The delayed value is then subtracted from the output value of the proportional element 19 in a further adder 22. The output value of the further adder 22 is then fed to the counting input of the first counter Z1.

Overall, the combination of the FIR filter 17 with the first counter Z1 forms a PI controller structure. The P component is achieved by the combination of the differentiating effect of the delay element 21 with the integrating action of the counter Z1. The I component is formed accordingly by the proportional element 19 and the counter Z1.

The data format of the input of the FIR filter 17 is usually smaller than that of the output. At least at the exit we preferably use a fixpoint format.

The output value of the counter Z1 is divided by a scaling element 23, for example by an integer factor, and the result Z1 'is passed on to the comparator 12 as the first input signal. If the integer factor is a power of "2", this scaling corresponds to reading out the high-order bits in FIG. 1. However, other integer values, but also floating-point values, can be used. Usually, however, the scaling factor will be greater than one.

Moreover, it is shown in FIG. 3 that the reset of the counter Z2, the switch-on operation of the switch S (by the signal START in FIG. 3) and the zero crossing of the current through the charging coil can be selected independently of one another by a logic unit 24.

The logic unit 24 is (optionally) supplied to the output signal of the zero point detector 13 '. Furthermore, the output signal of the comparator 12 is supplied to it. On the other hand, the logic unit 24 generates the RESET signal for the counter Z2 and the start signal START for the control unit 14 (for example a flip-flop), to which signal START the control unit 14 switches the switch S on (start of a switch-on pulse). The reset process of the counter Z2 may possibly also take place before the starting process of the counter Z2 and thus independently of the start of the counting process of the counter Z2. In this case, the counting of the counter Z2 (rising from zero) is also triggered by the signal START of the logic unit 24.

Basically, the logic unit 24, the start signal START for turning on the switch S upon detection of the zero crossing of the current through the charging sink and / or at the end of a defined time (eg., Generated by a Time base or another counter of the logic unit 24) output.

The resulting waveforms are shown in Figures 5a - 5c and will now be explained.

FIG. 5a shows the case that upon detecting the zero crossing of the current through the charging coil, the counter Z2 is restarted and the switch S is switched on (signal START). Regardless of this, the RESET operation of the counter Z2 is triggered by the signal RESET before the counting process starts. This can be done, for example, when the logic unit 24 detects that another counter (not shown) that has the function of a time base has reached a certain level (maximum level). It should be noted that the reset process continues to be independent and time after the switch S is turned off by the comparator 12, the counter Z2 thus continues to run for some time after the switch S is turned off.

FIG. 5b shows the case that once the zero-crossing of the current through the charging coil is detected, the counter Z2 is started and the switch S is switched on (signal START). However, there is no separate RESET and START signal for the counter Z2, but rather takes place in a RESET and start of Zählvorghangs the counter Z2 upon detection of the zero crossing.

Finally, FIG. 5c shows the case that the counter Z2 is not caused by a detection of the zero crossing of the current through the charging coil, but after a defined time has elapsed (for example, detected by a further counter), and restarted and at the same time Switch S is switched on (signal START). In this case, therefore, the switch-on of the switch S takes place at fixed intervals, however, the switch-on pulse duration is variable (PWM).

In any case, on the one hand the restart of the second counter Z2 coincides with the switching on of the switch S and on the other hand the switch S is switched off when the compared output signals of the two counters Z1, Z2 reach a tie.

Possible time profiles of the direct current through the charging choke in relation to the mains current are shown in FIGS. 6a-6c.

As shown in FIG. 6a, when the reset signal is used, the direct current through the charging choke immediately increases again, which is also called "borderline control".

As shown in Fig. 6b, may continue to be the case that at the time when the direct current has already dropped to zero by the throttle, the second counter Z2 has not yet reached its maximum level and the switch during a dead time on remains closed in which dead time no current flows through the throttle. This is also called "Discontinuous Conduction".

On the other hand, as shown in Figure 6c, the case may occur that the counter Z2 reaches its maximum at a time when the current through the inductor has not yet decayed. By switching the switch accordingly, the direct current through the reactor will never drop to zero as in this case. This is called "Continuous Conduction".

The circuit shown in Fig. 3 is a general representation of the present invention, which opens in the case of n> 1 by the higher compared to the comparator resolution of the A / D converter 15, the amount of deviation between the setpoint U _setpoint and actual value U _must be taken into account. In the case that the A / D converter 15 is used as a 1-bit converter and for the multiplication factors, the values K ₁ = 2 and K ₂ = 0 (das In this case, the integrator element has no function) and as a digital reference value 0.5, the special case of a 1-bit PFC is again obtained. The following applies to the processing of the signals:

If the current actual value U _is the DC output voltage is greater than the target voltage _to U, the 1-bit A / D converter 15 outputs the value 1. The value obtained from the comparison block 18 is then -1 + 0.5 = -0.5. The value calculated by the P-element 19 and thus the input block 17 is -0.5 * 2 = -1 in this case, ie the counter Z1 counts down if the value of the DC output voltage is too high, whereby the switch-on time for the switch S is shortened. On the other hand is the DC output voltage U _{is intended to} below the nominal voltage U, the 1-bit A / D converter 15 outputs to 0. The value obtained from the comparison block 18 is then 0 + 0.5 = +0.5 and the value supplied to the counter Zl is 0.5 * 2 = 1. In this case, the first counter Z1 thus counts up. This 1-bit variant thus represents a particularly simple way of regulating the output DC voltage.

Both in the 1-bit variant as well as in general n-bit form, the circuit according to the invention has the advantage that it consists of standardized digital circuit components, which can be well integrated into an ASIC design in the sense of the task.

Claims (14)

1. Electronic ballast for a gas discharge lamp having a d.c. voltage converter (3) with clocked switch (S) and regulated output d.c. voltage (U), fed from a d.c. voltage source (1, 2), an inverter (4) fed from the output d.c. voltage (U) of the d.c. voltage converter (3), and a regulation circuit (7) to which there is delivered a desired value signal (U_soll) and an actual value signal (U_ist) corresponding to the output d.c. voltage of the d.c. voltage converter, and which generates switch-on pulses for the clocked switch (S) as setting value signal,
   characterized in that,
   the regulation circuit (7) comprises a first and a second counter (Z1, Z2),
   in that the bit width of the first counter (Z1) is at least equal to the bit width of the second counter (Z2),
   in that the first counter (Z1) is a counter with reversible count direction, which counts in the one or the other direction in dependence upon whether the actual value signal (U_ist) is greater or smaller than the desired value signal (U_soll),
   in that a comparator (10) compares the output signals of the two counters (Z1, Z2) for obtaining the setting value signal, and
   in that the pulse width of the switch-on pulses for the clocked switch is determined by the temporal spacing (t_on) between one switch-on signal (START; U_n) for the switch (S) and the temporally following attainment of the equality of the count stages compared with one another,
   wherein at the switch-on time point of the switch (S) the second counter carries out a new count process.
2. Electronic ballast according to claim 1,
   characterized in that,
   the bit width of the first counter (Z1) is greater than the bit width of the second counter (Z2), and in that in the comparator (12) the output signal of the second counter (Z2) is compared with an output signal of the first counter (Z1) divided by a scaling factor.
3. Electronic ballast according to any preceding claim,
   characterized in that,
   the d.c. voltage converter (3) is an up-converter having - seen from input to output - a charge coil (L) in a first series branch, having the switch (S) in a first transverse branch, a diode (D) in a second longitudinal branch and a charge capacitor (C) in a second transverse branch.
4. Electronic ballast according to claim 3,
   characterized in that,
   a zero point detector (13) for the d.c. current flowing through the charge coil (L) of the d.c. voltage converter (3) is connected with a logic unit (24) which brings about the start procedure of the second counter (Z2) and the simultaneous switching on of the switch (S), as soon as the zero point detector (13) detects the zero crossing of the current through the charge coil.
5. Electronic ballast according to any of claims 1 to 3,
   characterized in that,
   a logic unit (24) closes the switch (S) in each case after passage of a predetermined duration of time and simultaneously causes the second counter (Z2) to effect a new start procedure.
6. Electronic ballast according to any preceding claim,
   characterized in that,
   the actual value signal (U_ist) is generated by means of a d.c. voltage sensor (14'), which measures the output d.c. voltage (U) of the d.c. voltage converter (3),
   in that the actual value signal (U_ist) and the desired value signal (U_soll) are delivered in analog form to the two inputs of an A/D converter (10, 15), which compares these two signals and on the output side generates a digital value dependent upon the difference between the actual value signal (U_ist) and the desired value signal (U_soll),
   in that the output of the A/D converter (10, 15) is connected with the first counter (Z1), and
   in that the first counter (Z1) carries out a count process in dependence upon the output value of the A/D converter (10, 15).
7. Electronic ballast according to claim 6,
   characterized in that,
   the step width of the first counter is variable and depends upon the output value of the A/D converter (15).
8. Electronic ballast according to claim 7,
   characterized in that,
   a digital filter (17) is connected upstream of the first counter (Z1).
9. Method of operating an electronic ballast for a gas discharge lamp having a d.c. voltage converter (3) with clocked switch (S) and regulated output d.c. voltage (U), fed from a d.c. voltage source (1, 2), an inverter (4) fed from the output d.c. voltage (U) of the d.c. voltage converter (3), and a regulation circuit (7) to which there is delivered a desired value signal (U_soll) and an actual value signal (U_ist) corresponding to the output d.c. voltage of the d.c. voltage converter, and which generates switch-on pulses for the clocked switch (S),
   having the following steps:

   - comparison (10, 15) of the actual value signal with the desired value signal for generating a digital difference signal (X_ist),

   - delivery of the digital difference signal (X_ist) to the count input of a first counter (Z1), the count direction of which depends upon the sign of the digital difference signal (X_ist),

   - comparison of the count or the scaled count of the first counter with the count of a second counter (Z2), which begins a count process in each case in response to a start or RESET signal,

   - switching on of the switch (S) and starting of the second counter (Z2) in each case after expiry of a predetermined time or when the current through a charge coil (L) of the d.c. voltage converter reaches the zero point, and

   - switching off the switch (S) when the count or the scaled count of the first counter is equal to the count of the second counter (Z2).
10. Method according to claim 9,
    characterized in that,
    the bit width of the first counter (Z1) is greater than the bit width of the second counter (Z2), and in that the output signal of the second counter (Z2) is compared with an output signal of the first counter (Z1) divided by a scaling factor.
11. Method according to claim 9 or 10,
    characterized in that,
    the actual value signal (U_ist) is generated by means of a d.c. voltage sensor (14'), which measures the output d.c. voltage (U) of the d.c. voltage converter (3),
    in that the actual value signal (U_ist) and the desired value signal (U_soll) are delivered in analog form to the two inputs of an A/D converter (10, 15), which compares these two signals and on the output side generates a digital value dependent upon the difference between the actual value signal (U_ist) and the desired value signal (U_soll),
    in that the output of the A/D converter (10, 15) is connected with the first counter (Z1), and
    in that the first counter (Z1) carries out a count process in dependence upon the output value of the A/D converter (10, 15).
12. Electronic ballast according to claim 11,
    characterized in that,
    the step width of the first counter is variable and depends upon the output value of the A/D converter (15).
13. Method according to any of claims 9 to 12,
    characterized in that,
    the digital difference signal (X_ist) is digitally filtered.
14. Method according to claim 13,
    characterized in that,
    the digital filtering is a FIR filtering or IIR filtering.

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