EP1450536A1 - Routage de flux de donnees - Google Patents
Routage de flux de donnees Download PDFInfo
- Publication number
- EP1450536A1 EP1450536A1 EP03251091A EP03251091A EP1450536A1 EP 1450536 A1 EP1450536 A1 EP 1450536A1 EP 03251091 A EP03251091 A EP 03251091A EP 03251091 A EP03251091 A EP 03251091A EP 1450536 A1 EP1450536 A1 EP 1450536A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- packet
- destination
- stream
- streams
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding in a switch fabric
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/103—Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
Definitions
- the present invention relates to the routing of data streams, and in particular streams constituted by data packets.
- a transport stream multiplexer (TSMUX) has been implemented which can route a data stream received as an input to any one of a number of outputs. It is an aim of the present invention to expand the capabilities so that a number of input streams can be merged and can be directed to one or more of a plurality of output destinations.
- the preferred embodiment of the invention provides an intellectual property (block of logic) known as TSmerger which merges multiple lower bit rate transport streams to a single higher bit rate transport stream for processing by a single programmable transport interface (PTI). For example, nine input streams can be merged into three output streams, with each input stream being able to be routed to any output stream, or to multiple destinations.
- TSmerger intellectual property (block of logic) known as TSmerger which merges multiple lower bit rate transport streams to a single higher bit rate transport stream for processing by a single programmable transport interface (PTI).
- PTI programmable transport interface
- the TSmerger IP is implemented by storing packets of incoming streams in a single SRAM in a stream merger unit, which effectively behaves as a series of first-in first-out buffers (FIFOs).
- FIFOs first-in first-out buffers
- the TSmerger unit itself is capable of merging the lower bit rate transport streams to individual higher bit rate streams for processing by respective single PTIs.
- Each input stream can be routed to any output stream, and each input stream may be distributed to multiple output streams and thereby to multiple destinations.
- the TSmerger unit 2 illustrated in Figure 1 includes a memory (SRAM) 3 for holding packets of the input streams, a packet allocation table 4 (PAT), a source to destination matrix 6 and a processing means 8 which implements an algorithm to control removal of packets from the SRAM 3.
- SRAM memory
- PAT packet allocation table 4
- SRAM source to destination matrix 6
- processing means 8 which implements an algorithm to control removal of packets from the SRAM 3.
- the algorithm 8 controls the removal of packets from the SRAM 3 to the destinations dest0, dest1, dest2 in such a way as to maintain maximum bandwidth, while allowing any source stream to go to any destination. Packets from multiple sources are merged without breaking individual packets (i.e. streams are merged at the packet level and not at the byte level) and packets from a single stream are read from the SRAM in the correct order, that is in the order in which they arrived.
- each packet is only read from the SRAM 3 once, so that if a packet from a particular input port is destined for more than one destination, it can only be output from the SRAM 3 when the ports for both of those destinations are free.
- the source to destination matrix 6 is a data structure illustrated in Figure 2. This matrix 6 maps sources to destinations and can be changed on the fly. The source numbers are indicated on the left hand side of the rows of the matrix, and the destinations are illustrated at the top of the columns of the matrix. A "1" in each square of the matrix indicates that that particular source is to be mapped to that particular destination. A "0" indicates that that source stream must not be mapped to that particular destination. As is clear from the matrix 6 in Figure 2, some source streams (from source 2 and source 4) are mapped to more than one destination.
- Figure 3 illustrates the packet allocation table 4 which takes the form of a second data structure.
- This data structure takes the form of an array consisting of a plurality of slots SLOT1, SLOT2, etc, each slot containing a source identifier src_id of a particular packet in association with the address addr which is the start address of that packet in the SRAM 3.
- the source identifier is inserted into the packet header of each packet at the respective input port of the merger unit at which the packet is received.
- the source identifier insertion circuitry is labelled 7 in Figure 1.
- the packet allocation table 4 includes a write pointer wr_pointer and three destination pointers, dest0, dest1, dest2 each associated with a particular destination as illustrated in Figure 1.
- the pointers are implemented in any suitable known way.
- Figures 4A to 4D illustrate how the algorithm assigns destination pointers.
- Figure 4A illustrates the state of the pointers as in Figure 3, that is with the dest0 and dest2 pointers directed at SLOT3 holding the packet from source 2 and dest1 pointer directed at SLOT4 holding the most recently loaded packet from source 1. This is the status when an incoming packet is newly loaded into the SRAM 3.
- the next temporary assignment of destination pointers is illustrated in Figure 4B.
- the source identifier in the next slot down of the array, SLOT2 is read which identifies source 4 SRC4. From the assignment matrix it is determined that packets from this source are destined for destinations 1 and 2 and therefore the destination pointers dest1, dest2 are realigned to this slot.
- the destination pointer dest0 is reassigned to null.
- Figure 4D illustrates the next pass in the final assignment.
- the source identifier in SLOT2 of the array identifies src 4 as the source which is destined for destinations 1 and 2.
- There is no point assigning the destination pointer dest2 to this packet because the destination pointer dest1 has already been assigned to the packet which is identified in the SLOT1 of the array and, for bandwidth reasons, the packet should be removed to both destination ports simultaneously. Therefore, no destination pointers are assigned to this slot.
- In the next slot is a packet from source 2 which is destined for destinations 0 and 2, and so these destination pointers are set for that slot.
- Figure 5D shows the effect of removing this packet, i.e. the one identified by the data in SLOT3 in Figure 5A, from the SRAM 3, before the one identified by the data in SLOT1.
- the data defining the subsequent packet moves up one slot in the array and the destination pointers dest0 and dest2 are reassigned to null.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03251091A EP1450536A1 (fr) | 2003-02-24 | 2003-02-24 | Routage de flux de donnees |
US10/779,466 US7720112B2 (en) | 2003-02-24 | 2004-02-16 | Routing of data streams |
US12/781,118 US20100290466A1 (en) | 2003-02-24 | 2010-05-17 | Routing of data streams |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03251091A EP1450536A1 (fr) | 2003-02-24 | 2003-02-24 | Routage de flux de donnees |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1450536A1 true EP1450536A1 (fr) | 2004-08-25 |
Family
ID=32731607
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP03251091A Withdrawn EP1450536A1 (fr) | 2003-02-24 | 2003-02-24 | Routage de flux de donnees |
Country Status (2)
Country | Link |
---|---|
US (2) | US7720112B2 (fr) |
EP (1) | EP1450536A1 (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104297593A (zh) * | 2014-10-13 | 2015-01-21 | 国家电网公司 | 一种用于智能变电站合并单元的守时误差检测方法 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6961595B2 (en) * | 2002-08-08 | 2005-11-01 | Flarion Technologies, Inc. | Methods and apparatus for operating mobile nodes in multiple states |
US7363039B2 (en) | 2002-08-08 | 2008-04-22 | Qualcomm Incorporated | Method of creating and utilizing diversity in multiple carrier communication system |
US8190163B2 (en) * | 2002-08-08 | 2012-05-29 | Qualcomm Incorporated | Methods and apparatus of enhanced coding in multi-user communication systems |
AU2004213988B2 (en) | 2003-02-19 | 2009-09-10 | Qualcomm Incorporated | Methods and apparatus of enhanced coding in multi-user communications systems |
US8593932B2 (en) | 2003-05-16 | 2013-11-26 | Qualcomm Incorporated | Efficient signal transmission methods and apparatus using a shared transmission resource |
US7925291B2 (en) * | 2003-08-13 | 2011-04-12 | Qualcomm Incorporated | User specific downlink power control channel Q-bit |
US20070211669A1 (en) * | 2006-03-07 | 2007-09-13 | Bhupesh Manoharlal Umatt | Method and apparatus for searching radio technologies |
RU2438256C2 (ru) | 2007-01-11 | 2011-12-27 | Квэлкомм Инкорпорейтед | Использование dtx и drx в системе беспроводной связи |
US8838911B1 (en) * | 2011-03-09 | 2014-09-16 | Verint Systems Inc. | Systems, methods, and software for interleaved data stream storage |
US9152580B1 (en) * | 2011-10-27 | 2015-10-06 | Marvell International Ltd. | Method and apparatus for transferring data between a host and an embedded device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5862128A (en) * | 1995-12-29 | 1999-01-19 | Gte Laboratories Inc | Merged buffer signal switch |
US5905725A (en) * | 1996-12-16 | 1999-05-18 | Juniper Networks | High speed switching device |
US6081522A (en) * | 1997-06-30 | 2000-06-27 | Sun Microsystems, Inc. | System and method for a multi-layer network element |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5555244A (en) * | 1994-05-19 | 1996-09-10 | Integrated Network Corporation | Scalable multimedia network |
US5712907A (en) * | 1995-09-18 | 1998-01-27 | Open Port Technology, Inc. | Pro-active message delivery system and method |
US5748630A (en) * | 1996-05-09 | 1998-05-05 | Maker Communications, Inc. | Asynchronous transfer mode cell processing system with load multiple instruction and memory write-back |
US6363075B1 (en) * | 1998-01-23 | 2002-03-26 | Industrial Technology Research Institute | Shared buffer management mechanism and method using multiple linked lists in a high speed packet switching system |
US5999531A (en) * | 1998-04-17 | 1999-12-07 | Cabletron Systems, Inc. | Method and system for identifying ports and forwarding packets in a multiport switch |
US6421348B1 (en) * | 1998-07-01 | 2002-07-16 | National Semiconductor Corporation | High-speed network switch bus |
US6304552B1 (en) * | 1998-09-11 | 2001-10-16 | Nortel Networks Limited | Memory and apparatus for input based control of discards in a lossy packet network |
US6266702B1 (en) * | 1998-09-28 | 2001-07-24 | Raytheon Company | Method and apparatus to insert and extract data from a plurality of slots of data frames by using access table to identify network nodes and their slots for insertion and extraction data |
US6687247B1 (en) * | 1999-10-27 | 2004-02-03 | Cisco Technology, Inc. | Architecture for high speed class of service enabled linecard |
US7009968B2 (en) * | 2000-06-09 | 2006-03-07 | Broadcom Corporation | Gigabit switch supporting improved layer 3 switching |
US7212494B1 (en) * | 2001-04-30 | 2007-05-01 | Cisco Technology, Inc. | In-band must-serve indication from scheduler to switch fabric |
US7218637B1 (en) * | 2001-07-20 | 2007-05-15 | Yotta Networks, Llc | System for switching data using dynamic scheduling |
US7382787B1 (en) * | 2001-07-30 | 2008-06-03 | Cisco Technology, Inc. | Packet routing and switching device |
-
2003
- 2003-02-24 EP EP03251091A patent/EP1450536A1/fr not_active Withdrawn
-
2004
- 2004-02-16 US US10/779,466 patent/US7720112B2/en active Active
-
2010
- 2010-05-17 US US12/781,118 patent/US20100290466A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5862128A (en) * | 1995-12-29 | 1999-01-19 | Gte Laboratories Inc | Merged buffer signal switch |
US5905725A (en) * | 1996-12-16 | 1999-05-18 | Juniper Networks | High speed switching device |
US6081522A (en) * | 1997-06-30 | 2000-06-27 | Sun Microsystems, Inc. | System and method for a multi-layer network element |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104297593A (zh) * | 2014-10-13 | 2015-01-21 | 国家电网公司 | 一种用于智能变电站合并单元的守时误差检测方法 |
CN104297593B (zh) * | 2014-10-13 | 2017-02-15 | 国家电网公司 | 一种用于智能变电站合并单元的守时误差检测方法 |
Also Published As
Publication number | Publication date |
---|---|
US20100290466A1 (en) | 2010-11-18 |
US20040228342A1 (en) | 2004-11-18 |
US7720112B2 (en) | 2010-05-18 |
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Effective date: 20070925 |
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Owner name: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITE |
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