EP1449252A2 - Electronic assembly - Google Patents

Electronic assembly

Info

Publication number
EP1449252A2
EP1449252A2 EP02779160A EP02779160A EP1449252A2 EP 1449252 A2 EP1449252 A2 EP 1449252A2 EP 02779160 A EP02779160 A EP 02779160A EP 02779160 A EP02779160 A EP 02779160A EP 1449252 A2 EP1449252 A2 EP 1449252A2
Authority
EP
European Patent Office
Prior art keywords
carrier
layer
electronic arrangement
signal
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02779160A
Other languages
German (de)
French (fr)
Inventor
Rainer Topp
Dirk Balszunat
Christoph Ruf
Andreas Fischer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP1449252A2 publication Critical patent/EP1449252A2/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4092—Integral conductive tabs, i.e. conductive parts partly detached from the substrate

Definitions

  • the invention relates to an electronic module according to the preamble of the main claim.
  • a power module is already known from WO 98/15005, in which power transistors are mounted between two DBC substrates (direct bonded copper) with structured CU layers as the wiring level, the connection of the chip front and back sides to the CU Paths are made over a solder layer. With the help of optionally usable spacer balls, it can be ensured, if necessary, that the solder layer on the structured metal tracks of the chip front sides maintains a sufficient thickness during and after the reflow soldering process.
  • a feature of the DBC substrates is that the CU layers cannot be structured as finely as desired due to their thickness - typically approx. 300 ⁇ . The thickness of the CU layer is necessary in order to be able to dissipate the lost heat of the power chips sufficiently and to be able to conduct the high currents in the module with as little resistance as possible. in this connection
  • a major disadvantage of the structure known from the prior art is that it is initially only suitable for the assembly of preferably roughly structured front connections of power chips and uniform chip thicknesses.
  • the result of this is that a combination of power components (power chips) and signal components (signal ICs) is not possible if the signal IC s have many finely structured front connections and if the signal IC s have chip thicknesses that differ significantly from the chip thicknesses of the Powerchips differ.
  • the electronic arrangement according to the invention with the features of the main claim therefore has the advantage over the prior art that a very simple and inexpensive expansion of the module structure is achieved in that the combination of power chips and power chips is made possible.
  • FIG. 1 shows a first exemplary embodiment of the electronic arrangement
  • Figure 3 shows an upper DBC substrate before punching and embossing
  • Figure 4 shows an upper DBC substrate after stamping and embossing.
  • FIG. 1 shows a module structure of an electronic arrangement according to the invention for a first embodiment of the invention.
  • the electronic arrangement comprises a first carrier 10 and a second carrier 11. Between the carriers 10, 11 there are generally a plurality of electronic circuits in the form of semiconductor chips, which are identified in FIG. 1 by the reference symbols 21, 22 and 23 , According to the invention, it is both possible to provide fewer than three semiconductor chips 21, 22, 23 between the carriers 10, 11 and also to provide a larger number of such semiconductor chips 21, 22, 23.
  • reference symbols 21 and 22 denote a first and second power semiconductor chip.
  • the power semiconductor chips 21, 22 are characterized in that, in particular, a large amount of heat, which may be dissipated in the power semiconductor chip 21, 22, is to be dissipated via thermal couplings.
  • the reference symbol 23 in FIG. 1 denotes a signal IC which is provided for signal processing. With the signal IC 23, the requirements for heat dissipation are generally much less pronounced than with the power semiconductor chips 21, 22.
  • the signal IC 23 is provided such that the semiconductor substrate of the signal IC 23 has a greater thickness than the semiconductor substrate of the two power semiconductor chips 21, 22.
  • the electronic arrangement according to the invention is also shown in FIG. 2, again the first carrier 10, the second carrier 11 and the semiconductor chips 21, 22, 23 being provided.
  • the thickness of the signal IC 23 is smaller than the thickness of the power semiconductor chips 21, 22.
  • FIG. 1 and FIG. 2 are described together, but the differences are discussed.
  • the essence of the present invention is the use of a special second carrier 11 in the form that the second carrier 11 has a finely structured contact layer in parts that can be adjusted at a distance from the lower first carrier 10, so that without changing the module assembly method compared to the prior art, cost-effective integration of signal IC chips into the overall module or into the entire electronic arrangement is made possible.
  • the first carrier 10 which is also referred to below as the lower carrier 10, comprises, as carrier substance, in particular a ceramic material on which a lower contact layer 8 is applied in partial areas - ie the lower contact layer 8 is provided in a structurable manner ,
  • the lower contacting layer 8 is provided in particular as a copper layer, which is also referred to below as the lower CU layer 8.
  • the lower support 10 together with the lower contacting layer situated on it is satisfiable indungshunt 8 'are provided in particular as a DBC substrate and is also referred to below as un- therefore teres DBC substrate 10th On the lower CU layer
  • the semiconductor chips 21, 22, 23 also have connections on their front side or on their top side, which are supplied by means of the second carrier or the upper carrier 11.
  • the upper carrier 11 is in particular also provided as a DBC substrate and is therefore also referred to as an upper DBC substrate 11.
  • the upper support 11 has recesses 12 in partial areas.
  • a contacting layer is also provided on the upper carrier 11, which bears the reference symbol 13 in the regions where the upper carrier has no recess 12 and which has the reference symbol 14 in the regions where the upper carrier 11 has recesses 12 is.
  • the upper con- Clocking layer 13, 14, which according to the invention is also in particular provided as a CU layer 13, 14, is used for contacting the top of the semiconductor chips 21, 22, 23.
  • the “free contacting layer” 14 is flexible within limits in a direction that is perpendicular to the plane ′ of the upper carrier 11. It is thus possible for the free contacting layer 14 in FIG.
  • the upper contact layer 13, 14 is therefore free , so that again by the upper contacting layer 13, 14 throughout both contacting ⁇ the power semiconductor chips 21, 22 as the signal IC chips is ensured 23 plastically deformed area 14 downwardly also.
  • the upper contacting layer 13, 14 is therefore arranged according to the invention in its area 13 not having a recess 12 in a first level and in its “free area” 14 at least partially in a second level that is different from the first level.
  • solder layer 15 is provided between the upper contacting layer 13, 14 and the semiconductor chips, which is not has spacer balls designated by means of a reference number.
  • FIG. 3 shows the upper carrier 11 with the upper contact layer 13.
  • the recess 12 is shown in the central region of the upper carrier 11 by means of a dotted rectangle.
  • the regions 13 of the upper contacting layer 13, 14 are again visible, which are provided in regions of the upper carrier 11 where the recess 12 is not provided.
  • the regions 14 of the upper contacting layer 13, 14, which are provided in the region of the recess 12, can also be seen.
  • the free areas 14 of the upper contacting layer 13, 14, for example by means of a stamping tool, in the area of the
  • Recess 12 are structured wider and finer than the structuring of the upper contact layer 13, 14 in the area of the upper carrier 11 at locations where the recess 12 is not provided.
  • FIG. 4 Such an additional and more extensive structuring is shown in FIG. 4, where the upper support 11 is shown with the upper structuring layer 13, 14 and the recess 12, but in FIG. 4, in contrast to FIG. 3, the more extensive structuring of the free areas
  • the structuring step which marks the transition from FIG. 3 to FIG. 4 is provided according to the invention in particular as a stamping and embossing process.
  • Other mechanical and / or other structuring methods are however also provided according to the invention.
  • both the geometric structuring of the free areas 14 of the upper contacting layer is carried out, ie structuring along the plane of the upper carrier 11, and the structuring in the orthogonal direction, ie the provision of deflections of the free ones Areas 14 of the upper contact layer 13, 14 for compensating for different chip thicknesses of the semiconductor chips provided in the area of the free areas 14 of the upper contact layer.
  • the invention it is therefore advantageously possible to carry out chips 21, 22, 23 with different thicknesses in a single electronic arrangement according to the invention in a sandwich construction. Furthermore, it is therefore advantageously possible according to the invention to enable the integration of signal ICs with finely structured connections and with a large number of connections into the electronic arrangement according to the invention, which is provided in particular as a power module. According to the invention, no additional parts are advantageously necessary for this. Furthermore, according to the invention there is the advantage of using an unchanged module assembly method, ie it is possible to assemble all of the chips in a reflow soldering process.
  • the electronic arrangement according to the invention is moreover possible in a cost-effective manner because the small additional expenditure for punching and embossing processing of the still unpopulated DBC substrate in one tool is already possible in multiple substrate uses.
  • substrate multiple use means the combination of several individual substrates for simultaneous processing.
  • both the signal ICs 23 and the power chips 21, 22 can be mounted in the same plane on the lower carrier 10 or its contact layer 8. As a result, the complete power module or the completely electronic arrangement can continue to be mounted flat on the front and the back, ie thermally optimal.
  • the signal ICs are mounted on the outer surface of the module and thus prevent cooling of the module on both sides.
  • the upper carrier 11 of the electronic arrangement according to the invention together with its contacting layer 13, 14, has the following properties according to the invention:
  • the structure of the DBC layer 11 remains unchanged compared to an upper carrier 11 without a recess 12.
  • the ceramic area of the substrate, i. of the upper beam 11, recessed - i.e. the recess 12 or the recesses 12 are provided - and the originally typically 300 ⁇ m thick contact layer 13, 14 is changed by a stamping and embossing process such that a finely structured and in height, i.e.
  • contacting of the signal IC 23 adapted to the IC thickness of the signal IC 23 is possible without having to change the assembly process of the entire module or the entire electronic arrangement.
  • the contacting layer 13, 14 can be adapted in its free area 14 in comparison to the power chips 21, 22 to both thicker and thinner IC chips 23.
  • the upper contact layer 13, 14 thinner in the embossed area, ie in the free area 14, before sintering onto the upper carrier 11, that is to say, for example, with a thickness of approximately 50 to 250 ⁇ m.

Abstract

The invention relates to a sandwich-type electronic assembly which comprises two supports (10, 11) every support having one strip conductor layer (8, 13, 14), the top strip conductor layer (13, 14) extending in different planes.

Description

Elektronische Anordnung Electronic arrangement
Stand der TechnikState of the art
Die Erfindung geht aus von einem elektronischen Modul nach der Gattung des Hauptanspruchs. Aus der WO 98/15005 ist bereits ein Power-Modul bekannt, bei dem Leistungstransistoren zwischen zwei DBC-Substraten (direct bonded copper) mit strukturierten CU-Schichten als Verdrahtungsebene montiert werden, wobei die Anbindung der Chipvorder- und -rückseiten an die CU-Bahnen über eine Lotschicht erfolgt. Mit Hilfe von optional verwendbaren Abstandskugeln kann bei Bedarf sichergestellt werden, dass die Lotschicht an den strukturierten Metallbahnen der Chip-Vorderseiten eine ausreichende Dicke während und nach dem Reflow-Lötprozess beibehält. Ein Merk- mal der DBC-Substrate ist dabei, dass die CU-Schichten aufgrund ihrer Dicke - typischerweise ca. 300 μ - nicht beliebig fein strukturiert werden können. Die Dicke der CU- Schicht ist dabei notwendig, um die Verlustwärme der Powerchips ausreichend abführen zu können und um die hohen Ströme im Modul möglichst widerstandsarm leiten zu können. HierbeiThe invention relates to an electronic module according to the preamble of the main claim. A power module is already known from WO 98/15005, in which power transistors are mounted between two DBC substrates (direct bonded copper) with structured CU layers as the wiring level, the connection of the chip front and back sides to the CU Paths are made over a solder layer. With the help of optionally usable spacer balls, it can be ensured, if necessary, that the solder layer on the structured metal tracks of the chip front sides maintains a sufficient thickness during and after the reflow soldering process. A feature of the DBC substrates is that the CU layers cannot be structured as finely as desired due to their thickness - typically approx. 300 μ. The thickness of the CU layer is necessary in order to be able to dissipate the lost heat of the power chips sufficiently and to be able to conduct the high currents in the module with as little resistance as possible. in this connection
•verhält es sich so, dass der Minimalabstand zwischen zwei CU-Bereichen nicht wesentlich geringer sein kann als die Dicke der CU-Schicht..• it is the case that the minimum distance between two CU areas cannot be significantly less than the thickness of the CU layer.
Vorteile der Erfindung Ein wesentlicher Nachteil des aus dem Stand der Technik bekannten Aufbaus ist, dass er zunächst nur für die Montage von vorzugsweise grob strukturierten Vorderseitenanschlüssen von Powerchips und einheitlichen Chipdicken geeignet ist. Daraus resultiert, dass eine Kombination von Leistungsbauelementen (Powerchips) und von Signalbauelementen (Signal - IC's) nicht möglich ist, wenn die Signal-IC s viele fein strukturierte Vorderseitenanschlüsse aufweisen und wenn die Signal-IC s Chipdicken aufweisen, die wesentlich von den Chipdicken der Powerchips abweichen. Die erfindungsgemäße elektronische Anordnung mit den Merkmalen des Hauptanspruchs hat daher gegenüber dem Stand der Technik den Vorteil, dass eine sehr einfache und kostengünstige Erweiterung des Modu-' laufbaus dadurch erreicht wird, dass die Kombination von Leistungschips und Powerchips ermöglicht wird.Advantages of the invention A major disadvantage of the structure known from the prior art is that it is initially only suitable for the assembly of preferably roughly structured front connections of power chips and uniform chip thicknesses. The result of this is that a combination of power components (power chips) and signal components (signal ICs) is not possible if the signal IC s have many finely structured front connections and if the signal IC s have chip thicknesses that differ significantly from the chip thicknesses of the Powerchips differ. The electronic arrangement according to the invention with the features of the main claim therefore has the advantage over the prior art that a very simple and inexpensive expansion of the module structure is achieved in that the combination of power chips and power chips is made possible.
Durch die in den Unteransprüchen aufgeführten Maßnahmen sind weitere vorteilhafte Weiterbildungen und Verbesserungen der im Hauptanspruch angegebenen elektronischen Anordnung mög- lieh.The measures listed in the subclaims lend further advantageous developments and improvements to the electronic arrangement specified in the main claim.
Zeichnungdrawing
Ein Ausführungsbeispiel der Erfindung ist in der Zeichnung dargestellt und in der nachfolgenden Beschreibung näher erläutert. Es zeigenAn embodiment of the invention is shown in the drawing and explained in more detail in the following description. Show it
Figur 1 ein erstes Ausführungsbeispiel der elektronischen Anordnung,FIG. 1 shows a first exemplary embodiment of the electronic arrangement,
Figur 2 ein zweites Ausführungsbeispiel der elektronischen Anordnung,• 2 shows a second embodiment of the electronic device, •
Figur 3 ein oberes DBC-Substrat vor der Stanz- und Prägebearbeitung undFigure 3 shows an upper DBC substrate before punching and embossing and
Figur 4 ein oberes DBC-Substrat nach der Stanz- und Prägebearbeitung.Figure 4 shows an upper DBC substrate after stamping and embossing.
Beschreibung der Ausführungsbeispiele In Figur 1 ist ein Modulaufbau einer erfindungsgemäßen elektronischen Anordnung für eine erste Ausführungsform der Erfindung dargestellt. Die elektronische Anordnung umfasst einen ersten Träger 10 und einen zweiten Träger 11. Zwischen den Trägern 10, 11 befinden sich in der Regel eine Mehrzahl von elektronischen Schaltkreisen in Form von Halbleiterchips, die in der Figur 1 mit den Bezugszeichen 21, 22 und 23 bezeichnet sind. Erfindungsgemäß ist es sowohl möglich weniger als drei Halbleiterchips 21, 22, 23 zwischen den Trägern 10, 11 vorzusehen als auch eine größere Anzahl solcher Halbleiterchips 21, 22, 23 vorzusehen. In Figur 1 ist es nun so, dass mit den Bezugszeichen 21 und 22 ein erster und zweiter Leistungshalbleiterchip bezeichnet ist. Die Leistungshalbleiterchips 21, 22 zeichnen sich dadurch aus, dass insbesondere eine große Wärmemenge, die ggf. in dem Lei- stungshalbleiterchip 21, 22 dissipiert wird, über thermische Kopplungen abzuführen ist. Dem gegenüber ist mit dem Bezugs- zeichen 23 in Figur 1 ein Signal-IC bezeichnet, der zur SignalVerarbeitung vorgesehen ist. Bei dem Signal-IC 23 sind die Anforderungen an die Wärmeabfuhr in der Regel wesentlich geringer ausgeprägt als bei den Leistungshalbleiterchips 21, 22. In Figur 1 ist der Signal-IC 23 derart vorgesehen, dass das Halbleitersubstrat des Signal-ICs 23 eine größere Dicke aufweist als das Halbleitersubstrat der beiden Leistungs- halbleiterchips 21, 22.Description of the embodiments FIG. 1 shows a module structure of an electronic arrangement according to the invention for a first embodiment of the invention. The electronic arrangement comprises a first carrier 10 and a second carrier 11. Between the carriers 10, 11 there are generally a plurality of electronic circuits in the form of semiconductor chips, which are identified in FIG. 1 by the reference symbols 21, 22 and 23 , According to the invention, it is both possible to provide fewer than three semiconductor chips 21, 22, 23 between the carriers 10, 11 and also to provide a larger number of such semiconductor chips 21, 22, 23. In FIG. 1 it is now the case that reference symbols 21 and 22 denote a first and second power semiconductor chip. The power semiconductor chips 21, 22 are characterized in that, in particular, a large amount of heat, which may be dissipated in the power semiconductor chip 21, 22, is to be dissipated via thermal couplings. In contrast, the reference symbol 23 in FIG. 1 denotes a signal IC which is provided for signal processing. With the signal IC 23, the requirements for heat dissipation are generally much less pronounced than with the power semiconductor chips 21, 22. In FIG. 1, the signal IC 23 is provided such that the semiconductor substrate of the signal IC 23 has a greater thickness than the semiconductor substrate of the two power semiconductor chips 21, 22.
In Figur 2 ist ebenfalls die erfindungsgemäße elektronische Anordnung dargestellt, wobei wiederum der erste Träger 10, der zweite Träger 11 und die Halbleiterchips 21, 22, 23 vor- gesehen sind. In Figur 2 ist es jedoch im Gegensatz zu Figur 1 so, dass die Dicke des Signal-IC s 23 kleiner vorgesehen ist als die Dicke der Leistungshalbleiterchips 21, 22.The electronic arrangement according to the invention is also shown in FIG. 2, again the first carrier 10, the second carrier 11 and the semiconductor chips 21, 22, 23 being provided. In contrast to FIG. 1, however, in FIG. 2 the thickness of the signal IC 23 is smaller than the thickness of the power semiconductor chips 21, 22.
Im folgenden werden sowohl die Figur 1 als auch die Figur 2 gemeinsam beschrieben, wobei jedoch auf die Unterschiede eingegangen wird. Kern der vorliegenden Erfindung ist die Verwendung eines speziellen zweiten Trägers 11 in der Form, dass der zweite Träger 11 in Teilbereichen eine feinstrukturierte und im Abstand zum unteren ersten Träger 10 anpassbare Kontaktschicht aufweist, so dass ohne Änderung des Modulmontage-Verfahrens gegenüber dem Stand der Technik eine ko- stengünstige Integration von Signal-IC Chips in das Gesamtmodul bzw. in die gesamte elektronische Anordnung ermöglicht wird.In the following, both FIG. 1 and FIG. 2 are described together, but the differences are discussed. The essence of the present invention is the use of a special second carrier 11 in the form that the second carrier 11 has a finely structured contact layer in parts that can be adjusted at a distance from the lower first carrier 10, so that without changing the module assembly method compared to the prior art, cost-effective integration of signal IC chips into the overall module or into the entire electronic arrangement is made possible.
Der erste Träger 10, der im folgenden auch als unterer Trä- ger 10 bezeichnet wird, umfasst als Trägersubstanz insbesondere ein Keramikmaterial, auf welchem eine untere Kontak ie- rungsschicht 8 in Teilbereichen - d.h. die untere Kontaktie- rungsschicht 8 ist strukturierbar vorgesehen - aufgebracht ist. Die untere Kontaktierungsschicht 8 ist erfindungsgemäß insbesondere als Kupferschicht vorgesehen, welche im folgenden auch als untere CU-Schicht 8 bezeichnet wird. Der untere Träger 10 samt der auf ihm befindlichen unteren Kontaktierungsschicht 8 ist erf'indungsgemäß insbesondere als DBC- Substrat vorgesehen und wird im folgenden daher auch als un- teres DBC-Substrat 10 bezeichnet. Auf der unteren CU-SchichtThe first carrier 10, which is also referred to below as the lower carrier 10, comprises, as carrier substance, in particular a ceramic material on which a lower contact layer 8 is applied in partial areas - ie the lower contact layer 8 is provided in a structurable manner , According to the invention, the lower contacting layer 8 is provided in particular as a copper layer, which is also referred to below as the lower CU layer 8. The lower support 10 together with the lower contacting layer situated on it is satisfiable indungsgemäß 8 'are provided in particular as a DBC substrate and is also referred to below as un- therefore teres DBC substrate 10th On the lower CU layer
8 des unteren Trägers 10 ist sowohl in der Figur 1 als auch in der Figur 2 eine elektrisch und thermisch leitende Verbindung jeweils einzeln zu den Halbleiterchips 21, 22, 23 in Form von unteren Lotschichten 7 vorgesehen.8 of the lower carrier 10, both in FIG. 1 and in FIG. 2, an electrically and thermally conductive connection is provided individually to the semiconductor chips 21, 22, 23 in the form of lower solder layers 7.
Die Halbleiterchips 21, 22, 23 weisen ebenfalls Anschlüsse an ihrer Vorderseite bzw. an ihrer Oberseite auf, welche mittels des zweiten Trägers bzw. des oberen Trägers 11 versorgt werden. Der obere Träger 11 ist erfindungsgemäß insbe- sondere ebenfalls als DBC-Substrat vorgesehen und wird daher auch als oberes DBC-Substrat 11 bezeichnet. Der obere Träger 11 weist in Teilbereichen Ausnehmungen 12 auf. Weiterhin ist auch am oberen Träger 11 eine Kontaktierungsschicht vorgesehen, welche in den Bereichen, wo der obere Träger keine Aus- nehmung 12 aufweist das Bezugszeichen 13 trägt und welche in den Bereichen, wo der obere Träger 11 Ausnehmungen 12 aufweist, mit dem Bezugszeichen 14 versehen ist. Die obere Kon- taktierungsschicht 13, 14, welche erfindungsgemäß insbesondere ebenfalls als CU-Schicht 13, 14 vorgesehen ist, dient der Kontaktierung mit der Oberseite der Halbleiterchips 21, 22, 23. Da die Kontaktierungsschicht in ihren Bereichen 14 an dem oberen Träger 11 nicht anliegt, ist es möglich, dass die „Freie Kontaktierungsschicht" 14 in einer Richtung, die rechtwinklig zur Ebene' des oberen Trägers 11 steht, in Grenzen flexibel ist. So ist es möglich, dass die freie Kontaktierungsschicht 14 in Figur 1 nach oben, d.h. in Richtung des zweiten Trägers 11 hin, biegbar bzw. plastisch verformbar ist, so dass die obere Kontaktierungsschicht 13, 14 im ganzen sowohl eine Kontaktierung eines eine geringere Dicke aufweisenden Leistungshalbleiterchips 21, 22 als auch die elektrische Kontaktierung eines eine größere Dicke auf ei - senden Signal-IC Chips 23 erfüllen kann, obwohl der Leistungshalbleiterchip und der Signal-IC Chip von ihrer Unterseite her, d.h. von dem ersten Träger 10, der Kontaktierungsschicht 8 und der Lötschicht 7 her auf gleichem Niveau angeordnet sind. In Figur 2 ist der umgekehrte Fall darge- stellt, nämlich bei dem der Signal-IC Chip 23 eine geringere Dicke aufweist als die Leistungshalbleiterchips 21, 22. Bei dieser zweiten Ausführungsform der erfindungsgemäßen elektronischen Anordnung wird daher die obere Kontaktierungsschicht 13, 14 in ihrem freien Bereich 14 nach unten hin plastisch verformt, so dass wiederum durch die obere Kontaktierungsschicht 13, 14 im ganzen sowohl eine Kontaktierung ■ der Leistungshalbleiterchips 21, 22 als auch des Signal-IC Chips 23 gewährleistet ist. Die obere Kontaktierungsschicht 13, 14 ist daher erfindungsgemäß in ihrem keine Ausnehmung 12 aufweisenden Bereich 13 in einer ersten Ebene angeordnet und in ihrem „freien Bereich" 14 zumindest teilweise in einer von der ersten Ebene unterschiedlichen zweiten Ebene vorgesehen.The semiconductor chips 21, 22, 23 also have connections on their front side or on their top side, which are supplied by means of the second carrier or the upper carrier 11. According to the invention, the upper carrier 11 is in particular also provided as a DBC substrate and is therefore also referred to as an upper DBC substrate 11. The upper support 11 has recesses 12 in partial areas. Furthermore, a contacting layer is also provided on the upper carrier 11, which bears the reference symbol 13 in the regions where the upper carrier has no recess 12 and which has the reference symbol 14 in the regions where the upper carrier 11 has recesses 12 is. The upper con- Clocking layer 13, 14, which according to the invention is also in particular provided as a CU layer 13, 14, is used for contacting the top of the semiconductor chips 21, 22, 23. Since the contacting layer in its regions 14 is not in contact with the upper carrier 11, it is it is possible that the “free contacting layer” 14 is flexible within limits in a direction that is perpendicular to the plane ′ of the upper carrier 11. It is thus possible for the free contacting layer 14 in FIG. 1 to be upward, ie in the direction of the second Carrier 11 out, is bendable or plastically deformable, so that the upper contact layer 13, 14 as a whole both a contact of a smaller thickness power semiconductor chips 21, 22 and the electrical contact of a larger thickness on egg - signal IC chips 23 can meet, although the power semiconductor chip and the signal IC chip from their underside, ie from the first carrier 10, the Kon Taktierungsschicht 8 and the solder layer 7 ago are arranged at the same level. The reverse case is shown in FIG. 2, namely in which the signal IC chip 23 has a smaller thickness than the power semiconductor chips 21, 22. In this second embodiment of the electronic arrangement according to the invention, the upper contact layer 13, 14 is therefore free , so that again by the upper contacting layer 13, 14 throughout both contacting ■ the power semiconductor chips 21, 22 as the signal IC chips is ensured 23 plastically deformed area 14 downwardly also. The upper contacting layer 13, 14 is therefore arranged according to the invention in its area 13 not having a recess 12 in a first level and in its “free area” 14 at least partially in a second level that is different from the first level.
Erfindungsgemäß ist es bei beiden Ausführungen so, dass zwischen der oberen Kontaktierungsschicht 13, 14 und den Halbleiterchips eine Lötschicht 15 vorgesehen ist, welche nicht mittels eines Bezugszeichens näher bezeichnete Abstandskugeln aufweist.According to the invention, it is the case in both embodiments that a solder layer 15 is provided between the upper contacting layer 13, 14 and the semiconductor chips, which is not has spacer balls designated by means of a reference number.
In Figur 3 ist der obere Träger 11 mit der oberen Kontakt ie- rungsschicht 13 dargestellt . Im mittleren Bereich des oberen Trägers 11 ist mittels eines punktierten Rechtecks die Ausnehmung 12 dargestellt. In Figur 3 sind wiederum die Bereiche 13 der oberen Kontaktierungsschicht 13, 14 erkennbar, die in Bereichen des oberen Trägers 11 vorgesehen sind, wo die Ausnehmung 12 nicht vorgesehen ist. Weiterhin sind auch die Bereiche 14 der oberen Kontaktierungsschicht 13, 14 erkennbar, welche im Bereich der Ausnehrnung 12 vorgesehen sind. Erfindungsgemäß ist es vorgesehen, dass die freien Bereiche 14 der oberen Kontaktierungsschicht 13, 14, bei- spielsweise mittels eines Stanzwerkzeugs, im Bereich derFIG. 3 shows the upper carrier 11 with the upper contact layer 13. The recess 12 is shown in the central region of the upper carrier 11 by means of a dotted rectangle. In FIG. 3, the regions 13 of the upper contacting layer 13, 14 are again visible, which are provided in regions of the upper carrier 11 where the recess 12 is not provided. Furthermore, the regions 14 of the upper contacting layer 13, 14, which are provided in the region of the recess 12, can also be seen. According to the invention, it is provided that the free areas 14 of the upper contacting layer 13, 14, for example by means of a stamping tool, in the area of the
Ausnehmung 12 weiter und feiner strukturiert werden als dies die Strukturierung der oberen Kontaktierungsschicht 13, 14 im Bereich des oberen Trägers 11 an Stellen wo die Ausnehmung 12 nicht vorgesehen ist vorsieht.Recess 12 are structured wider and finer than the structuring of the upper contact layer 13, 14 in the area of the upper carrier 11 at locations where the recess 12 is not provided.
Eine solche zusätzliche und weitergehende Ξtrukturierung ist in Figur 4 dargestellt, wo der obere Träger 11 mit der oberen Strukturierungsschicht 13, 14 und der Ausnehmung 12 dargestellt ist, wobei jedoch in Figur 4 im Unterschied zu Fi- gur 3 die weitergehende Strukturierung der freien BereicheSuch an additional and more extensive structuring is shown in FIG. 4, where the upper support 11 is shown with the upper structuring layer 13, 14 and the recess 12, but in FIG. 4, in contrast to FIG. 3, the more extensive structuring of the free areas
14 der oberen Kontaktierungsschicht 13 , 14 durchgeführt wurde . Erkennbar ist, dass ausgehend von dem noch in Figur 3 sichtbaren und mit dem Bezugszeichen M angedeuteten unstrukturierten mittleren Bereich der freien oberen Kontaktie- rungsschicht 14 eine feine Strukturierung des freien Bereichs 14 der oberen Kontaktierungsschicht 13, 14 erreicht wurde, insbesondere in Form von feinst ukturierten Anschlüssen, die insbesondere für Signal-IC Chips 23 gedacht sind.14 of the upper contact layer 13, 14 was carried out. It can be seen that, starting from the unstructured central region of the free upper contact layer 14 which is still visible in FIG. 3 and is indicated by the reference symbol M, fine structuring of the free region 14 of the upper contact layer 13, 14 has been achieved, in particular in the form of finely structured Connections, which are intended in particular for signal IC chips 23.
Der Strukturierungsschritt der den Übergang von Figur 3 zu Figur 4 markiert, ist erfindungsgemäß insbesondere als Stanz- und Prägevorgang vorgesehen. Andere mechanische und/oder sonstige Ξtrukturierungsverfahren sind jedoch erfindungsgemäß ebenfalls vorgesehen. Beim erfindungsgemäßen Stanz- und Prägeverfahren ist es so, dass sowohl die geometrische Strukturierung der freien Bereiche 14 der oberen Kontaktierungsschicht durchgeführt wird, d.h. Strukturierung entlang der Ebene des oberen Trägers 11, als auch die Strukturierung in hierzu ortogonaler Richtung d.h. das Vorsehen von Auslenkungen der freien Bereiche 14 der oberen Kontaktierungsschicht 13, 14 zur Kompensation von unterschiedli - chen Chipdicken der im Bereich der freien Bereiche 14 der oberen Kontaktierungsschicht vorgesehenen Halbleiterchips .The structuring step which marks the transition from FIG. 3 to FIG. 4 is provided according to the invention in particular as a stamping and embossing process. Other mechanical and / or other structuring methods are however also provided according to the invention. In the stamping and embossing method according to the invention, both the geometric structuring of the free areas 14 of the upper contacting layer is carried out, ie structuring along the plane of the upper carrier 11, and the structuring in the orthogonal direction, ie the provision of deflections of the free ones Areas 14 of the upper contact layer 13, 14 for compensating for different chip thicknesses of the semiconductor chips provided in the area of the free areas 14 of the upper contact layer.
Erfindungsgemäß ist es daher vorteilhaft möglich, Chips 21, 22, 23 mit unterschiedlichen Dicken in einer einzigen erfin- dungsgemäßen elektronischen Anordnung in Sandwich-Bauweise vorzunehmen. Weiterhin ist es daher erfindungsgemäß vorteilhaft möglich, die Integration von Signal-IC s mit fein strukturierten Anschlüssen und mit einer großen Anzahl von Anschlüssen in die erfindungsgemäße elektronische Anordnung, welche insbesondere als Powermodul vorgesehen ist, zu ermöglichen. Hierfür sind erfindungsgemäß in vorteilhafter Weise keine zusätzlichen Teile notwendig. Weiterhin ergibt sich erfindungsgemäß der Vorteil, ein unverändertes Modulmontageverfahren zu verwenden, d.h. es ist möglich, die Montage al- 1er Chips in einem Reflow-Lötvorgang vorzunehmen. Die erfindungsgemäße elektronische Anordnung ist darüber hinaus kostengünstig möglich weil der geringe Zusatzaufwand für die Stanz- und Prägebearbeitung des noch unbestückten DBC- Substrats in einem Werkzeug bereits im Substratmehrfachnut- zen möglich ist. Der Begriff Substratmehrfachnutzen bedeutet dabei den Verbund von mehreren Einzelsubstraten zur simultanen Bearbeitung. Erfindungsgemäß ist es darüber hinaus weiterhin möglich, die feine Strukturierung der freien Bereiche 14 der oberen Kontaktierungsschicht 13, 14 im Bereich der externen Anschlüsse der erfindungsgemäßen elektronischen Anordnung zu verwenden, um eine deutlich erhöhte Anzahl von Außenanschlüssen des Moduls zu ermöglichen. Weiterhin ist von Vorteil, dass erfindungsgemäß sowohl die Signal-ICs 23 als auch die Leistungschips 21, 22 in derselben Ebene auf dem unteren Träger 10 bzw. dessen Kontaktierungsschicht 8 montierbar sind. Dadurch kann das vollständige Leistungsmo- dul bzw. die vollständig elektronische Anordnung weiterhin auf der Vorder- und der Rückseite flächig, d.h. thermisch optimal, montiert werden.According to the invention, it is therefore advantageously possible to carry out chips 21, 22, 23 with different thicknesses in a single electronic arrangement according to the invention in a sandwich construction. Furthermore, it is therefore advantageously possible according to the invention to enable the integration of signal ICs with finely structured connections and with a large number of connections into the electronic arrangement according to the invention, which is provided in particular as a power module. According to the invention, no additional parts are advantageously necessary for this. Furthermore, according to the invention there is the advantage of using an unchanged module assembly method, ie it is possible to assemble all of the chips in a reflow soldering process. The electronic arrangement according to the invention is moreover possible in a cost-effective manner because the small additional expenditure for punching and embossing processing of the still unpopulated DBC substrate in one tool is already possible in multiple substrate uses. The term substrate multiple use means the combination of several individual substrates for simultaneous processing. According to the invention, it is furthermore possible to use the fine structuring of the free areas 14 of the upper contacting layer 13, 14 in the area of the external connections of the electronic arrangement according to the invention in order to enable a significantly increased number of external connections of the module. Still is It is advantageous that, according to the invention, both the signal ICs 23 and the power chips 21, 22 can be mounted in the same plane on the lower carrier 10 or its contact layer 8. As a result, the complete power module or the completely electronic arrangement can continue to be mounted flat on the front and the back, ie thermally optimal.
Beim Stand der Technik sind die Signal-ICs auf der äußeren Oberfläche des Moduls montiert und verhindern so eine beid- seitige flächige Kühlung des Moduls .In the prior art, the signal ICs are mounted on the outer surface of the module and thus prevent cooling of the module on both sides.
Der obere Träger 11 der erfindungsgemäßen elektronischen Anordnung weist zusammen mit seiner Kontaktierungsschicht 13, 14 erfindungsgemäß die folgenden Eigenschaften auf:The upper carrier 11 of the electronic arrangement according to the invention, together with its contacting layer 13, 14, has the following properties according to the invention:
Im Bereich der Powerchips 21, 22 bleibt der Aufbau der DBC- Schicht 11 gegenüber einem oberen Träger 11 ohne Ausnehmung 12 unverändert . In den Bereichen, in denen mit Hilfe der freien Bereiche 14 der oberen Kontaktierungsschicht 13, 14 Signal-IC s 23 angeschlossen werden sollen, ist der Keramikbereich des Substrats, d.h. des oberen Trägers 11, ausgespart - d.h. es ist die Ausnehmung 12 bzw. sind die Ausnehmungen 12 vorgesehen - und die ursprünglich typischerweise 300 μm dicke Kontaktie- rungsschicht 13, 14 ist durch ein Stanz- und ein Prägeverfahren so verändert, dass eine fein strukturierte und in der Höhe, d.h. in zur Ebene des oberen Trägers 11 ortogonaler Richtung, an die IC-Dicke des Signal-ICs 23 angepasste Kontaktierung des Signal-ICs 23 möglich ist, ohne den Montage- prozess des gesamten Moduls bzw. der gesamten elektronischen Anordnung verändern zu müssen. Dabei kann die Kontaktierungsschicht 13, 14 in ihrem freien Bereich 14 im Vergleich zu den Leistungschips 21, 22 sowohl an dickere als auch an dünnere IC-Chips 23 angepasst werden. Um den Stanz- und Prrä- gevorgang der oberen Kontaktierungsschicht im IC-In the area of the power chips 21, 22, the structure of the DBC layer 11 remains unchanged compared to an upper carrier 11 without a recess 12. In the areas in which signal ICs 23 are to be connected using the free areas 14 of the upper contacting layer 13, 14, the ceramic area of the substrate, i. of the upper beam 11, recessed - i.e. the recess 12 or the recesses 12 are provided - and the originally typically 300 μm thick contact layer 13, 14 is changed by a stamping and embossing process such that a finely structured and in height, i.e. in the direction orthogonal to the plane of the upper carrier 11, contacting of the signal IC 23 adapted to the IC thickness of the signal IC 23 is possible without having to change the assembly process of the entire module or the entire electronic arrangement. The contacting layer 13, 14 can be adapted in its free area 14 in comparison to the power chips 21, 22 to both thicker and thinner IC chips 23. The stamping and embossing process of the upper contact layer in the IC
Kontaktierungsbereich der Ausnehmung 12 möglichst einfach durchführen zu können, kann es optional erfindungsgemäß hilfreich sein, die obere Kontaktierungsschicht 13, 14 im Prägebereich, d.h. im freien Bereich 14, bereits vor dem Aufsintern auf den oberen Träger 11 dünner, d.h. beispielsweise mit einer Dicke von etwa 50 bis 250 μm, auszugestalten. To be able to carry out the contacting area of the recess 12 as simply as possible, it can optionally be done according to the invention be helpful to make the upper contact layer 13, 14 thinner in the embossed area, ie in the free area 14, before sintering onto the upper carrier 11, that is to say, for example, with a thickness of approximately 50 to 250 μm.

Claims

Ansprüche Expectations
1. Elektronische Anordnung in Sandwich-Bauweise mit einem ersten Träger (10) und einem zum ersten Träger (10) im wesentlichen parallel angeordneten zweiten Träger (11) , wobei der erste Träger (10) auf der zum zweiten Träger1. Electronic arrangement in sandwich construction with a first carrier (10) and a second carrier (11) arranged essentially parallel to the first carrier (10), the first carrier (10) being on the second carrier
(11) hinweisenden Seite eine erste Leiterbahnschicht (8) umfasst, wobei der zweite Träger (11) auf der zum ersten Träger (10) hinweisenden Seite eine zweite Leiterbahnschicht (13, 14) umfasst, dadurch gekennzeichnet, dass die zweite Leiterbahnschicht (13, 14) teilweise in einer ersten Ebene vorgesehen ist und das die zweite Leiterbahnschicht (13, 14) in einem Teilbereich (14) zumindest teilweise in einer zweiten Ebene vorgesehen ist.(11) facing side comprises a first conductor track layer (8), the second carrier (11) on the side facing the first carrier (10) comprising a second conductor track layer (13, 14), characterized in that the second conductor track layer (13, 14) is partially provided on a first level and that the second interconnect layer (13, 14) is at least partially provided in a partial area (14) on a second level.
2. Elektronische Anordnung nach Anspruch 1, dadurch gekennzeichnet, dass, der zweite Träger (11) in dem Teilbereich2. Electronic arrangement according to claim 1, characterized in that, the second carrier (11) in the partial area
(12) ausgespart vorgesehen ist.(12) is provided recessed.
3. Elektronische Anordnung nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass in dem Teilbereich (12) zwischen den3. Electronic arrangement according to claim 1 or 2, characterized in that in the partial area (12) between the
Trägern (10, 11) wenigstens ein Signal-IC (23) vorgesehen ist.Carriers (10, 11) at least one signal IC (23) is provided.
4. Elektronische Anordnung nach einem der vorhergehenden An- sprüche, dadurch gekennzeichnet, dass außerhalb des Teilbereichs (12) zwischen den Trägern (10, 11) wenigstens ein Leistungshalbleiterchip (21, 22) vorgesehen ist. Elektronische Anordnung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass der Signal-IC (23) und der Leistungshalbleiterchip (21, 22) eine unterschiedliche Dicke aufweisen. 4. Electronic arrangement according to one of the preceding claims, characterized in that at least one power semiconductor chip (21, 22) is provided outside the sub-area (12) between the carriers (10, 11). Electronic arrangement according to one of the preceding claims, characterized in that the signal IC (23) and the power semiconductor chip (21, 22) have a different thickness.
EP02779160A 2001-11-17 2002-10-15 Electronic assembly Withdrawn EP1449252A2 (en)

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DE102004031592A1 (en) * 2004-06-30 2006-02-09 Robert Bosch Gmbh Electronic module arrangement and corresponding manufacturing method
US8018056B2 (en) 2005-12-21 2011-09-13 International Rectifier Corporation Package for high power density devices
JP5414644B2 (en) 2010-09-29 2014-02-12 三菱電機株式会社 Semiconductor device
DE102022207848A1 (en) 2022-07-29 2023-11-16 Vitesco Technologies Germany Gmbh Contacting element for power semiconductor modules, power semiconductor module and inverter with a contacting element

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DE3201296C2 (en) * 1982-01-18 1986-06-12 Institut elektrodinamiki Akademii Nauk Ukrainskoj SSR, Kiev Transistor arrangement
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