EP1449110A2

EP1449110A2 - Method for determination of a separation from processor units to at least one reference position in a processor arrangement and processor arrangement

Info

Publication number: EP1449110A2
Application number: EP02798255A
Authority: EP
Inventors: Anton Georg Buchmeier; Stefan Jung; Thomas Sturm; Annelie STÖHR
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2001-11-30
Filing date: 2002-11-28
Publication date: 2004-08-25
Also published as: WO2003048953A2; WO2003048953A3; US20050078115A1

Abstract

A processor arrangement comprises a number of processor units. Each processor unit is coupled to at least one adjacent processor unit by means of a bi-directional communication interface. Messages are exchanged between adjacent processor units for the determination of the separation of a processor unit in the processor arrangement from a reference position. Each message contains separation information, giving the separation of the processor unit receiving the message from the reference position or the separation of the processor unit sending the message from the reference position, where each processor unit is embodied such as to be able to determine or store the separation thereof from the reference position from the separation information in a received message.

Description

description

Method for determining a distance from processor units to at least one reference position in a processor arrangement and processor arrangement

The invention relates to a method for determining a / distance from processor units to at least one reference position in a processor arrangement and a processor arrangement.

If a processor arrangement with a multiplicity of processors has been produced in such a way that the local position of the individual processors within the processor arrangement is not known, the individual processors cannot be addressed individually.

Before using the processor arrangement, however, the processors must be organized so that the local position of the individual processors within the processor arrangement can be determined and so that the processors within the processor arrangement can be addressed individually.

The organization should be feasible even in the event of errors occurring during the production of the processor arrangement or in the event of later failures of one or more processors or one or more connections between the processors.

An example of such a processor arrangement can be seen in a pixel arrangement, with each pixel of the pixel arrangement being assigned a processor which can control the pixel. The pixel can be configured as an imaging element or also as a sensor element, so that the pixel arrangement can be configured as a display unit or as a sensor field. In a pixel arrangement with a large number of pixels, in particular with a large-area dot matrix display unit or a large-area sensor field, considerable problems often occur.

Such a pixel arrangement has, for example, in the case that it is set up as a so-called "electronic newspaper", several million pixels per page, that is, pixels.

In the following, a pixel arrangement is understood to mean a homogeneous pixel matrix which is controlled or addressed from the edges thereof. Such a display matrix or a sensor matrix, that is to say generally such a matrix

Pixel arrangement, for example, has active non-linear selection devices such as thin film transistors (TFTs) in liquid crystal display units (Liquid Crystal Displays, LCDs), which are limited in size or dimension by the properties of the thin film transistors and by the parasitic resistances of the data lines, which are used to transmit the signals from and to the individual pixels.

In practice, the thin film transistors must have a current ratio of 10 ⁵ to 10 ^ between the current which flows when switched on (I ₀ n) ^and the current which flows when switched off (I ₀ ff). High electrical resistances of the very thin and very long ones

Data lines in such a pixel arrangement and a low current when the device is switched on limit the access time to individual rows or columns of the pixels in the pixel arrangement which are usually arranged in a matrix. This leads to a very slow electrical charging of the individual pixel elements. Furthermore, an excessively high current when the pixel arrangement is switched off when the matrix-shaped pixel arrangement is scanned row by row or column by column leads to a charge loss of electrical charges in the pixel capacitors, if these are not currently selected. For this reason, a control cycle, that is to say a time interval between which the individual pixel elements in the pixel arrangement are controlled, must not become too long.

The problems mentioned above are explained for example in [1] and in [2] in connection with the design of liquid crystal display units or electrophoretic display units with thin film transistors as drive transistors.

Furthermore, the manufacturing process of liquid crystal flat screens is extremely complex and prone to failure.

The problems described above are exacerbated in the case of large-area and flexible displays, that is to say in the case of large-area and flexible display units such as, for example, an electronic newspaper, in particular in the event that cost-effective production processes, such as printing processes for producing printable transistors, are used for the switching elements, for example in the field of polymer electronics. Such transistors typically have a ratio of I _on / I ₀ ff of 10 ^ to 10 ^. In any case, the transistors that are implemented in polymer electronics are even worse in their properties than conventional thin-film transistors based on silicon. However, such polymer electronics transistors are only suitable for display units with a few hundred picture lines or picture columns. A particular problem can be seen in the fact that the yield in the production of a pixel arrangement is lower due to the very large area. This is due to the higher probability of errors in such a manufacturing process. In other words, the number of defective pixels or image areas or defective sensor points, that is to say sensor elements, increases with the area of the pixel arrangement becoming larger.

When handling a very thin, flexible and possibly large-area display unit, the likelihood of new defects or damage occurring during handling is high. With conventional addressing of a matrix-shaped pixel arrangement, a defect in the matrix would immediately lead to a row error or column error or even an entire area of the pixel arrangement would fail.

The problems described above have been attempted in accordance with the prior art by improving the properties of the selection transistors, that is to say in particular the ratio of I _on to I _Q ff, and by means of improved production processes. Protection against mechanical stress on a flat screen was attempted with an appropriate housing or with special packaging.

The invention is based on the problem of specifying a method for determining a distance from processors to at least one reference position in a processor arrangement and a processor arrangement in which or at least some of the above-mentioned problems of the prior art are reduced , The problem is solved by the method and by the pixel arrangement with the features according to the independent patent claims.

In a method of determining a distance from

Processor units for at least one reference position in a processor arrangement with a plurality of processor units, each processor unit is coupled to at least one processor unit adjacent to it via a bidirectional communication interface. The processor units exchange electronic messages with one another, in particular between processor units which are immediately adjacent to one another. According to the method, a first message is generated by a first processor unit, which is located at the at least one reference position. The first message contains first distance information, which contains the distance of the first processor unit or the distance of a second processor unit receiving the first message from the reference position. The first message is transmitted from the first processor unit to the second processor unit. Depending on the first distance information, the distance of the second processor unit from the reference position is determined or stored. A second message is generated by the second processor unit, which contains a second distance information which contains the distance of the second processor unit or the distance of a third processor unit receiving the second message from the reference position. The second message is transmitted from the second processor unit to the third processor unit. The respective messages are preferably always transmitted via the bidirectional communication interface of the respective processor units which are immediately adjacent to one another. Depending on the second distance information, the distance of the third processor unit from the reference position is determined or stored. The storage is preferably carried out in each case locally in a local memory which is assigned to a respective processor unit. The method steps described above are carried out iteratively for all processor units in the pixel arrangement.

The reference position can in principle be arbitrary, preferably the reference position is a position at which a portal processor described below is located, which controls the processor units in the processor arrangement and initiates communication from outside the processor arrangement. The reference position can also be a position within the processor arrangement, in which case a processor unit is preferably arranged at the reference position and is assigned to it. In this case, the

Reference position on the edge, i.e. on the top or bottom row or the left or right column in the event that the processor units in the processor arrangement are arranged in a matrix in rows and columns. Information is preferably transmitted to or from the processor arrangement by means of the portal processor exclusively via at least part of the processor units located at the edge of the processor arrangement.

This procedure clearly means that, starting from an "introductory processor unit" at the reference position, usually at the edge of the processor arrangement, that is to say at a pixel external to the processor arrangement, a first distance is assigned, for example the

Distance value "1", which indicates that the initiating processor unit is at a distance "1" from the portal processor. In the event that the distance of the processor unit sending the message from the reference position is inserted into the message in each case and transmitted to the processor unit to be received, the first Processor unit transmits the distance value "1" to the second processor unit in the first message and the received distance value is incremented by a value "1" by the second processor unit. The incremented value "2" is now stored as an updated second distance value of the second processor unit. The second distance value is incremented by a value "1" and a third distance value is generated and transmitted to the third processor unit and stored there. The corresponding procedure is carried out in a corresponding manner for all processor units and the distance value assigned to a processor is updated after receipt of a message with distance information whenever the received distance value is smaller than the stored distance value.

A processor arrangement has a multiplicity of processor units. Each processor unit is coupled to at least one processor unit adjacent to it via a bidirectional communication interface. To the

Ascertaining the respective distance of a processor unit of the processor arrangement from a reference position, messages are exchanged between the respective processor units, preferably between adjacent processor units, each message being one

Contains distance information, which indicates the distance of a processor unit sending the message or a processor unit receiving the message from the reference position (also referred to as distance value) and wherein each processor unit is set up such that from the

Distance information of a received message, the own distance to the reference position can be determined or stored.

The invention can be clearly seen in that the global and direct provided according to the prior art Processor control via column and row lines is abandoned.

Due to the use of only local information and the exchange of electronic messages, in particular between processors that are directly adjacent to one another, the procedure is very robust against occurring malfunctions and failures of individual processor units or individual connections between two processor units.

The pixel arrangement, preferably the matrix-shaped pixel arrangement, is partitioned into certain areas, for example into image blocks, and an information processing unit, the pixel processor, is assigned to each area. The area can contain a pixel or a sensor or a plurality of pixels or sensors, each of which is controlled by a processor unit. The processors are preferably distributed in a coarser grid than the pixels or sensors themselves, which clearly corresponds to spatial subsampling. In this way, the problem of wiring and addressing via column lines and row lines in the case of a matrix-shaped pixel arrangement is alleviated, since the respective lines which the processor units connect to one another and with a pixel arrangement

Connect control circuit, according to the invention can be dimensioned more generously, that is to say spatially thicker and thus subject to a lower electrical resistance. Each pixel group processor controls the corresponding image area independently, for example by means of a passive matrix control or an active matrix control. The size of the sub-display units is preferably selected in such a way that the problems described above of slow charging of the pixel elements and of the very short period of time between two drive cycles do not occur with a given selection device and a given wiring technique. In the In principle, pixel group processors can implement any routing instructions for the image information to be displayed or the sensor information to be detected, so that the image information or the sensor information in the form of electronic data transmission also about defects that occur in the display, that is to say in the display device, that is to say the pixel arrangement ( for example in the event of physical destruction such as a punctual defect, holes, cracks, etc.). This leads to an increased defect tolerance of the device according to the invention. According to the invention, a pixel arrangement is thus provided and a method is provided with which it is possible in a very simple manner to determine the distance of a respective pixel from a reference position and thus also the local position of a pixel within the pixel arrangement. The determination is no longer based on global information, but on local information, which is exchanged in the form of messages between two adjacent processor units. In other words, the problem of distance determination is solved by

Self-organization based on local message exchange between neighboring processor units solved. The self-organization method thus has different distributed local uniform algorithms that exchange the respective messages via the respective bidirectional communication interface. In other words, according to the invention, the distance is determined on the basis of self-organization based on purely local information.

According to the invention, a pixel includes both an imaging unit or a sound-generating unit, for example a liquid crystal screen unit or a polymer electronics display unit or generally any type of screen which has a multiplicity of pixels, or a loudspeaker which generates a sound wave, generally to understand each element generating an electromagnetic wave. Alternatively, the invention can be used in a pixel arrangement in which at least some of the pixels are designed as sensor elements, that is to say the pixel arrangement in this case consists at least partially in a sensor field. This could, for example, also be a screen unit with a touchpad integrated into it, which can in particular also be divided into a number of image tiles, in other words, a number of image areas, wherein a processor unit can be assigned to each image area. At least some of the sensors can each be set up as a sound sensor or as a pressure sensor (for example a piezo crystal sensor), alternatively as a gas sensor, as a vibration sensor, as a deformation sensor or as a tension sensor.

Preferred developments of the invention result from the dependent claims. The embodiments of the invention described below relate to the method according to the invention and the processor arrangement according to the invention.

According to a development of the invention, each processor unit is coupled to at least one pixel, so that the pixel can be controlled by the respective processor unit assigned to it.

According to this embodiment of the invention, not only the distances between processor units coupled to one another, but also the distances between the respective pixels are determined. This is an important basis for routing of detailed image information to be displayed for the individual pixels used for the display of image information, of which the respective image information is displayed. Correspondingly, the distance determination of the pixels also forms a basis for routing sensed sensor information from the pixel to the external interfaces to, for example, the portal processor. According to another development of the invention, at least some of the pixels are each designed as a sensor. In this case, according to the invention, a distance determination is carried out for individual sensor pixels in a large-area sensor field.

As an alternative or in addition, at least some of the pixels can each be designed as an imaging element or generally an element generating and emitting an electromagnetic wave, for example as a sound-generating and emitting element. In this case, according to the invention, a distance determination is carried out for individual imaging elements in a large-area, preferably matrix-shaped, display.

The processor units can each be arranged in a hexagonal area, in which case each

Processor unit each has six adjacent processor units, each via a bidirectional

Communication interface are coupled to the processor unit.

Furthermore, the pixels themselves can have a hexagonal shape.

A very high packing density in the respective arrangement is achieved by using a hexagonal shape.

Alternatively, the processor units can each be arranged in a rectangular area, in which case each processor unit has four adjacent processor units, each of which is coupled to the processor unit via a bidirectional communication interface. Furthermore, the pixels themselves can have a rectangular shape.

According to another embodiment of the invention, before determining the distance of the pixel processors from the reference position, the local positions of the processor units within the processor arrangement are determined by starting from a processor unit at an introduction point of the processor arrangement, each determining position messages which have at least one line parameter z and have a column parameter s, which contains the line number or column number of the processor unit sending the message or the line number or column number of the processor unit receiving the message within the processor arrangement, to adjacent ones

Processor units are transmitted and the following steps are carried out by the respective processor unit:

If the line parameter in the received message is greater than the previously stored line number of the processor unit, the line parameter value z of the received message is assigned to the own line number of the processor unit,

• If the column parameter in the received message is larger than the processor unit's own column number, the saved one is saved

Column number assigned to the row parameter value of the received message,

• If the own line number and / or the own column number have been changed due to the above-described method steps, then new position ess messages are generated with new line parameters and new column parameters, which each contain the line number and column number of the processor unit sending the message or the line number and Column number of the recipient of the message

Processor unit contains, and these are about the transmit bidirectional communication interfaces to a respective neighboring processor unit.

Through this development, the concept of local message exchange between adjacent processor units according to the invention is further expanded, since the local positions of the individual processor units within the processor arrangement according to this concept are based on local position information, which only results from one of the immediately adjacent ones

Processor unit obtained position information is based. This enables a very robust procedure within the framework of the self-organization of the processor arrangement.

According to another development of the invention, the own distance value of the processor unit is changed in an iterative method if the previously stored distance value is greater than the distance value received in the respective received message increased by a predetermined value, and in the event that a processor unit has its own If the distance value changes, this generates a distance measurement message and sends it to neighboring processor units via all communication interfaces, the distance measurement message in each case containing its own distance as distance information or the distance value that the received processor unit has from the portal processor.

The distance value can be changed by a value increased by a predetermined value compared to the own distance value, preferably by the value “1”.

According to another aspect of the invention, a pixel arrangement is provided which has a multiplicity of pixels, which pixels are grouped into a multiplicity of pixel groups, and a multiplicity of processor units. A processor unit is assigned to a pixel group and controls the pixels of the respective pixel group.

This aspect of the invention can clearly be seen in that the pixels are grouped into groups and one processor unit is responsible for the “reading” and “writing” control of the pixels in a group, namely the pixel of the group to which the processor unit is assigned ,

In other words, the pixel arrangement, preferably a matrix-shaped pixel arrangement, is partitioned into certain areas, for example image blocks, and each area is assigned an information processing unit, the pixel processor. The area can be one

Contain pixel or another element generating an electromagnetic wave or a sensor or a plurality of pixels, elements or sensors generating electromagnetic waves, each of which is controlled by a processor unit. Preferably, the

Processors distributed in a coarser grid than the pixels or sensors themselves, which clearly corresponds to a spatial subsampling. In this way, the problem of wiring and addressing via column lines and row lines in the case of a matrix-shaped pixel arrangement is alleviated, since the respective lines which connect the processor units to one another and to a pixel arrangement control circuit are, according to the invention, more generous, i.e. spatially thicker and thus can be dimensioned with a lower electrical resistance. Each pixel group processor controls the corresponding image area independently, for example by means of a passive matrix control or an active matrix control. The size of the sub-display units is preferably chosen such that the problems described above of the slow charging of the pixel elements and the very short time period between two Drive cycles do not occur with a given selection device and a given wiring technique. In principle, any routing rules for the image information to be displayed or the sensor information to be detected can be implemented in the pixel group processors, so that the image information or the sensor information in the form of electronic data transmission also about defects that occur in the display, that is to say in the display device, that is to say the pixel Arrangement (for example in the event of physical destruction such as a punctual defect, holes, cracks, etc.) can be redirected. This leads to an increased defect tolerance of the device according to the invention. According to the invention, a pixel arrangement is thus provided and a method is provided with which it is possible in a very simple manner to determine the distance of a respective pixel from a reference position and thus also the local position of a pixel within the pixel arrangement. The determination is no longer based on global information, but on local information, which is exchanged in the form of messages between two adjacent processor units. In other words, the problem of distance determination is solved by self-organization based on local message exchange between neighboring processor units. The self-organization method thus has different distributed local uniform algorithms that exchange the respective messages via the respective bidirectional communication interface. In other words, according to the invention, the distance is determined on the basis of self-organization based on purely local information.

According to the invention, the hierarchical structure of the grouping can also be applied to the processor units. In other words, the processor units themselves are again divided into groups can be, which are controlled by further processor units of another hierarchy level, in which case one processor unit of a "controlling" group controls all processor units of the "controlled" group.

In other words, a first set of processor units can be assigned to first processor groups and a second set of processor units can be assigned to second processor groups. The number of processor units of the first set of processor units is greater than the second set of processor units. According to this embodiment of the invention, the processor units of a second processor group are each coupled only to processor units of a respective first processor group assigned to them. Each processor unit of the first processor group is assigned to a pixel group and controls the pixels of the respective pixel group.

It should be noted in this connection that any number of different sets of processor units can be provided, which can be provided in any number of hierarchy levels and can each be grouped into groups of processor units, which in turn are assigned by a processor unit that is assigned to it , is controlled. In this case, a multitude of hierarchy levels arise, which further increases the control efficiency of the pixel arrangement.

In a method for determining a distance from processor units to at least one reference position in the pixel arrangement with a plurality of processor units, each processor unit is coupled to at least one processor unit adjacent to it via a bidirectional communication interface. The processor units exchange electronic messages with one another, in particular between processor units which are immediately adjacent to one another. According to the procedure, a generates a first message from a first processor unit, which is located at the at least one reference position. The first message contains first distance information, which contains the distance of the first processor unit or the distance of a second processor unit receiving the first message from the reference position. The first message is transmitted from the first processor unit to the second processor unit. Depending on the first distance information, the distance of the second processor unit from the

Reference position determined or saved. A second message is generated by the second processor unit, which contains a second distance information which contains the distance of the second processor unit or the distance of a third processor unit receiving the second message from the reference position. The second message is transmitted from the second processor unit to the third processor unit. The respective messages are preferably always transmitted via the bidirectional communication interface of the respective processor units which are immediately adjacent to one another. Depending on the second distance information, the distance of the third processor unit from the reference position is determined or stored. The storage preferably takes place locally in a local memory, that of a respective one

Processor unit is assigned. The method steps described above are carried out iteratively for all processor units in the pixel arrangement.

The reference position can in principle be arbitrary, preferably the reference position is a position at which a portal processor described below is located, which controls the processor units in the processor arrangement and initiates communication from outside the pixel arrangement. The reference position can also be a position within the pixel arrangement, in which If a processor unit is preferably arranged at the reference position and assigned to it. In this case, the

Reference position on the edge, i.e. on the top or bottom row or the left or right column in the event that the processor units in the pixel arrangement are arranged in a matrix in rows and columns. Information is preferably transmitted to or from the pixel arrangement by means of the portal processor exclusively via at least part of the processor units located at the edge of the pixel arrangement.

This procedure clearly means that, starting from an "introductory processor unit" at the reference position, usually at the edge of the pixel arrangement, that is to say at a pixel external to the processor arrangement, a first distance is assigned, for example the distance value "1", which indicates that the initiating processor unit is at a distance "1" from the portal processor. In the event that the distance of the processor unit sending the message from the reference position is inserted into the message in each case and transmitted to the processor unit to be received, the distance value "1" from the second processor unit becomes transmitted in the first message and the received distance value is incremented by a value "1" by the second processor unit. The incremented value "2" is now stored as an updated second distance value of the second processor unit. The second distance value is incremented by a value "1" and a third

Distance value is generated and transmitted to the third processor unit and stored there. The corresponding procedure is carried out in a corresponding manner for all processor units, and the distance value assigned to a processor is always after receiving a message with distance information updated when the received distance value is less than the stored distance value.

The pixel arrangement has a multiplicity of processor units. Each processor unit is coupled to at least one processor unit adjacent to it via a bidirectional communication interface. To determine the respective distance of a processor unit of the pixel arrangement from a reference position, messages are exchanged between the respective processor units, preferably between adjacent processor units, each message containing distance information which indicates the distance between a processor unit sending the message or a processor unit receiving the message specifies the reference position (also referred to as distance value) and each processor unit is set up in such a way that the distance to the reference position can be determined or stored from the distance information of a received message.

According to this embodiment of the pixel arrangement, the global and direct processor control provided according to the prior art is advantageously abandoned via column and row lines.

Due to the use of only local information and the exchange of electronic messages, in particular between processors that are directly adjacent to one another, the procedure is very robust with respect to occurring ones

Malfunctions and failures of individual processor units or individual connections between two processor units.

According to one embodiment of the invention, each processor unit is coupled to each processor unit immediately adjacent to it in such a way that it is connected to the neighboring processor units can exchange electronic messages.

According to this configuration of the pixel arrangement, it is not only the distances of those coupled to one another

Processor units, but also the distances between the respective pixels. This is an important basis for routing of detailed image information to be displayed for the individual pixels used for the display of image information, of which the respective image information is displayed. Correspondingly, the distance determination of the pixels also forms a basis for routing sensed sensor information from the pixel to the external interfaces to, for example, the portal processor.

According to another development of the pixel arrangement, at least some of the pixels are each designed as a sensor. In this case, according to the invention, a distance determination is carried out for individual sensor pixels in a large-area sensor field.

Alternatively or additionally, at least some of the pixels can each be designed as an imaging element. In this case, according to the invention, a distance determination is carried out for individual imaging elements in a large-area, preferably matrix-shaped, display.

Processor unit each has six adjacent processor units, each of which is coupled to the processor unit via a bidirectional communication interface.

Furthermore, the pixels themselves can have a hexagonal shape. A very high packing density in the respective arrangement is achieved by using a hexagonal shape.

Alternatively, the processor units can each be arranged in a rectangular area, in which case each processor unit has four adjacent processor units, each of which is coupled to the processor unit via a bidirectional communication interface.

Furthermore, the pixels themselves can have a rectangular shape.

According to another embodiment of the pixel arrangement, before determining the distance of the pixel processors from the reference position, the local positions of the processor units within the processor arrangement are determined by starting from a processor unit at an introduction point of the processor arrangement

Position determination messages which have at least one row parameter z and one column parameter s, which contains the row number or column number of the processor unit sending the message or the row number or column number of the processor unit receiving the message within the processor arrangement, are transmitted to adjacent processor units and the following steps are carried out by the respective processor unit:

• if the line parameter in the received message is larger than the previously stored line number

Processor unit, the own line number of the processor unit is assigned the line parameter value z of the received message,

• if the column parameter in the received message is larger than the column number of the

Processor unit, so the stored Column number assigned to the row parameter value of the received message, • If the own row number and / or the own column number have been changed due to the above-described process steps, new position measurement messages are generated with new row parameters and new column parameters, each of which the row number and column number of the Processor unit sending the message or the row number and column number of the recipient of the message

Contains processor unit, and these are transmitted via the bidirectional communication interfaces to a respective neighboring processor unit.

Through this development of the pixel arrangement, the concept of local message exchange between adjacent processor units according to the invention is further expanded, since the local positions of the individual processor units within the processor arrangement according to this concept are based on local position information, which only results from one of the direct adjacent processor unit obtained position information is based. This enables a very robust procedure within the framework of the self-organization of the processor arrangement.

According to another development of the pixel arrangement, the own distance value of the processor unit is changed in an iterative process if the previously stored distance value is greater than the distance value received in the message received, which is increased by a predetermined value, and in the event that a processor unit changes its own distance value, this generates a distance measurement message and sends it to neighboring ones via all communication interfaces

Processor units, the distance measurement message each containing the own distance as distance information or the Distance value that the received processor unit has from the portal processor.

The methods and arrangements described above are particularly suitable for use in the following areas of application.

According to one embodiment of the invention, it is provided that the processor units and optionally additionally the pixels, i.e. the elements generating and emitting an electromagnetic wave or the sensors to be applied to textile material and by means of electrically conductive couplings which are woven into the textile material, for example. Alternatively, the textile material itself can contain electrically conductive structures in order to electrically connect the processor units and / or the pixels to one another. The processor units and / or the pixels are preferably arranged on the crossing points within the structure of the textile material, e.g. at the crossing points of the electrically conductive warp and weft threads of a textile fabric.

In a development of the invention, sound transmitters and sound sensors can be applied as pixels on the textile material, a garment preferably being made from the textile material. Using the sound transmitter and sound sensors as pixels, the position of the item of clothing and thus the position of a person wearing the item of clothing in a room or in a building can be determined.

Furthermore, by means of sensors integrated according to the invention in a garment, for example vital functions can be monitored in a person wearing the garment. In general, any sensors or actuators can be integrated as pixels in a textile material and preferably in a piece of clothing.

In an alternative embodiment, the textile material is configured as textile concrete, in other words as reinforcement in the concrete.

A textile concrete set up in this way can thus be provided in a simple manner with pixels set up, for example, as pressure sensors and / or as vibration sensors and / or as tension sensors and / or as deformation sensors. Such a textile concrete according to the invention can be installed very flexibly, in particular due to the self-organizing method for determining the position. In the case of a house, the textile concrete with the pixels and the processor units can be used to detect possible dangerous conditions in the house (excessive weight load on a concrete ceiling) and to use the processors to send a corresponding warning message to a master computer electrically connected to it via a house interface.

Alternatively, the textile concrete according to the invention can be used to build bridges. A bridge with one

Textile concrete has the particular advantage that it is now very easy to determine dangerous vibrations or deformations of the bridge structure using the integrated pixel sensors and to transmit a corresponding warning message to a host computer.

Another area of application of the textile concrete according to the invention can be seen in road construction. A road with textile concrete can be very simple with regard to the

Road use (for example the number of vehicles, etc.) or also for traffic control control, generally for Traffic monitoring, even used for speed control, since the pixel sensors integrated in the textile concrete can be used to determine at which point and at what point in time a vehicle is driving over the corresponding area of the road, which is "monitored" by a respective sensor.

Exemplary embodiments of the invention are shown in the figures and are explained in more detail below. Identical components are provided with identical reference symbols in the figures.

Show it

Figure 1 is a plan view of a pixel arrangement according to a first embodiment of the invention;

Figures 2a to 2d top views and a sectional view of individual pixels that can be provided in the pixel arrangement, wherein the pixel can have a rectangular shape (Figure 2a), a triangular shape (Figure 2b) or a hexagonal shape (Figure 2c) ; FIG. 2d shows a sectional view through the pixels shown in FIGS. 2a to 2c;

FIG. 3 shows a block diagram in which the pixel arrangement with the control device is shown schematically;

Figure 4 is a plan view of a processor arrangement according to the first embodiment of the invention;

FIG. 5 shows a plan view of a processor arrangement according to a second exemplary embodiment of the invention;

FIG. 6 shows a plan view of a processor unit in hexagonal form; FIGS. 7a and 7b a directed graph (FIG. 7a) and an undirected graph (FIG. 7b);

Figure 8 shows a directed tree;

FIGS. 9a and 9b show a sketch of a processor arrangement, modeled as an undirected graph (FIG. 9a) and as a directed graph (FIG. 9b);

FIG. 10 shows a sketch of different routing paths as a directed tree with an input node as the root;

FIG. 11 shows a sketch of an optimized routing tree;

FIGS. 12a to 12j show a sketch of the routing tree from FIG. 11 at different activation times;

Figures 13a to 13f a sketch of the routing tree from Figure 11 to different

Driving times;

Figure 14 is a plan view of two hexagonal

Processor units in which the bidirectional message exchange between the two

Processor units is shown;

Figure 15 is a sketch of an incoherent processor unit;

FIG. 16 shows a sketch of a coherent processor unit when sending measurement coherence messages;

FIG. 17 shows a sketch of a processor unit, on the basis of which the sending of measurement position messages is explained; FIG. 18 shows a sketch of a processor arrangement after the position of the individual processor units has been determined within the processor arrangement;

FIG. 19 shows a sketch of a processor unit, on the basis of which the sending of a measurement distance message is explained;

FIG. 20 shows the processor arrangement after the distance has been determined, the processor arrangement having a multiplicity of introductory processor units at the lower edge of the processor arrangement;

FIG. 21 shows a processor arrangement after the distance has been determined, with every third

A reference position is assigned to the processor unit in the bottom line of the processor arrangement;

FIG. 22 shows a sketch of a processor unit, on the basis of which the receiving and sending of MessOrganize messages is explained;

FIG. 23 shows a sketch of a processor unit, on the basis of which the organization sequence for sending a

MessChannel message is shown in an even column within the processor arrangement;

FIG. 24 shows a sketch of a processor unit, on the basis of which the organization sequence for sending a

MessChannel message is shown in an odd column within the processor arrangement;

FIG. 25 shows a sketch of a plurality of processor units on the basis of which the organization and the

Exchange of messages via channels that the Coupling communication interfaces of the processor units with one another are explained;

Figure 26 shows a processor arrangement after regular backward organization in the event that all

Processor units in the bottom line of the processor arrangement can be supplied or sent with information from or to a portal processor;

FIG. 27 shows a processor arrangement after regular backward organization has taken place in the event that information can be supplied or sent to or from a portal processor to every third processor unit in the bottom line of the processor arrangement;

FIG. 28 shows a sketch of a processor unit, on the basis of which the reception and transmission of MessCountNodes messages is explained,

FIG. 29 shows a sketch of a processor unit, on the basis of which the receiving and sending of MessNodesSize messages is explained,

FIG. 30 shows the processor arrangement after the throughput of the processor units has been determined in the event that all processor units in the bottom line of the processor arrangement can be supplied with or sent to or from a portal processor;

FIG. 31 shows the processor arrangement after the throughput of the processor units has been determined in the event that every third processor unit is in the lowest

Line of processor arrangement information from or can be fed to a portal processor or can be sent;

FIG. 32 shows a sketch of a processor unit, on the basis of which the sending of MessColDistance messages is explained;

FIG. 33 shows a sketch of a processor unit, on the basis of which the reception and transmission of measurement block token messages is explained;

FIG. 34 shows a sketch of a processor unit, on the basis of which the reception of a measurement token message by an “uncolored” processor unit is illustrated;

FIG. 35 shows the processor arrangement after meander channels have been determined in the processor arrangement when tokens have been issued in the event that all processor units in the bottom line of the processor arrangement have information from or to one

Portal processor can be fed or can be sent;

FIG. 36 is a sketch of a processor unit on the basis of which the receiving and sending of MesseleteChannels

News is explained;

FIG. 37 shows a sketch of a processor unit, on the basis of which the reception and transmission of MessColOrganize messages is explained;

FIG. 38 shows the processor arrangement after completion

Reorganization in the event that every third processor unit in the bottom line of the processor arrangement information from or to one

Portal processor can be fed or can be sent; FIG. 39 shows the processor arrangement after reorganization in the event that all processor units in the bottom line of the processor arrangement have information from or to one

Portal processor can be fed or can be sent;

FIG. 40 shows a sketch of a processor unit, on the basis of which the initialization of the introductory processor unit color is explained by means of a MessColDistance message;

FIG. 41 shows the processor arrangement after reorganization with a weight g = 0 in the event that all processor units in the bottom line of the processor arrangement can be supplied with or sent to or from a portal processor;

FIG. 42 shows the pixel arrangement after reorganization with a weight g = ∞ in the event that all processor units in the bottom line of the processor arrangement can be supplied with or sent to or from a portal processor;

FIG. 43 shows a sketch of a processor unit, on the basis of which the reception and transmission of measurement numbering messages is explained;

44 shows a sketch of the processor arrangement after the numbering has taken place in the event that all processor units in the bottom line of the processor arrangement have information from or to one

Portal processor can be fed or can be sent; FIG. 45 shows the processor arrangement after the numbering has been carried out in the event that information from or to a portal processor can or can be sent to every third processor unit in the bottom line of the processor arrangement;

FIG. 46 shows a routing table according to an exemplary embodiment of the invention;

FIG. 47 shows a sketch of a processor arrangement on the basis of which the routing and the representation of pixel data are explained;

FIG. 48 shows a sketch of a processor unit, on the basis of which the reception and transmission of measurement retry messages is explained;

FIG. 49 shows a sketch of a processor arrangement with a multiplicity of processor units and a multiplicity of pixels, a group of pixels in each case being assigned to a processor unit;

FIG. 50 shows a sketch of a 4 × 4 pixel group and its control by means of a processor unit; and

Figure 51 shows an overview of the messages used.

1 shows a pixel arrangement 100 according to a first exemplary embodiment of the invention.

The processor arrangement 100 is formed in accordance with a so-called "Fluidic Soap Assembly" (FSA) from Alien Technology ™ described in [3].

The processor arrangement 100 has a substrate 101 with a multiplicity of depressions 102. The substrate 101 is according to In this exemplary embodiment, a thin, flexible plastic film with a large number of recesses punched into it, via which a suspension with a large number of processor units 103, which are designed as computer chips 103 and have a size between 50 μm to 1000 μm, are washed into a liquid. The computer chips 103 are also referred to as nanoblocks. The size and shape of the integrated computer chips 103, which are referred to below as processor units 103, correspond to those of the depressions 102, so that the processor units 103 insert themselves into the depressions 102 automatically, that is to say in a self-regulating manner.

This process is shown schematically in Fig.l. In the manner described above, a field or an array of processor units is created which is subsequently meshed with one another, that is to say electrically coupled to one another.

The processor arrangement 100 becomes one

Image display device designed in which the processor units are used to control the pixels. For this purpose, an electro-optical medium (for example luminous, reflective, etc.), preferably a luminous medium, is placed over the array of processor units 103 formed, to which electrical couplings are created on the basis of the corresponding processor units 103 controlling the electro-optical medium.

Each processor unit 103 is responsible for the pixel located directly above it, that is to say drives it, or for the pixel region located above it, that is to say a pixel area with a plurality of pixels that are grouped into a pixel area.

For this reason, processor units 103 are also referred to below as pixel processors 103. In this context, it should be noted that the invention is in no way limited to imaging elements as a processor arrangement or pixel arrangement, but can also be used for a sensor array with a plurality of sensors that are electrically coupled to one another and controlled via one or more processor units 103 in each case ,

Arrays can also be used according to the invention which contain partly imaging elements and partly sensor elements.

According to the invention, the shape of the individual processor units 103 can be of any configuration, for example rectangular as shown in FIG. 2a, triangular as shown in FIG. 2a or hexagonal as shown in FIG. 2c.

FIG. 2D shows a trapezoidal cross section through the respective processor units 103. The trapezoidal cross section ensures that the individual pixels insert themselves more easily and with greater probability into the depressions 102 of the pixel arrangement.

In the following, a pixel arrangement, which is designed as an image-displaying system, that is to say, in other words, an imaging system, is described without restricting the general validity.

The image display system 300 according to an embodiment of the invention is shown schematically in FIG. 3 in a block diagram.

The imaging system 300 has a source 301 which represents the source of the information to be displayed and, according to this exemplary embodiment, a central processing unit (CPU), a graphics processor, Contains sensors or other input devices and optionally other components.

Furthermore, a display unit portal 302 which is electrically coupled to the source 301 is provided, which functions as an intermediary between the source 301 and the actual pixel arrangement 303 which is likewise coupled to the display unit portal 302 (which has the processor arrangement and the pixels ) represents. The display unit portal 302 is used according to the invention to generate a trigger, that is to say a trigger signal, in accordance with this exemplary embodiment a trigger message, for initializing the self-organization, and for distributing information about initiating processor units in the processor arrangement 303.

The processor arrangement 303 has an array of uniform, so-called intelligent pixels or pixel regions, which are formed by processor units 103 and the pixels coupled to the processor units 103 and controlled by the processor units 103. The processor units 103 are meshed with one another, that is to say coupled to one another via bidirectional communication interfaces respectively assigned to the processor units 103.

Some processor units 103 of the plurality of

Processor units 103 in the pixel arrangement 303 serve as introduction nodes for feeding information from the display unit portal 302 into the processor arrangement 100 of the pixel arrangement 303.

According to this exemplary embodiment, the respective processor - hereinafter referred to as the portal processor - of the display unit portal 302 has no information about the size and configuration of the pixel arrangement 303. The individual processor units 103 or the pixels coupled to the processor units 103 also have no information at the start of the method Information about their respective Orientation, ie orientation, or their local position within the processor arrangement.

The individual pixel processors, that is to say the processor units, also have no information about their own orientation and position, that is to say their local position within the processor arrangement.

In an initialization phase, which is explained in more detail below (before the first use of the pixel arrangement 303 or after the stored information has been reset in the pixel arrangement 303), the portal processor of the display unit portal 302 triggers a self-organization of the processor arrangement, such as it is explained in more detail below.

As part of the self-organization of the processor arrangement, the processor units 103 of the pixel arrangement 303 learn their position and orientation as well as information paths for image construction, that is to say for supplying them

Image information to the respective pixels, which should actually represent the respective image information.

This learning process takes place using messages which are exchanged between processor units in the pixel arrangement 303 which are adjacent to one another. Some of the knowledge that has been learned is given back to the outside, that is to say to the display unit portal 302, to the extent that the display unit portal 302 will need it later in order to display the image information in the correct ways and in the correct sequence of the pixel Arrangement 303 to be supplied for displaying an image to be displayed in each case.

The type of image information must be taken into account for the image structure, that is to say for the procedure for distributing information to be displayed within the pixel arrangement 303. In accordance with these exemplary embodiments, individual pixel data for representing a complete image or a differential image, for example in the context of compressed video images, are transmitted to the individual pixels, that is to say more precisely to the individual pixel processors 103. For this purpose, each pixel processor 103 is individually addressed by the portal processor of the display unit portal 302. This leads to routing of the image information to the corresponding pixels, and thus to the corresponding processor units within the pixel arrangement, which is required as part of the display of image information. When routing single pixel data, the following special features of the routing problem must be taken into account according to the invention:

Routing routes are only determined between the portal processor of the display unit portal 302 and the individual pixel processors, that is to say the processor units of the pixel arrangement 303, but not between the pixel processors.

• The routing volume is even, ie exactly one pixel date must be transmitted to each pixel processor for each digitized image to be displayed.

• There is no global knowledge of the shape of the network, that is, the meshing of the individual

Pixel processors provided within the processor arrangement. The choice of routing routes within the processor arrangement is based on local information which is exchanged between the individual pixel processors using electronic messages.

According to the invention, two phases are to be differentiated when using a pixel arrangement according to the invention: In a first phase, the so-called self-organization, a

• Self-recognition of the local positions of the individual pixel processors within the pixel arrangement and thus the overall shape of the pixel arrangement;

Self-organization of routing routes starting from the portal processor, that is to say the processor of the display unit portal 302, to each pixel processor in the pixel arrangement 303 in such a way that everyone can do so within a predetermined maximum number of time cycles

Pixel processor can receive an electronic message from the processor of the display unit portal 302.

In a second phase, the actual use of the pixel arrangement 303 in the context of the representation of image data, the image data are sent from the portal processor to the pixel processors, that is to say transmitted, as a result of which the image to be displayed is built up in the pixel arrangement 303.

The pixel processors 103, as shown in FIG. 4, in the event that they have a rectangular shape, preferably a square shape, on each side of the rectangle via one of the four bidirectional communication interfaces 401 per provided

Pixel processor 103 and above via electrical lines 402 each coupled to the pixel processor 103 directly adjacent to a respective pixel processor 103.

In other words, that means one at a time

Message exchange between two immediately adjacent pixel processors is enabled, but not an immediate, ie direct message exchange over a further distance than the immediate vicinity of a pixel processor 103. FIG. 5 shows another exemplary embodiment in which each pixel processor 103 has a hexagonal shape and six bidirectional ones per pixel processor 103

Communication interfaces 501, also on each side, that is to say the side edge, of the respective pixel processor 103 are provided. This means that, according to this exemplary embodiment, each pixel processor 103 has six neighboring pixel processors 103, with which the respective pixel processor 103 is coupled via a bidirectional communication interface 501 and an electrical line 502 for the exchange of electronic messages.

To simplify the illustration of the invention, only the case of the hexagonal shape of a pixel processor 103 is described below, but without restricting the generality.

The pixel arrangement 100 thus has two types of individual components:

Pixel processors 103, each of which is assigned up to six bidirectional communication interfaces 501 and electrical lines 502, and

Bidirectional connections, furthermore also as bidirectional communication interface 501 and electronic line 502 assigned to the respective communication interface 501, each of which couples two pixel processors 103 or one pixel processor 103 and the portal processor.

The hexagonal pixel processor 103 can have six different orientations, as shown in FIG.

According to FIG. 6, the individual connections, that is to say also the individual communication interfaces 501, have already been oriented during the self-organization phase, as will be explained in more detail below. The connections are numbered in accordance with this exemplary embodiment and identified with cardinal directions for better understanding, the following nomenclature being used in accordance with this exemplary embodiment: a first orientation 0 (east) (reference symbol 600), in other words an orientation to the right,

A second orientation 1 (northeast) (reference number 601), in other words an orientation to the top right,

A third alignment 2 (northwest) (reference symbol 602), in other words an alignment to the top left,

A fourth orientation 3 (west) (reference number 603), in other words an orientation to the left,

A fifth orientation 4 (south-west) (reference symbol 604), in other words an orientation towards the bottom left, and

A sixth orientation 5 (southeast) (reference numeral 605), in other words an orientation towards the bottom right.

According to this exemplary embodiment, it is assumed that the portal processor of the display unit portal 302 has electrical connections to pixel processors 103 on only one side of the pixel arrangement 100.

By definition, this is the lower side of the pixel arrangement 100, that is to say clearly the south side, the couplings likewise by definition running over the south-west side, that is to say over the fifth alignment direction of the respective pixel processors 103.

In this context, it should be noted that both the positioning and the orientation of the individual introduction points of information about the pixel processors 103 in the processor arrangement 100 and the shape and orientation of the individual pixel processors 103 in the processor arrangement 100 are basically arbitrary , In different embodiments of the invention is the portal processor

Electrically coupled to all pixel processors 103 of the lowest line in the form of a matrix, that is to say arranged in rows and columns, pixel processors 103 of the processor arrangement 100, or

With pixel processors 103 of the bottom line of the processor arrangement in a predetermined, regular, that is to say periodic distance, that is to say every third, fifth, tenth, etc., pixel processor 103 within the bottom line of the processor arrangement.

Although the portal processor knows the number of its connections to the pixel processors 103 after the manufacture of the pixel arrangement 303, in other words the number of introduction points for supplying information to pixel processors 103 within the pixel arrangement 303, it does not necessarily know the dimension and the configuration of the Pixel arrangement 303 and thus the processor arrangement, that is to say the actual shape and arrangement of the pixel processors 103 within the processor arrangement 100.

In this context, it should be noted that, in particular, an indication of the direction, for example the south side, does not necessarily have to represent a straight line within the processor arrangement 100.

In the partial methods explained below, it is only necessary to provide that the individual connections between the

Portal processor and the pixel processors 103 should always take place in the same place, according to this exemplary embodiment via the southwest side 604.

The individual pixel processors 103 or the connections, both of which are generic terms as individual components of the The following states can assume the following:

1. Error-free: The respective component of the pixel arrangement works without restrictions.

2. Defect:

The respective component of the pixel arrangement has failed completely. If the component is a processor unit, all connections to this processor unit must also be declared defective.

3. Unstable: The component has partial failures, for example a direction of a bidirectional connection between the respective processor unit only works intermittently (that is to say it has a loose contact or works methodologically incorrect, for example a processor which sends an incorrect message).

In the following, the third state is not considered for the sake of simplifying the illustration of the invention, that is to say one component is either faultless or defective in the following. Therefore, it does not play according to these embodiments

Role whether a component does not exist due to a special shape of the pixel arrangement (for example, a display unit film which has the shape of a triangle), or whether the respective component has become defective due to a manufacturing defect or due to wear.

In the case of information transfer, which is explained in more detail below, that is to say the sending of electronic messages between two pixel processors 103 within the pixel arrangement 303 or from the portal processor to a pixel processor 103 at one The point of introduction of the pixel arrangement 303 is considered below a clocking of the overall system, that is to say of the entire pixel arrangement 303.

Each pixel processor 103 in the pixel arrangement 303 is set up in such a way that it can carry out the following actions within a time cycle:

Reading of one or more electronic messages which are present on one or more connections, that is to say via one or more bidirectional communication interfaces of the respective pixel processor, and which were sent by a neighboring pixel processor in the previous time cycle. • Processing the received message.

If appropriate, sending one or more messages over one or more connections and thus over one or more bidirectional communication interfaces of the pixel processor 103, which can be received by a neighboring pixel processor in the chronologically subsequent, that is to say the next, clock cycle.

An electronic message can thus only be transmitted from one pixel processor 103 to a neighboring pixel processor 103 within a time cycle.

In this context, however, it should be noted that according to the invention, no global clocking of the pixel processors 103, that is to say that provided for the entire processor arrangement 100, must exist, but this is assumed below to simplify the illustration of the invention.

In order to facilitate understanding of the procedure according to the invention, the basics of mathematical modeling of the pixel arrangement are explained below. Furthermore, the pixel processors 103 and the display unit portal 302 are modeled together as a directed graph and the routing paths as a directed tree.

The choice of routing thus arises as a discrete optimization problem.

Definition 1 (directed graph, undirected graph)

(I)

Given a set V and a set E. Is

E → V "= V x V

an illustration with the components

g ^~ : E → V and g ⁺ : E -> V,

i.e.

E → V '

e ι- → g ^" (4 ^g + ^{ (.e)

that's the name of the tuple

(V, E, g)

directed graph with set of vertices (set of nodes) V, set of edges E and incidence map g. g ^" (e) is the initial corner of the edge ee E and g ⁺ (e) is the terminating corner of the edge e E E. (G)

Let there be a set V and a set M. Consider the equivalence relation

α: = {((x, y), (y, x)) £ V ² x V ² ; with x, ye Vj V ² XV ²

with the equivalence classes

[x, y]: = {(x, y), (y, x)}, for all x, y £ V.

With an illustration

u: M → V ² / α = {[x, y]; x, yev}

is the name of the tuple

(V, M, u)

undirected graph with set of vertices (set of nodes) V, set of edges M and incidence mapping u.

FIG. 7 a shows a directed graph 700 and FIG. 7 b shows an undirected graph 701.

Definition 2 (terminated edges, initiated edges)

Let (v, E, g) be a directed graph and ve V. Then let ^ term ( ^v ) be the set of edges terminated by v, ie

^E term ( ^v ) ■ = E; g ⁺ (e) = v),

and E- _Ln it ( ^v ) the set of edges initiated by v, ie

Definition 3 (path in a directed graph)

Let (V, E, g) be a directed graph, K E.

(I)

Define for a, b e V and n e N

(k _n ) = b,

T (a, b) ..., n - 1,

as the set of all paths from a to b of length n with edges K (^ (a, b) = {} if no such path exists).

(G)

Define for a, b e V

neN

than the set of all paths from a to b with edges from K.

Definition 4 (directional tree)

Let (V, E, g) be a directed graph, V ≠ O. (V, E, g) is called directed tree, if there is a we V such that | r _E (w, v) | = 1, for all ve V \ {w}

and for all K C E, K ≠ E

| l ^~ (w, v) | = 0, for at least one v ε V \ (w).

That means there is exactly one path from w to every corner v ≠ w and the amount of edges cannot be reduced. The unique corner w is called the root of the directed tree.

The second condition in the above definition 4 guarantees the uniqueness of the root, which would not otherwise exist, and prevents the existence of "superfluous" edges in the tree.

Figure 8 shows an example of a directed tree 800 as part of the directed graph outlined in Figure 7a.

Lemma 5 (properties of a directed tree)

Let (v, E, g) be a directed tree. Then for all a, b ε V

| r _E (a, b) | + | r _E (b, a) | <I.

Definition 6 (path length, throughput)

Let (v, E, g) be a directed tree with root w 6 V. Define

(I)

For each v ε V \ {w}, let YE ( ^V ) ^G Γ _E (W, V) be the unique path from w to v, ie

T _E (w, v) = {γ _E (v)}. (ü)

For each v ε V \ {w} there is an n ε N with

{YE ( ^V ) I = ^Γ E ( ^W < ^V ) = ^r E ( ^w 'v).

Define | γ _E ( ^v ) | "• = ^na l ^s path length of the path γ _E (v).

(Iii)

Define for | v | <∞ and all v ε V

d _E (v): = 1 + | {z ε V; T _E (v, z) ≠ {}} ε N

as the throughput of the node v.

Definition 7 (branch)

Let (v, E, g) be a directed tree. Define v ε V for all

V _E (v): = {v} {z ε V; T _E (v, z) ≠ {}}

as branch of the knot v.

The following lemma applies:

Lemma 8 (thickness of the branch)

Let (v, E, g) be a directed tree and v ε V. Then applies

d _E (v) = | v _E (v) | , The overall network of the imaging system 300, including the portal processor, is shown below as a graph. In order to model that existing connections between two nodes are always permeable in two directions, which symbolizes bidirectional communication, an undirected graph is first considered. An equivalent directed graph is then derived to determine the routing.

Definition 9 (display graph)

Let (v, M, u) be an undirected graph with

(I)

(G)

u injective (i.e. no triangles)

(Iii)

U (E) n {[x, x]; x ε V} = {} (i.e. loop free)

(Iv)

w ε V is an excellent knot and hot portal (knot). Let (v, E, g) be the directed graph for which the following applies: For every m ε M consider new elements m ^~ and m such that

E: = | m ^~ ; me Mj U | m ⁺ ; m ε M], | E | = 2 | M | ,

Choose the map g such that

u (m) = jg (m ^~ ], g (m If, for all m ε M.

Also applies

(V)

r _E (w, v) ≠ {} for all v ε V \ {w} (i.e. contiguous),

is the name of (v, E, g) a display unit graph, hereinafter also referred to as a display graph.

A corresponding undirected graph 900 (cf. FIG. 9a) and the directional pixel arrangement graph 901 (FIG. 9b) that is equivalent thereto are shown by way of example in FIGS. 9a and 9b.

According to this embodiment, a hexagonal 4x4

Pixel field selected with a defect. Definition 9 above is general. The networks considered have further restrictive properties, but are only mentioned briefly here: • With the exception of the portal node 902, the number of

Edges to which a node 903 can belong as an initial (terminating) corner are limited by a number q ε N. So far, q = 4 (orthogonal network) and q = 6 (hexagonal network) have been considered. The directed graph 901 is generally a flat graph or a graph that can be smoothed (extensions are conceivable in which this only applies to the sub-graph, which does not contain the portal node 902 if the feed lines 904 are not fed in at the edge of the pixel arrangement 100).

For the further explanations, it makes sense to mark, in addition to the portal node 902, those nodes 903 which have a direct connection to the portal node 902. As described above, these nodes are referred to as initiator nodes 903, that is to say they represent the reference positions to which the initiator pixel processors of the pixel arrangement are assigned. The edges from the portal node 902 to the introduction node 903 are referred to below as feed lines 904 and the edges 905 between pixel processors as network connections.

Definition 10 (supply lines, network connections, initiator nodes)

Let (v, E, g) be a display graph with portal node w. The amount of supply lines is then defined by

^E port: = p ε E; g ^~ (e) = w)

and the amount of network connections through

^E net ^{: =} | ^{ee E} '' g ^~ ( ^e ) ≠ w Λ g ⁺ (e) ≠ w).

The amount of the initiator nodes is defined by

^v port ^{: =} l ^E ρort) -

Furthermore, the problem is considered that each node of a pixel arrangement graph from the portal node an electronic message is to be transmitted within a time frame (within a refresh rate).

If this happens, as this problem suggests, on fixed paths and paths that have separated do not cross again, this means that a directed tree should be chosen as the sub-graph of the pixel arrangement graph. This directed graph, which is also called the routing tree, then clearly defines the paths of the information flow, but not the dynamics of the information flow.

The routing tree is not unique; in general the amount of all possible trees is unmanageable.

Definition 11 (permissible tree quantity, permissible edge quantity)

Let (v, E, g) be a display graph with portal nodes w ε V. The set of all permitted directed trees in (v, E, g) is defined as

B: = {(v, K, g | κ); with K c: E and (v, K, g | κ) a directed tree with root w}.

The set of all permissible edge sets with respect to (v, E, g) is then defined as

K: = {KCE; (v, K, g | _κ ) ε ß}.

An exemplary permissible tree 1000 is shown in FIG. 10 with the corresponding routing routes with the portal node 1001 as the root node of the directed tree 1000. Based on Definition 10, the following terms are introduced:

Definition 12 (supply lines, network connections)

Let (v, E, g) be a display graph with portal node w and let K ε K. The amount of supply lines in K is then defined by

Kport ^{: _ E} Port ^{n κ}

The amount of network connections through

K _net : = ^E net ^ ^κ •

A number of criteria are listed below for evaluating trees:

Definition 13 (tree ratings)

Let (v, E, g) be a display graph with portal nodes w ε V and the set K of the permissible edge sets.

(I)

Defined for all v ε V \ {w}

1min (v) == ™ infγ _κ (v) |} KεK

the distance of the node v from the root w in the display graph. (ü)

Defined for all K ε K.

L (K): = max γ _κ (v) |} vε v \ {w}

the maximum distance in the tree defined by K (v, K, g | κ).

^L min ^{: =} min {L (k)} KK

is then the maximum distance in the display graph.

(iü)

Defined for all K ε K.

D (K): = max {d _κ (v)} vεv \ {w}

the maximum throughput in the tree defined by K (v, K, g | κ)

Dmin == min {D (κ)} Kε K

is then the maximum throughput in the display graph.

At least the following problems can be considered when selecting the "best" trees or edge quantities:

(I)

Number of trees, the nodes of which are at a minimum distance from the root: O _λ : = {K ε κ, - | γ _κ (v) | = l _m i _n (v) for all v ε V \ {w}},

(G)

Amount of trees whose maximum distance is minimal

O ₂ : = {K ε K; L (K) = L _min },

(Iii)

Number of trees whose maximum throughput is minimal:

O ₃ : = {K ε K; D (K) = D _min }.

It is easy to see that O] _ c O ₂ .

If O2 π O3 ≠ {} applies, then all trees are from O ₂ π O3

Minimizer of the functions L and K and particularly suitable as a routing tree.

If O2 π O3 ≠ {} does not apply, relaxed problems are necessary.

(Iv)

Number of trees whose maximum distance is greater than minimum by a ε N _Q :

Of: = {K ε K; L (K) <L _min + a}

(V) Number of trees whose maximum throughput is greater than minimum by b ε N _Q :

θ |? : = {K ε K; D (K) <D _min + b}.

For a suitable choice of a, b e NQ, O? πOr ≠ {} be possible.

The problem can also be understood as a multi-criteria combinatorial optimization problem with two target functions.

For the display unit graph in accordance with FIG. 9b, the routing tree 1000 in accordance with FIG. 10 is certainly not optimal, and specifically not in accordance with any of the above criteria. The tree 1100 according to FIG. 11, on the other hand, is even in 0] _ cut with O3.

It was explained above how the paths of the information flow in the display unit network can be determined by selecting a routing tree from a permissible number of trees. In order to supply the display unit node with the information necessary for image construction, an electronic message is transmitted to each node from the portal node along these paths. A parallel transmission of all electronic messages is generally not possible, since certain capacities, how many messages can be transmitted over an edge in a time cycle and how many messages can be temporarily stored in a node (queue), must not be exceeded. A temporal sequence (dynamics) of the information flow should therefore be determined.

In the following (V, E, g) be a display unit graph with portal node w. Let r: = | v | - 1 and V = {VQ, V _] _, ... v _r }, VQ = w. If K ε K is also specified, then certain "Total" routing matrices τ and then certain "single" routing matrices σ- ^, 1 = 1, ..., r, are introduced.

Τ will contain the information on how many electronic messages are to be transmitted over the individual edges from K in the individual time cycles. Conditions at τ are formulated in such a way that the capacities are maintained and in the end there is an electronic message in each node. A distinction is not yet made in τ between different messages (i.e. the single pixel data). How a special single pixel data is routed to the respective target pixel is not yet immediately apparent from τ. However, certain "single" routing matrices σ - * -, 1 = 1, ..., r, can be derived from τ, which exactly this routing of

Describe single pixel data for the target pixels V _] _, 1 = 1, ... r. The "single" routing matrices α ^, 1 = 1, ... r are not necessarily unambiguous, but the evaluation of the routing based on the routing duration essentially depends only on τ. In the following, routing is therefore regarded as already given by τ.

Definition 14 (routing mapping, routing matrix)

Let K = {ki, ..., k _r } ε K (note: | κ | = | v | - 1). Let ^c port ' ^c net' ^EN - ^E i ^ne (cp _θr t ;, c _ne t, q) routing mapping or matrix over the tree determined by K (v, K, g | κ) is a matrix

τ = (TH). ε Nη ' ^r , n ε N, ^\ Jι = l, ..., nuj = l, ..., r

with the following characteristics

(I) τ-H ≤ Cp _θr t for all e {l, ..., r} with kj e Kp _θrt and all i ε {l, ..., n}, and TH <c _ne t for all j ε {l , ..., r} with k _j ε K _ne t and all i ε {l, ..., n},

(G)

for all v ε V \ {w} and l ≤ m ≤ n

Σ Σ τi _j - Σ Σ τi _j > 0, l≤i≤m-1 l≤j≤r, l≤i≤ml≤j≤r, ^k j ^eK term ( ^v ) ^k j ^eK init (v)

(Iii)

for all v e V \ {w} and l ≤ m ≤ n

L≤

(Iv)

for all v ε V \ {w}

∑ ∑ τij - ∑ ∑ ^ j = 1. l≤i≤nl≤j≤r, l≤i≤nl≤j≤r, kjeKterm (v) kjεκ _ini t (v)

^c _p ort means capacity of the supply lines, c _ne t means capacity of the network connections and q means maximum queue length.

τ: = n is called routing duration. The set of all (c _por t, c _ne t, q) - routing matrices over (v, K, g | κ) become with

9t ^c port ' ^c net'Q- ()

designated .

The extension compared to the previously considered routing trees consists primarily in the fact that τ also contains a temporal component.

The matrix entry τij, i e {1, ... n} j ε {l, ... r} states that messages are transmitted over the edge kj in the i-th time cycle τi.

Condition (i) ensures compliance with specified supply capacities and network capacities.

Condition (ii) ensures the necessary causality in the network. Messages can only be forwarded from a node if they have been sent to this node beforehand (i.e. at least one time clock earlier).

Condition (iii) takes into account space constraints in the nodes.

Finally, according to condition (iv), exactly one message lies in the node after n time units.

The routing matrix, together with the routing tree, thus specifies a routing method with an indication of the chronological sequence of the individual steps, which simultaneously supplies the network with messages.

It is defined: Definition 15 (routing)

Let Cp _θr t, c _ne t, qe N. A (Cp _θr ^, Cnet 'q) routing is a tuple (K, τ) consisting of a permissible edge length

K = {i, ..., k _r } ε K and a routing matrix τ e R _c . _c g (κ). The set of all routings is calculated with R _c , _c . designated g.

How the dynamic routing results for each individual node is shown below. To do this, determine matrices σ ε {θ, l} ^{n, r} , 1 = 1, ... r, according to the following algorithm:

τ °: = τ; for 1 = 1, ..., r: {σ ¹ : = 0 ⁿ ' ^r ε {0, l} ⁿ '^r; let (kp ₁ , ..., kp], z ε N, the path from w to V] _; iz + 1: = n + 1; for y: = z, ..., 1 descending:

{iy: = max- ie {l, i _{y + 1} - l}:> 0

OT: = 1; lyPy

} It is easy to show that the algorithm is well defined and that τ ^r = 0 ^{n, r} . Hence is

Σ = τ l≤l≤r

It is

L≤

for all for all 1, 1 ε {l, ..., r}. A matrix entry σ. • = 1 means that the message is forwarded to V_ in the i th time cycle via the edge kj.

As proof of the above well-definedness of the algorithm, two lemmas are listed:

Lemma 16 (well definedness of σ)

Let 1 e {l, ..., r}. If τ e NQ ' ^Γ fulfills condition (ii) from definition 14 for all v ε V \ {w} and condition (iv) from definition 14 for v: = ej_, then σ can be selected according to the algorithm.

Lemma 17 (properties of τ) 1-1 Let 1 e {l, ..., r}. Τ e N _Q ' ^{Γ meets} the requirements

1 of Lemma 16 and if σ is chosen according to the above algorithm, then τ also fulfills the requirements of Lemma 16.

Definition 18 (routing matrix for individual nodes)

Let c _port , c _net , q ε N. Let (K, τ) ε ^R c _port , c _net , q ^and the matrices σ, 1 = 1, ..., r, chosen according to the above algorithm. Then they are called σ, 1 = 1, ..., r,

Routing matrices for the nodes V] _, 1 = 1, ..., r regarding (K, τ).

We often reverse the construction of matrices τ and σ, 1 = 1, ..., r. We determine matrices σ, 1 = 1, ..., r, by specifying the time sequence in which the message is forwarded to V_ via the path Υκ ( ^v l) .T then results from

τ: = ∑ σ ¹ . l≤l≤r

The time sequence of the routing to each individual node and thus the σ, 1 = 1, ..., r, are to be selected so that the capacities of edges and nodes are not exceeded, i.e. H. that τ fulfills points (i) and (iii) from definition 14.

In addition, criteria for a “cheap” and, if possible, “optimal” selection of routing methods are specified in a display unit graph. Routing is referred to below as optimal if it takes the shortest possible duration. In order to be able to put this into mathematical language, the following terms are introduced. Let (V, E, g) always be a display unit graph and, as before, be V = {V _Q , ■ • -V _r } with vg = w.

Definition 19 (minimum routing duration)

(I)

Let K = {ki, .. J _r } ε K and let C _pθr , c _ne t, q ε N. Then define

CPORT ^ net. τεR _Cport , _Cnet , _g (κ)

the minimum routing duration over the tree defined by K (v, K, g | κ) ■

(11)

Let Cp _θr c _ne , qe N. Then define

T ^cm p ⁱ o ⁿ rt ' ^c net _' q: =

the minimum routing duration in the display graph

Definition 20 (optimal routing)

(I)

Let K = {ki, .. Jc _r } e K and let Cp _θr t, c _net , qe N. Under an optimal routing matrix in the tree defined by K (v, K, g | κ) a routing matrix is understood from the following

quantity

(G)

Let C _θr t-, c _ne t, qe N. Optimal routing is understood to mean routing from the following set

(K, τ); K = {ki, ..., k _r } e K, τ ε Rc _port , c _net , q (κ)

_R mιn ^c port ' ^c net' ° - undlτl = T ^mιn ¹ 'port _' ^c net '<3

Choosing an optimal routing matrix for a previously defined routing tree in the sense of Definition 20 (i) is easy. It is explained in this section for the special cases c _{port and} c _net = 1 and c _port and c _ne t> 1.

Solving the optimization problem in definition 20 (ii) with free choice of the routing tree is considerably more difficult. The problem is usually too complex to solve exactly. For this reason, heuristic methods for its solution are explained below. Solving the optimization problem from Definition 20 (i) with a defined routing tree provides important strategies for the cheap choice of the routing tree.

The special case is first explained, in which c _por t = ^C net = ¹ - Let qe N be arbitrary and K e K. Without restriction of generality, p _θr t = Ep _0rt (otherwise consider u ε Kp _θr t) not as an introductory node, so set V _port : = g ⁺ (κ _pθ rt) ⁾ •

Because of C _pθr t = 1 it is easy to consider that

^ ^C p ^ or xt-'c ^C ne-t-σg ^ ^≥ ve ^m V ^a _P ^x _place ^d κW ⁼ ° ( ^R )

There is even equality. Be there

n: = max djς (v) = D (K). veV _port

The idea of the following routing is that an electronic message is sent into the

Introductory node arrives and in the following time intervals is gradually forwarded to its respective target node, that is to say the target pixel processor. The messages to the nodes further away are fed in first, later the messages to the nodes located close to the portal node, that is to say the pixel processor. A corresponding routing is shown in FIGS. 12 a to 12 i for the case C _p0r = c _ne = 1. The small squares each symbolize an electronic message 1201, which is routed via the portal node 1202 to the initiating pixel processors 1203 in the pixel arrangement 100.

Consider u 6 Vp _θr t and set d: = dκ (u) = | (U) | , It is

V _jζ (u) = (vg., ... g,] with v _q - = u arranged such that

^r κ (v _qi , v _q . = {} (l; for i>. This is especially true if

YK ( ^v qi) ^≥ | Yκ | v

<2

for i> j. Now let 1 ε {l, ..., d} be arbitrary and be (kp.,, ..., kp j, z ε N, the path from w to Vg-,.

Then set for all i ε {l, ..., n} and each {l, ... r}

_gι _ fl if 1 + (d - 1) ≤ i ≤ z + (d - 1) and Pi- (dl) = D ϊj ^' | 0 otherwise.

To show that σ ^ l defines a routing matrix for Vg, it suffices to show that

z + (d - l) ≤ n,

because then the n clock cycles are sufficient to route the message according to our construction from σ ^g l to its destination Vg. Because of (1) 1> z and thus

z + (d-l) ≤ d ≤ n

and with that it is shown.

According to the above considerations,

Consideration of all initiator nodes finally determine the σ for all 1 ε {l, ..., r}. As usual, is formed

τ: = ∑ σ ¹ . 1 = 1 It is easy to see that τ then really defines (l, l, q) routing via (v, K, g | κ) for any qe N and according to the above

Considerations is optimal. So it applies

^ .c, c » ^{= maX} d _κ (v) = D (κ). port ' ^c net <°: v _{€ Vport}

12a shows the initial state for which all messages 1201 are stored in the portal node 1202. After a first clock cycle, the first two messages 1201 are fed to the introductory pixel processors 1203, that is to say the pixel processors of the pixel arrangement 100, via which the information about the pixel arrangement can be supplied to the respective pixel processors, and stored there temporarily (cf. Fig.12b). After a further time step (cf. FIG. 12c), the first two messages have already been transmitted to first inner nodes 1204 of the pixel arrangement and two further messages 1201 have been fed to the initiating pixel processors 1203. After a further time step in each case, the respective electronic message 1201 has always been transmitted one pixel processor at a time and two new messages 1201 have been fed into the pixel arrangement 100, in other words, fed to the introductory pixel processors 1203. Figures l2d, l2e, l2f, 12g, 12h, 12i show the successive progress of the transmission of the messages up to their respective target pixel processor after each time cycle.

As a possible advantageous strategy for the selection of an optimal routing with free choice of the routing tree in the sense of definition 20 (ii) can be stated:

Select the routing tree so that all initiating nodes have the same throughput (more precisely: differ by a maximum of 1) and set the routing matrix according to the considerations above. The second special case is briefly explained below, in which the following applies:

^c: = port = ^c net> ¹ > ° - ^{≥ c} -

Let K e K. Without restriction of generality apply again K _port = E _por .

In this case, it is more difficult to specify the minimum routing duration in advance. A routing matrix is thus developed that _defines an optimal (C _θr t, c _ne t, q) routing via (V, K, g | K). The minimum routing duration can finally be determined from it. The idea for this variant of routing is the same as that previously developed for the case c _pθ rt ^{= c} net ⁼ 1, except that in this case c = c _or t = c _ne t messages are always simultaneously introduced into an initiating node in order to from there to be forwarded to the most distant, not yet notified nodes. Such routing is again outlined in FIGS. 13a to 13f.

First of all

n: = max djζ (v) ^veV port

Let ue Vp _θr t and let d: = djς () = | Vjζ (u) | , Let ^v κ ( ^u ) ⁼ _\ ^v qι _' • • •' ^v q _< g) roit ^v qι = so that

d - 1 if i> j. Let 1 ε {l, ..., d} and d: = ie the

next smaller integer to Be (k _pι , ..., k _Pz j the path from w to Vg-. Now set for all i ε {l, ..., n} and j ε {1, ..., r}

if 1 + d≤i≤z + d and

^< otherwise.

As before, determine σ for all 1 ε {l, ..., r} and set

= 1

1 = 1

Now delete all those lines in τ that are equal to 0, i.e. H. put

n: = mm'jn e N; ] = 0 for all ή <i ≤ n and j = 1,

and

τ: = (τij) i = l, ..., n- j = l, ..., r

It can be shown that τ is an optimal \ Cp _θr , c _ne qj routing via (v, K, g | κ) defined for any q> c. Furthermore, applies

and

L (κ) ≤ n How big n actually is depends on the concrete

Structure of the branches of the lead-in nodes, but can be easily calculated. For this purpose, for each u ε V _pθr t

Calculates the number of clock cycles n _u that is required to route all messages to the nodes of the branch of u. Vκ (u) and d are as above. Then:

This results in the routing duration n as

n = max n _u uεvport

As an alternative strategy for the selection of an optimal routing with free choice of the routing tree in the sense of definition 20 (ii) there results:

Choose the routing tree in such a way that all initiating nodes have the same throughput as possible and the tree in the branches of the initiating nodes is "sufficiently branched" so that

D (K) - n comes as close as possible. Set the routing c matrix according to the considerations above.

A "sufficiently wide branch" is clearly present when the following applies to all initiating nodes: look at the branch of the initiating node, arrange the associated nodes according to the ascending path length. Then the path lengths of the nodes should only increase every c nodes by the value 1, i.e. c nodes of path length 2, c nodes of path length 3, ....

If the capacities of the respective nodes and the supply lines are low, it is more important to ensure an even one Pay attention to throughput in the initiating node, since in this case the throughput through the initiating node is usually the decisive factor for limiting the routing duration downwards. In this case, the introductory nodes represent a constriction of the tree. At higher ones

On the other hand, it is more important for capacities to ensure that there are enough branches in the tree and therefore short path lengths. Here it is usually the path lengths that limit the routing duration downwards. On the other hand, very high capacities are no longer sensible, since the hexagonal network limits the number of branches and certain minimum path lengths from the topology of the network, that is, the topology of the meshing or coupling of the pixel processors are specified in the processor arrangement.

Exemplary embodiments of the methods for self-organization of the pixel processors in the pixel arrangement are explained below.

According to the exemplary embodiments, the following situation is assumed:

• The topology of the network, that is to say the arrangement of the pixel processors in the processor arrangement, is unknown to the central external unit, that is to say the portal processor.

• The pixel processors are meshed with each other through bidirectional connections.

• Direct communication takes place only between neighboring pixel processors that are immediately adjacent to each other.

• The basis of the communication is the exchange of electronic messages, as shown for example in Fig. 14.

• Every contact with other components for self-organization (position determination, creation of routing tables, etc.) and for image creation is handled by different messages. Fig. 14 shows a first pixel processor 1401 with a hexagonal shape and a second pixel processor 1402, also in a hexagonal shape. The first pixel processor 1401 has six bidirectional communication interfaces 1403, which is indicated by a double arrow in FIG. 14. The second processor unit 1402 also has six bidirectional communication interfaces 1404. The first processor unit 1401 and the second processor unit 1402 are via a feed line 1405, that is to say an electrically conductive connection, which of course is also an optical one

Communication connection can be configured or coupled to one another as a radio link such that both a first message 1406 can be transmitted from the first processor unit 1401 to the second processor unit 1402 and a second message 1407 from the second processor unit 1402 to the first processor unit 1401.

According to the present exemplary embodiments, in the error-free state, all pixel processors 1401, 1402 are fully meshed with one another via the corresponding feed lines and the bidirectional communication interfaces.

The above problem is solved by

Self-organization based on local message exchange between two immediately adjacent processor units 1401, 1402 solved.

The self-organization process thus consists of distributed uniform algorithms that transmit these electronic messages via their communication interfaces.

In the course of the method, the processor units 1401, 1402 learn their alignment and their level position within the processor arrangement, as well as the distance between them Processor unit to the portal processor, generally to a reference position. The reference position can also be the position of a processor unit, which is located at the point of introduction of the pixel arrangement. In further steps, local routing paths between the individual processor units and the portal processor are shaped. The algorithms for selecting the routing routes are designed in such a way that the routing duration is kept to a minimum, while the information flow is uniform. The self-organization also defines the algorithm for distributing the information when using the pixel arrangement in the context of the image construction, that is to say in the context of the representation of a digitized image on the pixel arrangement. Due to the special conception of the method, the shape of the pixel arrangement and thus also the individual components that have failed are irrelevant, with which a high fault tolerance is achieved according to the invention.

The entire method has a combination of the following sub-methods: • Uniform sub-algorithms for message processing, which are executed by the pixel processors,

The control algorithm of the portal processor,

• a message catalog, which represents the interface of the sub-algorithms.

In the following, a hexagonal meshing of the pixel processors within the pixel arrangement 100 is assumed without restricting the generality.

However, the transfer of the algorithms to the orthogonal case or other flat meshes is, according to the invention, completely analogous to the illustration given below.

According to a communication layer model, functions lying below the functions required according to the invention, for example ping messages, securing the transmission by means of checksums, acknowledgment of receipt, New requests for defective messages etc. are not taken into account in the following. However, these can easily be implemented within the scope of the invention.

Generally applies to those described below

Method steps that each pixel processor creates a data record for each of its neighboring pixel processors on the basis of received messages, which data record the information obtained in a memory assigned to the respective processor.

In a first partial process, the pixel processors learn how to align them evenly.

Since all connections of the portal processor according to the above

Convention with the southwestern side of the corresponding lead-in pixel processors at the lead-in points, this can be used to generate coherence.

For this purpose, measurement coherence messages are sent, which contain as parameters the number of connections that the receiving connection is counterclockwise from the east, as defined above.

Each pixel processor is set as incoherent for initialization.

When a measurement coherence message 1501 is received (see FIG. 15), the processor unit 1500 receiving the measurement coherence message 1501 carries out the following steps:

1. If the processor unit 1500 is already coherent, the processing is ended.

2. The east direction is determined based on the message parameter and all connection names / connection numbers are aligned accordingly. 3. The processor unit 1500 is set as coherent.

4. Measurement coherence messages 1601, 1602, 1603, 1604, 1605, 1606 are sent out by processor unit 1500 over all connections, the parameters of which are selected such that the respective measurement coherence message 1601, 1602, 1603, 1604, 1605, 1606 receiving processor units 103 can align themselves correctly in the above manner (see FIG. 16)

The partial method for uniform alignment is started by the portal processor transmitting the measurement coherence message (2) with the parameter value 2 to the respective introductory pixel processors via its connections. The partial process terminates when the last processor unit has become coherent.

The number of times required to carry out the process corresponds to the maximum distance of a pixel processor from the portal processor. Until the last message communication "dies", one or two more clock cycles may be required.

In a further sub-process, the pixel processors determine electronic exchanges

Messages among themselves automatically position themselves within the pixel array.

Since the hexagonal field of the pixel processors within the pixel arrangement consists of staggered rows, the coordinate system according to this exemplary embodiment is selected such that the column numbers in the rows are alternately even or odd.

In this context, it should be pointed out that the coordinate system can be selected very canonically in the case of an orthogonal structure of the pixel arrangement. In the manner described above, the hexagonal field enables a processor to determine the positions of its neighboring pixel processors independently of the geometry of the pixel arrangement from its own position (i, j) with row i and column j.

The respective positions are shown in FIG. 17 for the processor unit 1500. As can be seen in Fig. 17, it has been agreed as a convention that the column numbers increase from west to east (left to right) and the line numbers increase from south to north (from bottom to top).

According to this, for position determination

Embodiment measuring position messages 1701, 1702,

1703, 704, 1705, 1706, which contain two parameters, namely the row number and the column number, the processor unit sending the measurement position message 1701, 1702, 1703, 1704, 1705, 1706 as accepted by it

Position of the processor unit receiving the respective message 1701, 1702, 1703, 1704, 1705, 1706.

For initialization, the position of each pixel processor is defined as (0.0). The process of determining location begins with each pixel processor once it has become coherent, as discussed above.

The measurement position messages 1701, 1702, 1703, 1704, 1705, 1706 are then sent over all connections, as shown in FIG.

On receipt of a measurement position message 1701, 1702, 1703,

1704, 1705, 1706 with row parameter z and column parameter s, the respective receiving processor unit carries out the following steps: 1. If z> i, where i represents your own line number, then i = z is set.

2. If s> j, where j is your own column number, then j = s is set.

3. If a change in one's own position (i, j) has resulted due to step 1 or step 2, then measurement position messages 1701, 1702, 1703, 1704, 1705, 1706 are sent over all connections, as in FIG. 17 shown.

The partial procedure is ended when there are no more changes in position.

18 shows an example of the processor arrangement 1800 with various defects, which has automatically determined the positions of the individual processors according to the procedure described above. According to this embodiment, both failed, i.e. faulty processors used as well as failed connections. This exemplary embodiment also serves in the further course of this description in two variants with a different number of initiating processor units for describing the further sub-methods.

The number of clock cycles required to carry out the process is limited by the maximum distance of a pixel processor from another pixel processor in the processor arrangement. Until the last message communication "dies", one or two more clock cycles may be required. Usually, however, depending on the geometry of the processor arrangement 1800, the partial method can usually be carried out even faster.

In this context it should be noted that the

Representation of hexagonal pixel images or orthogonal pixel images by the portal processor thus determined coordinate system of the processor arrangement 1800 is carried out. When routing routes are set up in later partial processes, the information that is now stored locally is transmitted to the portal processor, so that a corresponding mapping can take place in the portal processor.

In FIG. 18, the local position of the respective pixel processor 1801 within the processor arrangement 1800 is plotted in the form of a value group in the pixel arrangement for each pixel processor 1801.

In an additional partial method, the respective distance of a processor unit from the portal processor, that is to say the length of the path from the pixel processor to the portal processor (see also definition 6), generally the distance of a processor unit 1801 in the processor arrangement 1800 from a predetermined one Reference position.

To initialize this partial method, the distance between each processor unit 1801 is defined as "infinite". According to this exemplary embodiment, the distance between each pixel processor and the portal processor is defined as a value that is greater than a maximum value that can be assumed as a distance within the pixel arrangement.

Without restricting the generality, it is assumed that the steps of the sub-methods described above have already been carried out.

The process of determining the distance is then started by the portal processor by sending MessDistance (0) messages to the processor units at the introduction points of the processor arrangement 1800. When a MessDistance message with distance parameter a is received, the following steps are carried out by the respective processor unit receiving the MessDistance message:

1. If d ≥ a + 1, where d represents the own distance, then d = a + 1 is set.

2. If, due to step 1, there has been a change in your own distance d, then all

Connections MessDistance messages 1901, 1902, 1903, 1904, 1905, 1906 sent to the neighboring processor units (see Fig. 19). The respective MessDistance message 1901, 1902, 1903, 1904, 1905, 1906 contains as parameters the distance value that the processor unit 1500 determined in the previous step.

The partial procedure terminates when there are no more changes in distance.

20 and FIG. 21 show the processor arrangement 1800 according to a first exemplary embodiment and a processor arrangement 2100 according to a second exemplary embodiment, with all processor units 2001 in the bottom line 2002 of the processor arrangement in the processor arrangement 1800 according to the first exemplary embodiment. Arrangement 1800 are coupled to the portal processor via their southwest side 2003.

In the processor arrangement 2100 according to the second exemplary embodiment, the bottom line 2101 of the processor arrangement 2100 contains both processor units 2102 which are not coupled to the portal processor and processor units 2103 which communicate with the portal processor via their communication interfaces 2104 arranged on the south-west side are coupled. According to the second

Exemplary embodiment is every third processor unit in the bottom line 2101 over its lying on the southwest side Communication interface connected to the portal processor.

The number of time cycles required to carry out the process corresponds to the maximum distance one

Processor unit from the portal processor. Again, one or two more clock cycles may be required before the last message communication "dies".

In this context it should be noted that each

Processor unit can also store the distance of its direct neighboring processor units from the portal processor locally for later use based on the messages received.

Clearly, in this sub-method the own distance value of the processor unit is changed in an iterative process if the previously stored distance value is greater than the received distance value increased by a predetermined value in the respectively received message. In the event that a processor unit changes its own distance value, it generates a measurement distance message and sends it to neighboring processor units via all communication interfaces, the measurement distance message each containing the own distance as distance information or the distance value that the received processor unit from the Portal processor preferably has a value increased by a predetermined value compared to its own distance value, preferably a distance value which is increased by the value "1".

The sub-procedure for regular backward organization is described below.

In order to be able to carry out the following method steps, it is necessary that the distance of a pixel processor from a respective reference position has been determined and is thus known and is preferably stored as the respective distance information in the memory of the respective processor.

In the sub-method described below, the connections between the respective processor units are hereinafter referred to as channels.

The sets of processor units with the portal processor as the root node and the channels as the edges between the respective processor units form a tree. This tree is used for the subsequent routing as described above in connection with the graph-theoretical basics.

The channels are determined in a regular manner so that each processor unit is connected to the portal node in the shortest possible way.

For initialization, each pixel processor is 1500

The process of organization is started across all connections by the portal processor by sending MessOrganize messages 2201, 2202, 2203, 2204, 2205, 2206, which have no parameters.

When a MessOrganize message 2201, 2202, 2203, 2204, 2205, 2206 is received, the following steps are carried out by the processor unit receiving the message:

1. If the processor unit is already organized, the processing is ended.

2. Across all connections except the

Receive connection, i.e. the connection over which the MessOrganize message 2201, 2202, 2203, 2204, 2205, 2206 additional measurement organize messages have been received (see Fig. 22).

3. On the basis of the previously determined distance information, the processor unit determines a neighboring processor unit which is at a smaller distance than it itself from the reference position, and thus preferably from the portal processor. The neighboring processor unit is selected and defined as the "predecessor", which is the first to have a shorter distance than the processor unit itself in the order defined in FIGS. 23 and 24. The connection between the processor unit and its "predecessor" becomes special excellent and called "channel". The set of pixel processors with the portal processor as nodes and the channels as edges then form a tree. In the case of a regular display without errors, this procedure leads to a "zigzag pattern" when defining the channels.

4. A "MessChannel" message is sent to the "predecessor" and the processor unit is set as organized.

When a MessChannel message is received, the processor that receives the Mess Channel message defines the sender as "successor". The is accordingly

Connection between the processor unit and the "successor" one channel.

The partial process terminates after all processor units have organized themselves in this way.

25 shows an example of an organized processor unit 2500, the connections 2501, which are channels, being optically highlighted. When the display is used, the pixel information, for example the image information to be displayed, is routed via the channels 2501. Fig. 26 and Fig. 27 show examples of the processor arrangement 1800 and 2100 after automatic organization, as described above.

The number of times required to carry out the partial method for rearward-facing self-organization corresponds to the maximum distance of a pixel processor from the portal processor. In this case, one or two more clock cycles may be required until the last message communication "dies".

The regular backward organization leads to well balanced trees in the case of error-free rectangular displays, i.e. display units.

Since all processor units within the processor arrangement 1800, 2100 are each connected to the portal by a shortest route, this algorithm determines an element of the “optimal amount” defined above. In the case of horizontal cracks 2600, 2700, as in FIGS and FIG. 27, however, the procedure described above leads to the fact that the portions of the processor arrangement 1800, 2100 shaded by the crack are essentially supplied by a single supply line from the portal to the display Organization described.

The throughput of a pixel processor is of considerable importance for setting up routing tables.

The throughput is the number of pixel information that must be processed or passed on by this processor in order to build up an image.

The mathematical definition of throughput is given in Definition 6 above. This number is identical to the number of pixel information received via the input channel.

To carry out the following sub-method steps, a tree structure must have been organized in the processor arrangement 1800, 2100, for example by means of channels, as described above.

The partial process is carried out by the portal processor

Sending measurement count notes messages that have no parameters started over all connections to the respective initiating processor units.

When an incoming MessCountNodes message 2801 is received via the input channel, the processor unit receiving the MessCountNodes message performs the following steps:

1. MessCountNodes messages 2802 are again sent over all output channels of the processor unit receiving the MessCountNodes message, as shown in FIG.

2. All neighboring processor units which are connected to one another via output channels are marked with a throughput with the throughput value "0".

3. If there are no output channels, the own throughput is set to the through value "1" and a MessNodesSize message 2901 is sent to the respective predecessor processor unit via the input channel. 29 shows for a processor unit 1500 two incoming MessNodesSize messages, a first incoming MessNodesSize message 2901 which contains the value di and a second incoming MessNodesSize message 2902 with the parameter d ₂ . at

Receiving a MessNodesSize message with throughput parameter d via an output channel from which the MessNodesSize Processor receiving the message performed the following steps:

1. The neighboring processor unit from which the MessNodesSize message 2901, 2902 was received is with the

Throughput parameters of the MessNodesSize message marked.

2. If at least one output channel with a throughput with the throughput value. "0" is marked, the processing is ended.

3. If all output channels are marked with a throughput value> 0, the own throughput d is calculated as the sum of all output throughputs +1.

4. An additional MessNodesSize message 2903 is generated by the processor unit and sent with the throughput value d, which results, according to the following rule: d = di + d ₂ +1 according to the exemplary embodiment described above, via the respective input channel.

The partial procedure terminates after the portal processor has received a MessNodesSize message over all connections.

The number of time cycles required to carry out the partial method corresponds to twice the maximum distance of a pixel processor from the portal processor. In this case, one or two more clock cycles may be required until the last message communication "dies".

30 and 31 show examples of the processor arrangement 1800 and 2100, respectively, after the throughputs have been determined automatically in the manner described above. The respective throughput value is specified in the respective pixel processors. These examples show that the throughputs of those single-processor units which have to supply the area of the processor arrangement 1800 or 2100 shaded by the respective horizontal crack 2600, 2700 are very high.

Therefore, an alternative is described below

Organizational method described, which can react even more flexibly to errors, that is, defects and irregular forms of a processor arrangement 1800, 2100.

In order to achieve a throughput that is as uniform as possible, there is a heuristic approach to selecting a routing tree by successively sending so-called

MessToken messages, which "occupy places" in the processor arrangement 1800, 2100.

In analogy to a gradual coloring of the processor arrangement 1800, 2100 using color streams, each

Delivery point is loaded with tokens of a different "color". In this way, the processor arrangement 1800, 2100 is divided into color regions, each of which is supplied by the portal node via an initiating processor unit.

In other words, this means that a "color" or an individual marking is provided for each processor unit supplied by a respective initiating processor unit.

Furthermore, the term "color" is used for a clearer illustration and accordingly an area marked with the same marking is used as the "color region".

The following heuristic distribution strategies are used: • A token weight determines how much the distance to the portal node can be increased due to the coloring.

• Once colored pixels, that is to say processor units, remain colored, in other words remain marked.

• The processor unit sending the token becomes the “predecessor” and the connection to it becomes the channel. Furthermore, the colored pixel, that is to say the marked process unit, “.only.” Still accepts tokens from the respective predecessor.

• Tokens are preferably sent via channels.

After the processor arrangement 1800, 2100 has been completely colored, a reorganization within the colored areas is necessary, since the partial process does not result in optimal “meandering channels” 3501, as shown for example in FIG.

First, the sub-procedures for processing the messages used for token assignment are described in the following subsections.

The distance determination within a color region is largely identical to the general distance determination to a reference position described above.

The color distance determines the length of the shortest path from a processor unit to the portal processor, whereby all processor units of the path must belong to the same color region.

For initialization, the color distance of each processor unit is defined as infinite and its color as undefined. According to this exemplary embodiment, the distance between each pixel processor and the portal processor is defined as a value which is greater than a maximum value which is assumed to be a distance within the pixel arrangement can. The processor unit also marks its neighboring processor units as undefined colored with an infinite color difference.

When a MessColDistance message with color c and color distance parameter a is received, the following steps are carried out by the respective processor unit receiving the MessColDistance message:

1. The one sending the MessColDistance message

Processor unit is marked with the color c and the color distance a.

2. If the color c does not match the own color f, that is to say the color f of the processor unit receiving the MessColDistance message, the processing is ended.

3. The own color difference d is set as the minimum of the color differences of neighbors marked in the same color plus the value 1.

4. If there is a change in the own color distance d as a result of step 3, then MessColDistance messages 3201, 3202, 3203, 3204, 3205, 3206 with the parameters (f, d), that is to say in other words with, are sent over all connections your own color difference d and your own color f (see Fig. 32).

To block neighboring processor units from received token messages, the invention uses

MessBlockToken messages used, that is, after receiving such a MessBlockToken message, no more tokens may be sent to these blocked neighboring processor units.

At the same time, the color and color difference are communicated as in the MessColDistance message. For initialization, all neighboring processor units of a processor unit are set as unblocked.

When an incoming MessBlockToken message 3301 with the color c and the color distance parameter a is received as the message parameter, the processor unit receiving the MessBlockToken message performs the following steps:

1. The processor unit sending the MessBlockToken message is set as blocked and marked with the color c and the color difference a.

2. If the color c does not match the own color f, that is to say the color of the processor unit receiving the measurement block token message, the processing is continued with step 5 described further.

3. The own color difference d is set as the minimum of the color differences of neighboring processor units marked in the same color plus the value 1.

4. If there is a change in your own color difference d due to step 3, the

Processor unit MessColDistance messages 3201, 3202, 3203, 3204, 3205, 3206 sent over all connections with parameters (f, d), as shown in Fig. 32.

5. If there is an input channel and all neighboring processor units are set as blocked, a measurement block token message 3302 with the parameters (f, d) is generated and sent via the input channel, as shown in FIG. 33.

For coloring, that is, for marking processor units and thus for defining color regions, that is, for marked areas within the processor arrangement 1800, 2100, so-called measurement token messages are used according to the invention.

When processing measurement token messages, a distinction must be made as to whether the processor unit was still undyed or already colored by a token.

Upon receipt of an incoming MessToken message 3401 with ... weight g and color f as message parameters, the following steps are carried out by an undyed processor unit which receives the MessToken message 3401:

1. The potential own color distance pd is set as the minimum of the color distances of neighboring processor units colored with the color f + 1.

2. If the weight g ≤ pd - a, where a is the distance (not the color difference!) Of the processor unit from that

If the portal processor is active, a measuring block token message is sent to the processor unit sending the MessToken message 3401 and the processing is ended (the spread of the tokens is therefore restricted by a relaxed distance).

3. The processor unit sending the MessBlockToken message 3401 is set as blocked. Your own color is set as f and your own color difference as pd.

4. The processor unit sending the measurement token message 3401 is sent a measurement channel message and the processor unit is set as organized. This defines the input channel.

5. Measurement block token messages are sent over all connections with the exception of the input channel of the processor unit 1500 3402, 3403, 3404, 3405, 3406, as shown in Fig. 34, to prevent a token assignment from there.

6. If all neighboring processor units are set as blocked, then a measurement block token message 3402,

3403, 3404, 3405, 3406 sent over the input channel, as shown in Fig. 33.

On the other hand, when a measurement token message with the weight g and the color f is received via the input channel, a previously colored processor unit proceeds differently.

Consider an order R = (SE, SW, E, W, NE, NW) for an even column number, which corresponds to an order R of (Southeast, Southwest, East, West, Northeast, Northwest) and an order for an odd column number R = (SW, SE, W, E, NW, NE), which corresponds to an order (southwest, southeast, west, east, northwest, northeast) and performs the following process steps:

1. If the received measurement token message did not come through the input channel or the color f does not match the own color, the processing is ended.

2. If, according to the order R, it is an unblocked one

Output channel, a MessToken message with the parameters (g, f) is sent via this output channel, i.e. the token is passed on and processing is ended.

3. If there is an unblocked connection in the order R, a MessToken message (g, f) is sent via this connection and the processing is ended.

4. A MessBlockToken message is sent via the input channel because the token cannot be passed on. Since the channels cannot be optimally set when selecting the color regions due to the partial method described above, as shown in Fig. 35, these channels are deleted with MessDeleteChannels messages and set again later. To terminate the partial process, the message is provided with a parameter "sta p", the value of which is not identical to the correspondingly stored parameter in the processor unit. In this context it should be noted that the portal processor uses a different parameter "stamp" for each reorganization.

When an incoming MessDeleteChannels message 3601 is received with the "stamp" parameter, the processor unit receiving the respective MessDeleteChannels message carries out the following steps:

1. If the own stamp parameter is identical to the received parameter value "stamp", the processing is ended.

2. Your own stamp parameter is set to the value in the MessDeleteChannels message "stamp".

3. All channels are deleted.

4. MessDeleteChannels messages 3602, 3603, 3604, 3605, 3606 are sent with the parameter “stamp” over all connections with the exception of the connection to the processor unit sending the MessDeleteChannels message, as shown in FIG. 36.

After deleting the old channels, new channels are set within a color region using MessColOrganize messages. The processing of incoming MessColOrganize messages 3701 and the sending of MessColOrganize messages 3702, 3703, 3704, .3705, 3706 is largely identical to the processing of MessOrganize messages, as described above.

One difference, however, is that the neighboring processor units under consideration have to be colored in the same way as the processing processor unit, and that it is not the distance but the color distance that is used as a criterion.

In order to carry out the partial method described above, all of the steps described up to the distance determination should have been carried out in the pixel array as explained above.

As above in the first embodiment, the connections are specifically labeled "channels".

In a first step, the portal processor sends a MessColDistance message 4001 (see FIG. 40) with the parameters (f, 0) with different color parameters f over all connections. All neighboring processor units thus mark the portal processor with a different color.

This ensures that an individual and unambiguous marking is carried out on the basis of each introductory processor unit.

In a second step, the portal processor sends successive measurement token messages with the parameters (g, f) with identical weight g ε NQ and different color parameters f over all connections in order to color all processor units of the processor arrangement 1800, 2100. The partial method terminates when measurement block token messages have arrived via all connections of the pixel processor, that is to say when the processor arrangement 1800, 2100 has been completely colored.

In this context, it should be noted that the entire processor arrangement 1800, 2100 can always be completely colored using this method.

FIG. 38 shows the processor arrangement 2100 in the event that it was colored with the weight g = 4 and in which the throughput was shown after the organization. As can be seen in comparison with Fig. 30, which was formed by means of regular backward organization, the tree is considerably better balanced.

However, due to the construction of this partial method, meandering paths 3801 are formed within the colored areas, so that the processor units are not connected to the portal processor by the shortest possible distance.

Therefore, in a third step, the portal processor sends a MessDeleteChannels message, as explained above, over all connections in order to delete the channels formed.

Immediately after this message, a MessColOrganize message is sent across all connections, creating new channels within the colored areas, which then represent the shortest connections.

The partial process terminates after all processor units have organized themselves in this way. The number of times required to carry out the processes corresponds to the maximum color distance of a pixel processor from the portal processor. Until the last died

In this case, too, message communication can be required one to two cycles more. The routing tree generated depends on the weight g, which is contained as a parameter in the respective measurement token message.

Fig. 39 shows the processor arrangement 1800 for after reorganization with weight g = 4 and the corresponding meandering paths 3901.

The weight g indicates how much the color difference one

The processor unit may be larger than the distance itself. The greater the weight g, the better balanced the tree that will be created, but the longer the paths in this tree are. For explanation, reference is made to FIG. 41, in which the processor arrangement 1800 after the formation of the meandering paths with the weight g = 0 and to FIG. 42, in which the processor arrangement 1800 after the formation of the meandering paths with the weight g = ∞ are shown.

The best choice of weight usually depends on the transport properties of the respective connections, i.e. how many messages can be sent over a connection per time cycle. The smaller this number is, the larger the weight will usually have to be.

Two methods for selecting a routing tree were previously described.

If a routing tree has been selected, i.e. if the corresponding channels have been selected, optimal routing for this tree can be determined in a very simple manner. The basics were explained in the description of the graph-theoretical basics. In a first step, all pixel processors, that is to say the processor units within the processor arrangement 1800, 2100, are numbered consecutively.

The numbers are then used as destination addresses for routing. In a second step, the local information collected is transmitted from the respective processor units to the portal processor. The overall routing table is then created in the portal processor.

According to this exemplary embodiment, measurement numbering messages are used to number all processor units in the pixel arrangement 1800, 2100. The prerequisite is that the throughput of the respective processor units has already been determined, for example in accordance with the partial method described above.

The partial process of numbering is carried out by the portal processor by sending measurement numbering messages 4301 via the output channels of the

Portal processor, which are transmitted to the initiating processor units, started.

If throughputs di, d ₂ , d ₃ , ... have been determined for the corresponding neighboring processor units, then the respective measurement numbering message 4302 of the parameters 1, 1 + di, 1 + di + d, ... is also transmitted as a message parameter.

After receiving a measurement numbering message 4301 with the parameter n via the respective input channel of the processor unit (cf. FIG. 43), the Processor unit receiving MessNumbering message 4301 performed the following steps:

1. The processor unit's own number is set to the value n, which corresponds to the value of the received measurement numbering message

4301 corresponds.

2. An additional measurement numbering message 4302 generated by the processor unit is generated over all output channels of the processor unit and with the

Parameters n + 1, n + dι + 1, n + dι + d + l,. , ,

sent, where di, d ₂ , ... are the throughputs of the corresponding neighboring processor units.

The partial process terminates when the last processor has been numbered by the last processor unit. The number of time cycles required to carry out the partial method corresponds to the maximum distance of a processor unit via channels from the portal processor. Until the last message communication "dies", one or two more clock cycles may also be required in this partial method.

44 and 45 show the pixel arrangements 1800 (FIG. 44) and 2100 (FIG. 45) after the individual processor units have been numbered within the respective pixel arrangement.

The number of a processor unit can simply be used as an address for routing data or images, since a processor unit is assigned a unique number interval for each output channel. each The processor unit can thus create a simple routing table.

In the example of FIG. 45, for example, the table for the processor unit numbered 123 is as shown in the routing table 4600 in FIG. 46.

The locally generated information is communicated to the portal processor by means of MessCollectlnfo messages, which contain the following message parameters:

The position of the respective processor unit within the respective pixel arrangement, that is to say the row and the column in which the processor unit is located,

• the pixel number, • the distance value with which the distance of the

Processor unit is specified by the portal processor,

• the color difference, and

• the throughput of the processor unit.

The MessCollectlnfo messages are from the

Processor units are sent as soon as the respective processor unit has been numbered.

With this information the pixel processor can on the one hand map pixel images onto the real pixel field (sampling) and on the other hand route this image data with the help of the pixel numbers.

When sending an overall image, that is, when feeding the data to all processor units, the

Messages sent first that have the longest route, as explained above in the description of the graph-theoretical basics.

The routing duration with which the routing trees are evaluated then also results directly from this routing table. With the help of the pixel numbers and the routing tables described above, a pixel image can be sent in a very simple manner when the display continues to operate. For this purpose, the portal processor sends messages of the type MessRGB with the following parameters:

• The number of the pixel to be addressed and

The color information for this pixel, for example red-green-blue values.

Fig. 47 shows an example of an image representation on the pixel arrangement. Of course, the display is independent of the selected routing tree.

The selection and evaluation of routing matrices was described previously, that is to say essentially of routing routes. The evaluation criterion was the routing duration. Since a real combinatorial optimization cannot usually be carried out in a short time due to the complexity, an alternative was presented above.

The freely selectable parameter is the weight g. For (partial) optimization of the routing duration, this process can also be carried out several times by the portal processor with different weights g.

Usually the weights g = 0, 1, 2, 3, ... will be considered and examined.

These have proven to be advantageous in numerical considerations. The routing that has the shortest routing duration can then finally be used.

In order to be able to carry out the process several times, the portal processor uses the message MessRetry, which deletes all channels, color regions and color distances, as in Fig. 48 is shown. To terminate the process, the MessRetry message is provided with the parameter "stamp", the value of which is not identical to the corresponding stored parameter of the processor unit. In other words, the portal processor uses a different parameter "stamp" each time it is reset.

When an incoming MessRetry message 4801 is received with the "stamp" parameter, the following steps are carried out by the respective processor unit receiving the MessRetry message 4801:

1. If the own stamp parameter is identical to the stamp parameter "stamp" contained in the MessRetry message, the processing is ended.

2. The own stamp parameter is set to the value of the stamp parameter value "stamp" contained in the MessRetry message.

3. All numbering, channels, color regions, color distances and token blocks are deleted.

4. Additional MessRetry messages 4802 are transmitted over all connections, with the exception of the connection to the processor unit sending the MessRetry message, as shown in FIG.

During the operation of the pixel arrangement, errors can occur due to wear and tear which were not present at the time of the self-organization described above. Additional messages can be used to self-identify these errors.

According to the model assumptions shown above, from the point of view of a local processor, an error can only consist in the fact that a previously connected neighboring processor is no longer is achievable. However, it cannot judge whether only the connection to this neighboring processor or whether the neighboring processor itself has failed. In the event of such an occurrence, however, an error message, hereinafter referred to as the MessError message, can be sent to the portal processor, which identifies it itself, preferably using its own pixel number as the message parameter and which additionally contains the number of the newly failed connection.

A possible reaction of the portal processor to such a message is a global reset of the pixel arrangement with the help of a measurement reset message.

In response to this message, each pixel processor forwards this message to all neighboring processors and deletes all data that have been determined in the organization. To terminate this process, each pixel processor should adhere to a certain dead time, before which it does not react to further messages. The dead time prevents the distribution of the MessReset message from being repeated an infinite number of times.

In summary, Fig. 51 gives an overview of the messages used and their respective parameters.

In this context, it should be noted that the message catalog can of course be functionally expanded by any additional messages.

FIG. 49 shows an additional exemplary embodiment of the invention, in which the processor units 4901 are arranged in a matrix in a first hierarchical level and are fully meshed with one another. The processors 4901 of the pixel arrangement 4900 in this case have a square, preferably a square shape and are controlling and reading coupled with a group of pixels, that is, pixels or sensor elements.

According to this exemplary embodiment, each processor for controlling or reading out 4 * 4 pixels 4902, which are each grouped into a pixel block 4903, is coupled.

As shown above, the individual pixel group processors are networked with one another in an orthogonal network by local closest-neighbor connections 4904.

One or more connections can run between two processors 4901, for example, to enable bidirectional data transmission or separate distribution of the supply voltages. As explained above, the layer of pixels 4902 contains the individual pixel elements, each pixel block 4903 being controlled by means of a conventional matrix control, as is shown, for example, in FIG. 50.

The matrix controller 5000 in FIG. 50 shows an example of a pixel block 5001 and a column addressing unit, which is designed as a shift register 5002, and a row addressing unit 5003, which is also designed as a shift register. The data are fed via a data source 5004 to the input of the shift register 5001 of the column addressing unit and to a clock generation unit 5005, which is connected on the output side to the

Input of the column addressing unit 5003 is coupled.

In this way, the vertical wiring effort between the two levels, the processor level and the pixel level is kept low, since only one serial

Data transmission is carried out over only one line, the clock signals also being obtained from the data signal itself.

In this context, it should be noted that more than two levels can be present, that is to say groups of pixel group processors can in turn be combined into groups, so that there is a deeper hierarchical tree structure.

As in the figure, the pixel group processors can be meshed orthogonally with one another, but other meshings are also possible, in particular a hexagonal meshing as explained above.

The pixel group processors can also exchange your messages in any format. However, they preferably exchange message blocks with one another, which may contain address codes, for example, with the aid of which the image information contained in data packets can then be passed from processor to processor. Defects in the matrix can also be avoided in this way, which is not possible with rigid x / y addressing via row lines and column lines.

Depending on the performance of the pixel group processors, in addition to the information transfer and

Information distribution also take on other tasks, such as compression or decompression of

Image information.

The architecture can also be used for large-area sensor arrays, such as fingerprint sensors, touchpads or

Font recognition sensors are used.

For example, each pixel group processor can wait for an event, i.e., input with a pen, etc., to occur in a pixel group and then this data send or route to the edge of the respective matrix. In this way it can be avoided that the entire sensor surface must always be scanned by an external addressing unit. This clearly corresponds to a local triggering by an event instead of a global image evaluation.

The pixel group processors can, for example, be converted into a suitable one with the aid of a technique such as, for example, the fluidic soap assembly as described in [3]

Carrier substrate are introduced, as described according to the first embodiment.

The connections between the processors and the sensor or display matrices can then be applied to the carrier substrate with the processors in further process steps.

The upper functional layers can preferably be implemented by means of printable circuits such as are provided in polymer electronics.

It should be noted that the partial processes described above can all be carried out independently of one another, ie independently. You only need the input information required for the respective sub-procedure. However, it is fundamentally irrelevant how the required input information has been determined. Nevertheless, the considerable advantages in the context of the intermeshing and joint implementation of several or all partial methods must be pointed out, since in this case the concept described above is implemented throughout. The following publications are cited in this document:

[1] T.J. Nelson and J.R. Wullert, Electronic Information Display Technologies, World Scientific, Chapter 8.2, 1997

[2] K. Amundson, Microencapsulated Electrophoretic Materials for Electronic Paper Displays, International Display Research Conference, 2000

[3] J.S. Smith, high density, low parasitic direct

Integration by Fluidic Self-Assembly (FSA), IEDM, pp. 201 - 204, 2000

LIST OF REFERENCE NUMBERS

100 pixel arrangement

101 substrate

102 deepening

103 processor unit

300 image display system

301 source

302 Display unit portal

303 pixel arrangement

401 bidirectional communication interfaces

402 Electrical wire

501 bidirectional communication interfaces

502 Electrical line

600 First alignment

601 Second alignment

603 Third direction

604 Fourth Alignment

605 Fifth Alignment

606 Sixth alignment

700 Directed graph

701 Undirected graph

800 directed tree

900 undirected graph

901 Directional Pixel Map Graph

902 portal nodes

903 knots

904 supply line

905 edge 1000 Permitted Tree

1001 portal nodes

1100 tree

1201 message

1202 portal nodes

1203 introductory pixel processors

1204 First inner knots

1401 First pixel processor

1402 second pixel processor

1403 Bidirectional communication interface first pixel processor

1404 Bi-directional communication interface second pixel processor

1405 supply line

1406 First message

1407 Second message

1500 processor unit

1501 measurement coherence message

1601 measurement coherence message

1602 measurement coherence message

1603 MessKoherenz message

1604 Measurement coherence message

1605 MessKoherenz message

1606 measurement coherence message

1701 measurement position message

1702 measurement position message

1703 measurement position message

1704 Measurement position message

1705 measurement position message

1706 measurement position message 1800 processor arrangement

1801 pixel processor

1901 MessDistance message

1902 MessDistance message

1903 MessDistance message

1904 MessDistance message

1905 MessDistance message

1906 MessDistance message

2001 processor unit

2002 Bottom line processor arrangement

2003 Southwest side processor unit

2100 processor arrangement

2101 Bottom line processor arrangement

2102 processor units that are not coupled to the portal processor

2103 processor units which are coupled to the portal processor

2201 MessOrganize message

2202 MessOrganize message

2203 MessOrganize message

2204 MessOrganize message

2205 MessOrganize message

2206 MessOrganize message

2600 horizontal crack

2700 horizontal crack

2801 Incoming MessCountNodes message

2802 MessCountNodes message sent

2901 First incoming MessNodesSize message

2902 Second incoming MessNodesSize message 2903 Sent MessNodesSize message

3201 MessColDistance message

3202 MessColDistance message

3203 MessColDistance message

3204 MessColDistance message

3205 MessColDistance message

3206 MessColDistance message

3301 MessBlockToken message received

3302 MessBlockToken message sent

3401 Incoming MessToken message

3402 MessBlockToken message sent

3403 MessBlockToken message sent

3404 MessBlockToken message sent

3405 MessBlockToken message sent

3406 MessBlockToken message sent

3601 Incoming MessDeleteChannels message

3602 Sent MessDeleteChannels message

3603 Sent MessDeleteChannels message

3604 Sent MessDeleteChannels message 3605 Sent MessDeleteChannels message 3606 Sent MessDeleteChannels message

3701 Incoming MessColOrganize message

3702 Sent MessColOrganize message

3703 Sent MessColOrganize message

3704 Sent MessColOrganize message

3705 Sent MessColOrganize message

3706 Sent MessColOrganize message

3801 meander path

3901 Meander path 4301 Incoming MessNumbering message

4302 MessNumbering message sent

4600 routing table

4801 Incoming MessRetry message

4802 MessRetry message sent

4900 pixel arrangement

4901 processor unit

4902 pixels

4903 block of pixels

5000 matrix control

5001 block of pixels

5002 shift registers

5003 line addressing unit

5004 data source

5005 clock generation unit

Claims

claims

1. Method for determining a distance from processor units to at least one reference position in a processor arrangement with a multiplicity of processor units, each processor unit being coupled to at least one adjacent processor unit via a bidirectional communication interface, and wherein messages are exchanged between adjacent processor units,

In which a first message is generated by a first processor unit, the first message containing first distance information which contains the distance of the first processor unit or the distance of a second processor unit receiving the first message from the reference position,

In which the first message is sent from the first processor unit to the second processor unit,

In which, depending on the distance information, the distance of the second processor unit from the reference position is determined or stored, and

In which a second message is generated by the second processor unit, which is a second

Contains distance information, which contains the distance of the second processor unit or the distance of a third processor unit receiving the second message from the reference position, • in which the second message from the second

Processor unit is sent to the third processor unit,

In which the distance of the third processor unit from the reference position is determined or stored depending on the second distance information, In which the method steps are carried out for all processor units in the pixel arrangement.

2. The method according to claim 1, wherein each processor unit is coupled to at least one pixel, so that the pixel can be controlled by the respective processor unit assigned to it.

3. The method according to claim 2, wherein at least some of the pixels are each configured as a sensor.

4. The method according to claim 2, wherein at least some of the pixels are each configured as an imaging element.

5. The method according to any one of claims 1 to 4,

In which the processor units are each arranged in a hexagonal area, and

In which each processor unit has six adjacent processor units, each of which is coupled to the processor unit via a bidirectional communication interface.

6. The method according to any one of claims 1 to 5, wherein the pixels have a hexagonal shape.

7. The method according to any one of claims 1 to 4, • in which the processor units are each arranged in a rectangular area, and

In which each processor unit has four adjacent processor units, each of which is coupled to the processor unit via a bidirectional communication interface.

8. The method according to any one of claims 1 to 4 or 7, where the pixels have a rectangular shape.

9. The method according to any one of claims 1 to 8, wherein the local positions of the prior to determining the distance of the pixel processors from the reference position

Processor units within the processor arrangement are determined by, starting from a processor unit at an introduction point of the processor arrangement, position determination messages which have at least one row parameter z and one column parameter s, which contain the row number or column number of the processor unit sending the message or the Contains the line number or column number of the processor unit receiving the message within the processor arrangement, is transmitted to neighboring processor units and the following steps are carried out by the respective processor unit:

If the column parameter in the received message is larger than the processor unit's own column number, the stored column number is assigned the row parameter value of the received message,

• If the own line number and / or the own column number have been changed due to the above-described method steps, new position measurement messages are generated with new line parameters and new column parameters, which each contain the line number and column number of the processor unit sending the message or the line number and column number of the processor unit receiving the message, and these are transmitted via the bidirectional communication interfaces to a respective neighboring processor unit.

10. The method according to any one of claims 1 to 9,

In which the own distance value of the processor unit is changed in an iterative method if the previously stored distance value is greater than the distance value received in the respective received message increased by a predetermined value, and

• In the event that a processor unit changes its own distance value, it generates a distance measurement message and across all

Sends communication interfaces to neighboring processor units, the distance measurement message each containing the own distance as distance information or the distance value that the received processor unit has from the portal processor,

11. The method according to claim 10, wherein the distance value is a value increased by a predetermined value compared to the own distance value

12. Processor arrangement with a large number of processor units,

Wherein each processor unit is coupled to at least one adjacent processor unit via a bidirectional communication interface and wherein messages are exchanged between adjacent processor units to determine the respective distance of a processor unit of the processor arrangement from a reference position,

Wherein each message contains distance information which indicates the distance of a processor unit sending the message or the distance of a processor unit receiving the message from the reference position, and

• wherein each processor unit is set up in such a way that from the distance information of a received one Message the own distance to the reference position can be determined or saved.